Prosecution Insights
Last updated: August 18, 2026
Application No. 18/165,292

METHOD OF EXECUTING DESIGN FLOW WITH MACHINE LEARNING TECHNIQUES

Final Rejection §103
Filed
Feb 06, 2023
Examiner
NGUYEN, NHA T
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
929 granted / 1066 resolved
+19.1% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
19 currently pending
Career history
1081
Total Applications
across all art units

Statute-Specific Performance

§101
14.7%
-25.3% vs TC avg
§103
28.9%
-11.1% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
14.7%
-25.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1066 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION This Office Action responds to the amendment filed 6/24/2026. Claims 1-20 are pending. Response to Applicant’s Remarks 3. With respect to Applicant’s remarks, the following are addressed: Applicant’s arguments with respect to claim(s) have been considered but are moot in view of new ground of rejection, as follow: Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Najibi et al. (U.S. Pub. No. 12,417,336 B1) in view of Chuang et al. (U.S. Pub. No. 2020/0104457 A1). In the current rejection, newly cited prior art reference Chuang teaches that two designs are converted into vectors for similarity comparison. Therefore, the combination of Chuang and Najibi discloses all limitations of the claims, as set forth below. The rejection of the claims are as cited below. This office action is Final. Claim Rejections - 35 USC § 103 4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 5. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Najibi et al. (U.S. Pub. No. 12,417,336 B1) in view of Chuang et al. (U.S. Pub. No. 2020/0104457 A1). As per claim 1, Najibi discloses: A method comprising: constructing a set of reference design contents associated with a set of reference design recipes (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation –[prior art include previous circuit design considered as the reference design and setting of the previous circuit design considered as the recipe]) determining a content similarity between a user design content and a reference design content taken from the set of reference design contents (See Col 7; Line 16-42, i.e. how similar a prior design session compared to the current design session, See Col 13; Lines 1-25, i.e. identify similarities between the current circuit design and the one or more previous circuit designs); and executing a design flow specified by a reference design recipe associated with the reference design content, as a result of the content similarity reaching a predetermined threshold (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10 –[prior art use settings from previous design for current design, considered as the design flow specified by the reference design recipe as cited above]). Najibi does not teach the limitations: wherein determining the content similarity comprises transforming the user design content into a first vector and transforming the reference design content into a second vector. However, Chuang teach the limitations: wherein determining the content similarity comprises transforming the user design content into a first vector and transforming the reference design content into a second vector (See Para [0063], i.e. machine learning circuitry 110 may analyze the received training data 120 and/or the information stored in the systematic DRC database 112 and may identify or generate the clustered DRC patterns using cosine similarity…Cosine similarity, in general, is a measure of similarity between two non-zero vectors of an inner product space that measures the cosine of the angle between them… by comparing cosines of angles between a plurality of vectors). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Chuang into the teaching of Najibi because it would allow designer to determine design violations in a placement layout before routing of the layout (See Para [0025]). As per claim 2, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein each reference design content is associated with a reference design recipe in the set of reference design recipes (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation). As per claim 3, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the reference design content from content parameters that include one or more design recipe parameters in the reference design recipe (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation). As per claim 4, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses constructing the user design content from content parameters that include one or more design recipe parameters in a user design recipe (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10). As per claim 5, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the reference design content from a reference design flow based on one or more content parameters which specify a technology targeted by the reference design flow (See Col 6; Line 1-35, i.e. library cell choices…IC size, IC aspect ratio, See Col 14; Lines 23-35, i.e. optimized for a target semiconductor manufacturing technology). As per claim 6, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the user design content from a user design flow based on one or more content parameters which specify a technology targeted by the user design flow (See Col 6; Line 1-35, i.e. library cell choices…IC size, IC aspect ratio, See Col 14; Lines 23-35, i.e. optimized for a target semiconductor manufacturing technology). As per claim 7, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses fetching the reference design content from a database (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation, See Col 1; Line 45-67, i.e. searching a database for data associated with previous design sessions). As per claim 8, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein executing the design flow comprises: optimizing the design flow while carrying out a machine learning session (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10, See Abstract, i.e. using machine learning to modify a current circuit design is provided). As per claim 9, Najibi discloses all of the features of claim 1 as discloses above wherein Najibi also discloses wherein executing the design flow comprises: executing the design flow based on a reference machine learning model associated with the reference design content (See Col 6; Lines 1-35, i.e. multiple machine learning strategies including incrementally searching entire search spaces…implemented learning strategies can be changed or adjusted based on how similar a prior search is with respect to a current design). As per claim 10, Najibi discloses all of the features of claim 9 as discloses above wherein Najibi also discloses fetching the reference design content and the reference machine learning model from a database (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation, See Col 1; Line 45-67, i.e. searching a database for data associated with previous design sessions). As per claim 11, Najibi discloses: A non-transitory machine-readable medium having instructions stored thereon, instructions being configured to cause a system having at least one processor to execute (See Figure 7, i.e. static memory and processing device): constructing a set of reference design contents associated with a set of reference design recipes (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation –[prior art include previous circuit design considered as the reference design and setting of the previous circuit design considered as the recipe]); determining a content similarity between a user design content and a reference design content taken from the set of reference design contents (See Col 7; Line 16-42, i.e. how similar a prior design session compared to the current design session, See Col 13; Lines 1-25, i.e. identify similarities between the current circuit design and the one or more previous circuit designs); and executing a design flow specified by a reference design recipe associated with the reference design content, as a result of the content similarity reaching a predetermined threshold (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10 –[prior art use settings from previous design for current design, considered as the design flow specified by the reference design recipe as cited above]). Najibi does not teach the limitations: wherein determining the content similarity comprises transforming the user design content into a first vector and transforming the reference design content into a second vector. However, Chuang teach the limitations: wherein determining the content similarity comprises transforming the user design content into a first vector and transforming the reference design content into a second vector (See Para [0063], i.e. machine learning circuitry 110 may analyze the received training data 120 and/or the information stored in the systematic DRC database 112 and may identify or generate the clustered DRC patterns using cosine similarity…Cosine similarity, in general, is a measure of similarity between two non-zero vectors of an inner product space that measures the cosine of the angle between them… by comparing cosines of angles between a plurality of vectors). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Chuang into the teaching of Najibi because it would allow designer to determine design violations in a placement layout before routing of the layout (See Para [0025]). As per claim 12, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein each reference design content is associated with a reference design recipe in the set of reference design recipes (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation). As per claim 13, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the reference design content from content parameters that include one or more design recipe parameters in the reference design recipe (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation). As per claim 14, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein the instructions is configured to cause the system further to execute: constructing the user design content from content parameters that include one or more design recipe parameters in a user design recipe (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10). As per claim 15, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the reference design content from a reference design flow based on one or more content parameters which specify a technology targeted by the reference design flow (See Col 6; Line 1-35, i.e. library cell choices…IC size, IC aspect ratio, See Col 14; Lines 23-35, i.e. optimized for a target semiconductor manufacturing technology). As per claim 16, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein constructing the set of reference design contents comprises: constructing the user design content from a user design flow based on one or more content parameters which specify a technology targeted by the user design flow (See Col 6; Line 1-35, i.e. library cell choices…IC size, IC aspect ratio, See Col 14; Lines 23-35, i.e. optimized for a target semiconductor manufacturing technology). As per claim 17, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein the instructions is configured to cause the system further to execute: fetching the reference design content from a database (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation, See Col 1; Line 45-67, i.e. searching a database for data associated with previous design sessions). As per claim 18, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein executing the design flow comprises: optimizing the design flow while carrying out a machine learning session (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10, See Abstract, i.e. using machine learning to modify a current circuit design is provided). As per claim 19, Najibi discloses all of the features of claim 11 as discloses above wherein Najibi also discloses wherein executing the design flow comprises: executing the design flow based on a reference machine learning model associated with the reference design content (See Col 6; Lines 1-35, i.e. multiple machine learning strategies including incrementally searching entire search spaces…implemented learning strategies can be changed or adjusted based on how similar a prior search is with respect to a current design). As per claim 20, Najibi discloses: A system for manufacturing a semiconductor device, the system comprising: at least one processor; at least one non-transitory computer readable medium that stores computer executable code; and the at least one non-transitory computer readable medium, the computer executable code and the at least one processor being configured to cause the system (See Figure 7, i.e. static memory and processing device) to: construct a set of reference design contents associated with a set of reference design recipes (See Col 44 to Col 6; Line 35, i.e. learning from data previously collected from IC designer’s modification session…every permutton setting…software setting…design settings, See Col 7; Line 16 to Col 8 ; Line 58, i.e. different relevance setting … previous circuit design … high relevance , See Col 8; Line 59 to Col 10; Line 10, See Col 13; Line 1-25, i.e. previous circuit design…setting related to a simulation –[prior art include previous circuit design considered as the reference design and setting of the previous circuit design considered as the recipe]), determine a content similarity between a user design content and a reference design content taken from the set of reference design contents (See Col 7; Line 16-42, i.e. how similar a prior design session compared to the current design session, See Col 13; Lines 1-25, i.e. identify similarities between the current circuit design and the one or more previous circuit designs), and execute a design flow specified by a reference design recipe associated with the reference design content, as a result of the content similarity reaching a predetermined threshold (See Col 13; Lines 1-25, i.e. apply values obtained from the simulation data…setting related to a simulation, See Col 7; Line 16 to Col 8 ; Line 58, i.e. if there is high relevance 112, a very similar previous circuit design was found and the system can use the same permuton settings, See Col 8; Line 59 to Col 10; Line 10 –[prior art use settings from previous design for current design, considered as the design flow specified by the reference design recipe as cited above]). Najibi does not teach the limitations: transform a user design content into a first vector and transform a reference design content into a second vector, wherein the reference design content is taken from the set of reference design contents, determining a content similarity based on a calculation with the first vector and the second vector. However, Chuang teach the limitations: transform a user design content into a first vector and transform a reference design content into a second vector, wherein the reference design content is taken from the set of reference design contents, determining a content similarity based on a calculation with the first vector and the second vector (See Para [0063], i.e. machine learning circuitry 110 may analyze the received training data 120 and/or the information stored in the systematic DRC database 112 and may identify or generate the clustered DRC patterns using cosine similarity…Cosine similarity, in general, is a measure of similarity between two non-zero vectors of an inner product space that measures the cosine of the angle between them… by comparing cosines of angles between a plurality of vectors). Therefore, it would have been obvious to a person of ordinary skill in the art at the effective filing date of the invention to incorporate the teaching of Chuang into the teaching of Najibi because it would allow designer to determine design violations in a placement layout before routing of the layout (See Para [0025]). Conclusion 6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NHA T NGUYEN/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Feb 06, 2023
Application Filed
Feb 26, 2026
Non-Final Rejection mailed — §103
Jun 24, 2026
Response Filed
Jul 15, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+18.4%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1066 resolved cases by this examiner. Grant probability derived from career allowance rate.

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