DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 5-6, 9-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (PG Pub. No. US 2019/0305099 A1) in view of Pan et al. (PG Pub. No. US 2022/0320088 A1).
Regarding claim 1, Jo teaches a semiconductor device (figs. 1-7 & 15-27 among others) comprising:
a first active pattern (¶ 0024: 110) extending in a first direction on a substrate (fig. 1: 110 extends in X direction);
a second active pattern (¶ 0024: 310) extending in the first direction on the substrate (fig. 1: 310 extends in X direction), the second active pattern spaced apart from the first active pattern in a second direction (fig. 1: 110 spaced apart from 310);
a field insulating film (¶ 0029: 105) between the first active pattern and the second active pattern on the substrate (figs. 5, 26: 105 disposed between 110 and 310);
a first gate electrode (¶ 0032: 130) intersecting the first active pattern on the substrate (figs. 1, 5, 26: 130 intersects 110 and 310);
a second gate electrode (¶ 0032: 230) intersecting the second active pattern on the substrate (figs. 1, 5, 26: 230 intersects 110 and 310); and
a gate separation structure (¶ 0046: 170, including portions 160 and 180) on the field insulating film (figs. 5, 26: portion 160 disposed on 105), the gate separation structure separating the first gate electrode and the second gate electrode from each other (fig. 5, 26: portion 160 separates 130 and 230), the gate separation structure including a plurality of insulating films (fig. 5, 26: 161, 162).
Jo fails to teach the plurality of insulating films comprising first sub-insulating films and at least one second sub-insulating film, and the at least one second sub-insulating film between the first sub-insulating films, wherein in a third direction perpendicular to the first direction and to the second direction, at least one first sub-insulating film of the plurality of first sub-insulating films overlaps with the at least one second sub-insulating film.
Pan teaches a semiconductor device (figs. 28-29 among others) including a gate separation structure (¶ 0031: 260 and 280B, similar to 170 of Jo) on a field insulating film (¶ 0031 & figs. 28-29: 260/280B formed on isolation feature 255, similar to 105 of Jo), the gate separation structure separating a first gate electrode and a second gate electrode from each other (¶ 0056 & figs. 28-29: 260/280B separate gates 370A and 370B, similar to 130 and 230 of Jo). Pan further teaches the gate separation structure including a plurality of first sub-insulating films (¶¶ 0026, 0029: 262, 272, and/or 274) and at least one second sub- insulating film (¶ 0026: 264), the at least one second sub-insulating film between the first sub-insulating films (figs. 28-29: 264 arranged between 262 and 272/274),
wherein in a third direction perpendicular to the first direction and to the second direction, at least one first sub-insulating film of the plurality of first sub-insulating films overlaps with the at least one second sub-insulating film (figs. 28-29: in a vertical direction, at least one of 262 and 272/274 overlaps 264).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the plurality of insulating films of Jo with a vertical overlap, as a means to provide isolation structures with different heights (Pan, 280A and 260/280B), increasing functionality by allowing for gate interconnection structures (Pan, 374A/374B) as well as gate isolation structures.
Regarding claim 3, Jo in view of Pan teaches the semiconductor device of claim 1, wherein
the first active pattern is included in a first channel region of a transistor (Jo, ¶ 0043),
the second active pattern is included in a second channel region of the transistor (Jo, ¶ 0043),
the first channel region and the second channel region have a same conductive type (Jo, ¶ 0028: in at least one embodiment, 110 and 310 comprise same materials and dopants),
the gate separation structure includes a first sidewall facing the first active pattern and a second sidewall facing the second active pattern (Jo, fig. 5 among others: 160 includes sidewalls facing 110 and second sidewall facing 310), and
a distance of an uppermost surface of the gate separation structure in the second direction from a central axis to the first sidewall, is same as a distance of the uppermost surface of the gate separation structure in the second direction from the central axis to the second sidewall (Jo, fig. 5: distance of center of upper surface of 160 equidistant to each sidewall).
Regarding claim 5, Jo in view of Pan teaches the semiconductor device of claim 1, further comprising a gate insulating film (Jo, ¶ 0032: 135) between the first gate electrode and the first active pattern (Jo, fig. 5 among others: 135 disposed between 130 and 110),
wherein the gate insulating film is between the second gate electrode and the second active pattern (Jo, fig. 5 among others: 135 disposed between 230 and 310), and
the gate insulating film does not extend along a sidewall of the gate separation structure (Jo, fig. 5: 135 does not extend along sidewall of 160).
Regarding claim 6, Jo in view of Pan teaches the semiconductor device of claim 1, wherein the plurality of first sub-insulating films includes a silicon nitride film (Pan, ¶¶ 0026, 0030: in at least one embodiment, 262 and 274 include silicon and nitrogen, meeting the broadest reasonable interpretation of ‘silicon nitride’), and
the second sub-insulating film includes an oxide (Pan, ¶ 0026: 264 includes silicon oxide).
Regarding claim 9, Jo in view of Pan teaches the semiconductor device of claim 1, wherein a lowest portion of the gate separation structure is at a center between the first active pattern and the second active pattern (Jo, fig. 5: lowest portion of 160 centered between 110 and 310).
Regarding claim 10, Jo in view of Pan teaches the semiconductor device of claim 1, wherein the plurality of first sub-insulating films are convexly curved toward the field insulating film (Pan, ¶¶ 0027, 0029 & figs. 28-29: at least 262 and 272 have u-shaped profiles which face away from 255, meeting the broadest reasonable interpretation ‘convexly curved toward the field insulating film’).
Regarding claim 11, Jo in view of Pan teaches the semiconductor device of claim 1, further comprising a gate insulating film (Jo, ¶ 0032: 135) between the first gate electrode and the first active pattern (Jo, fig. 5 among others: 135 disposed between 130 and 110), wherein the gate insulating film is between the second gate electrode and the second active pattern (Jo, fig. 5 among others: 135 disposed between 230 and 310), and the gate insulating film extends along a sidewall of the gate separation structure (Jo, fig. 26: 135 extends at least indirectly along sidewall of 160).
Regarding claim 14, Jo teaches a semiconductor device (figs. 1-7 & 15-27 among others) comprising:
a first active pattern (¶ 0024: 110) extending in a first direction on a substrate (fig. 1: 110 extends in X direction);
a second active pattern (¶ 0024: 310) extending in the first direction on the substrate (fig. 1: 310 extends in X direction), the second active pattern spaced apart from the first active pattern in a second direction (fig. 1: 110 spaced apart from 310);
a field insulating film (¶ 0029: 105) between the first active pattern and the second active pattern on the substrate (figs. 8, 26: 105 disposed between 110 and 310);
a first gate electrode (¶ 0032: 130) intersecting the first active pattern on the substrate (figs. 1, 8, 26: 130 intersects 110 and 310);
a second gate electrode (¶ 0032: 230) intersecting the second active pattern on the substrate (figs. 1, 8, 26: 230 intersects 110 and 310);
a gate insulating film (¶ 0032: 135 and/or 235) between the field insulating film and the first gate electrode (fig. 8: 135/235 disposed between 105 and 130), the gate insulating film between the field insulating film and the second gate electrode (fig. 8: 135/235 disposed between 105 and 230), the gate insulating film between the first gate electrode and the first active pattern (fig. 8: 135/235 disposed between 130 and 110), and the gate insulating film between the second gate electrode and the second active pattern (fig. 8: 135/235 disposed between 230 and 310); and
a first gate separation (¶ 0046: 170, including portions 160 and 180) on the field insulating film (figs. 8, 26: portion 160 disposed on 105), the first gate separation structure separating the first gate electrode and the second gate electrode from each other (fig. 8: portion 160 separates 130 and 230),
wherein the gate insulating film does not extend along a sidewall of the first gate separation structure (fig. 8 135/235 does not extend along sidewall of portion 160), the first gate separation structure includes a plurality of insulating films including silicon nitride (¶¶ 0050, 0067: plurality of silicon nitride films 161), the first gate separation structure includes an oxide film (¶¶ 0050, 0068: 162) between the plurality of insulating films (fig. 8: 162 disposed between 161), and the plurality of insulating films and the plurality of oxide films are alternately stacked (fig. 8: 161/162 laterally stacked).
Jo does not teach a plurality of oxide films between the plurality of insulating films, the plurality of insulating films and the plurality of oxide films are alternately stacked in a third direction perpendicular to the first direction and the second direction and have a convex shape toward the field insulating film.
Pan teaches a semiconductor device (figs. 28-29 among others) including a gate separation structure (¶ 0031: 260 and 280B, similar to 170 of Jo), the gate separation structure including a plurality of oxide films (¶¶ 0026, 0030: 264, 274) between a plurality of insulating films (¶¶ 0026-0032 & figs. 28-29: 264/274 disposed between insulating films 262, 272 and/or 276), the plurality of insulating films and the plurality of oxide films are alternately stacked in a third direction perpendicular to the first direction and the second direction (figs. 28-29: 262/264/272/274/276 alternately stacked in a vertical direction) and have a convex shape toward a field insulating film (¶¶ 0027, 0029, 0064: 262/264/272/274/276 include u-shaped cross-sections facing away from isolation feature 255, meeting the broadest reasonable interpretation of ‘a convex shape toward a field insulating film’).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the plurality of insulating films of Jo with a vertical overlap, as a means to provide isolation structures with different heights (Pan, 280A and 260/280B), increasing functionality by allowing for gate interconnection structures (Pan, 374A/374B) as well as gate isolation structures.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Pan as applied to claim 1 above, and further in view of Liaw (PG Pub. No. US 2020/0126989 A1).
Regarding claim 7, Jo teaches the semiconductor device of claim 1, comprising a thickness of the plurality of first sub-insulating films and a thickness of the second sub-insulating film the third direction perpendicular to the first direction and the second direction (Jo, fig. 5 among others: vertical thickness of 161 and 162).
Jo in view of Pan does not teach wherein the thickness of the plurality of first sub-insulating films is greater than the thickness of the second sub-insulating film.
Liaw teaches a semiconductor device (¶ 0028: 100) including a gate separation structure (¶ 0031: 114b), the gate separation structure including a first sub-insulating film (¶ 0031: 136b) and a second sub-insulating film (¶ 0031: 134b), wherein in a third direction perpendicular (Z axis direction) to a first direction and a second direction (X axis direction and Y axis direction of fig. 15), a thickness of the plurality of first sub-insulating films is greater than a thickness of the second sub-insulating film (fig. 30 among others: vertical thickness of 136b greater than vertical thickness of 134b).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the gate separation structure of Jo in view of Pan with the sub-insulating film thicknesses of Liaw, as a means to maintain a height of the gate separation structure and reduce gate coupling capacitance (Liaw, ¶ 0040).
Claims 8, 12-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Jo in view of Pan as applied to claims 1 and 14 above, and further in view of Paul et al. (PG Pub. No. US 2021/0020644 A1).
Regarding claim 8, Jo in view of Pan teaches the semiconductor device of claim 1, wherein the first active pattern includes a first lower pattern extending in the first direction (Jo, figs. 1, 5: 110 includes a lower pattern extending in the X direction), and
the second active pattern includes a second lower pattern extending in the first direction (Jo, figs. 1, 5: 310 includes a lower pattern extending in the X direction).
Jo in view of Pan further teaches non-illustrated embodiments including nano-wire and/or nano-sheet transistors (Jo, ¶ 0021).
Jo in view of Pan does not teach wherein the first active pattern further includes a first sheet pattern spaced apart from the first lower pattern, and
the second active pattern further includes a second sheet pattern spaced apart from the second lower pattern.
Paul teaches a semiconductor device (fig. 11 among others) including a first active pattern (¶ 0030: 120N) comprising a first sheet pattern (¶ 0052: nanosheets 320N) spaced apart from a first lower pattern (fig. 9: 320N arranged over a fin-shaped portion of substrate 112), and
a second active pattern (¶ 0030: 220P) comprising a second sheet pattern (¶ 0052: nanosheets 420P) spaced apart from the second lower pattern (fig. 9: 420P arranged over a fin-shaped portion of substrate 112).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the active patterns of Jo in view of Pan with the sheet patterns of Paul, as a means to provide a gate all around configuration, creating more surface area and better control (Paul, ¶ 0004).
Regarding claim 12, Jo in view of Pan teaches the semiconductor device of claim 1, wherein the gate separation structure has an asymmetric structure with respect to a central axis of an uppermost surface of the gate separation structure in the second direction (Jo, fig. 27: 170 includes an asymmetric structure with respect to a central axis an uppermost surface of portion 160).
Jo in view of Pan does not teach the first active pattern is in a PMOS region, the second active pattern is in an NMOS region.
Paul teaches a semiconductor device (fig. 11 among others) including a gate separation structure (¶ 0031: gate cut isolation 130) separating first and second regions (¶ 0030: 90, 92), the first region comprising an active region (¶ 0042: 122N) of an NMOS (120N) and the second region comprising an active region (¶ 0047: 222P) a PMOS (220P).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the active patterns of Jo in view of Pan in respective PMOS and NMOS regions, as a means to provide an integrated circuit (IC), comprising a static random access memory (Paul, ¶ 0008), increasing functionality of the device.
Regarding claim 15, Jo in view of Pan teaches the semiconductor device of claim 14, wherein the first gate separation structure has an asymmetric structure with respect to a central axis of an uppermost surface of the first gate separation structure in the second direction (Jo, fig. 27: 170 includes an asymmetric structure with respect to a central axis an uppermost surface of portion 160).
Jo in view of Pan does not teach the first active pattern is in a PMOS region, the second active pattern is in an NMOS region.
Paul teaches a semiconductor device (fig. 11 among others) including a gate separation structure (¶ 0031: gate cut isolation 130) separating first and second regions (¶ 0030: 90, 92), the first region comprising an active region (¶ 0042: 122N) of an NMOS (120N) and the second region comprising an active region (¶ 0047: 222P) a PMOS (220P).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the active patterns of Jo in view of Pan in respective PMOS and NMOS regions, as a means to provide an integrated circuit (IC), comprising a static random access memory (Paul, ¶ 0008), increasing functionality of the device.
Regarding claim 16, Jo in view of Pan and Paul teaches the semiconductor device of claim 15, wherein the first gate separation structure includes a first sidewall facing the first active pattern and a second sidewall facing the second active pattern (Jo, figs. 8, 27 among others: portion 160 includes first sidewall facing at least one active pattern 110 and second sidewall facing second active pattern 310), and
at a same height in the third direction perpendicular to the first direction and the second direction, a first distance between the first sidewall and the first active pattern is smaller than a second distance between the second sidewall and the second active pattern (Jo, fig. 1: distance between first sidewall of 160 and 130 smaller than distance between second sidewall of 160 and distal active pattern 110).
Regarding claim 16, Jo in view of Pan and Paul teaches the semiconductor device of claim 15, wherein the first gate separation structure includes a first sidewall facing the first active pattern and a second sidewall facing the second active pattern (Jo, figs. 8, 27 among others: portion 160 includes first sidewall facing at least one active pattern 110 and second sidewall facing second active pattern 310), and
at a same height in the third direction perpendicular to the first direction and the second direction, a first distance between the first sidewall and the first active pattern is smaller than a second distance between the second sidewall and the second active pattern (Jo, fig. 1: distance between first sidewall of 160 and 130 smaller than distance between second sidewall of 160 and distal active pattern 110).
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Allowable Subject Matter
Claims 4 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“a distance of an uppermost surface of the gate separation structure in the second direction from a central axis to the first sidewall is greater than a distance of the uppermost surface of the gate separation structure in the second direction from the central axis to the second sidewall, and
the central axis is a straight line that vertically intersects the center of an upper surface of the gate separation structure” as recited in claim 4, and
“at a same height in a third direction perpendicular to the first direction and the second direction, the second width is smaller than the first width and the second width is greater than the third width” as recited in claim 17.
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowance: The prior art fails to teach or clearly suggest the limitations stating:
“at a same height in a third direction perpendicular to the first direction and the second direction, a first distance between the first sidewall and the first active pattern, nearest to the first sidewall,is smaller than a second distance between the second sidewall and the second active pattern nearest to the second sidewall” as recited in claim 18.
Jo teaches the semiconductor device of claim 14, comprising a second gate electrode (230), and first and second active patterns (110, 310), wherein the first gate separation structure has a first width in the second direction (fig. 8: portion 160 has width in Y direction).
Liaw teaches a semiconductor device (fig. 10 among others: 100) including
a third active pattern (¶ 0030: 112 in region 104N) extending in a first direction on a substrate (fig. 7: Y direction), the third active pattern spaced apart from a second active pattern in the second direction (fig. 10: 112 spaced apart from fin 110);
a fourth active pattern (¶ 0030: second 112) extending in the first direction on the substrate (fig. 7: Y direction), the fourth active pattern spaced apart from the third active pattern in the second direction (fig. 10: second 112 spaced apart from first 112 in X direction);
a third gate electrode (¶ 0042: 132) intersecting the third active pattern on the substrate (fig. 10: portion of 132 intersects 112);
a fourth gate electrode (¶ 0042: 132) intersecting the fourth active pattern on the substrate (fig. 10: second portion of 132 intersects second 112);
a second gate separation structure (¶ 0031: 114a) separating a second gate electrode and the third gate electrode from each other (fig. 10: 114a at least partially separates portion of 132 from additional portion of 132), the second gate separation structure having a second width in the second direction (figs. 7, 10: 114a has width in X direction); and
a third gate separation structure (¶ 0031: 114b) separating the third gate electrode and the fourth gate electrode from each other (fig. 10), the third gate separation structure having a third width in the second direction (figs. 7, 10: 114b has width in X direction),
wherein a first active pattern and the second active pattern are in a PMOS region (¶ 0030 & fig. 10: 110 disposed in PMOS region), the third active pattern and the fourth active pattern are in an NMOS region (¶ 0030 & fig. 10: 112 disposed in NMOS region).
However, neither Jo nor Liaw, either alone or in combination with cited prior art, teaches a distance of an uppermost surface of the gate separation structure in the second direction from the center of an upper surface of the gate separation structure to the first sidewall is greater than a distance of the uppermost surface of the gate separation structure in the second direction from the center of the upper surface of the gate separation structure to the second sidewall (required by claim 4),
at a same height in a third direction perpendicular to the first direction and the second direction, the second width is smaller than the first width and the second width is greater than the third width (required by claim 17), or
a first distance between the first sidewall and the first active pattern nearest to the first sidewall, is smaller than a second distance between the second sidewall and the second active pattern nearest to the second sidewall (required by claim 18).
In light of these limitations in the claims (see applicant’s fig. 13 & ¶ 0126), the previously applied references do not anticipate or obviate the claimed method as in the context of the claims.
Claims 19-20 depend on claim 18, are allowed for implicitly including the allowable subject matter above.
Response to Arguments
Applicant’s argument, see page 9, filed 12/4/2025, with respect to the 35 USC § 112(b) rejection of claim 4 has been fully considered and are persuasive. Accordingly, this rejection has been withdrawn.
Applicant’s arguments with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to the 35 USC § 103 rejections of claims 18-20 have been fully considered and are persuasive. Accordingly, these rejections have been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818