DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 12-13 and 16-17 in the Applicant’s response dated 22 January 2026. The claim amendments have been addressed below.
The Examiner acknowledges the cancellation of claim 4 and the addition of new claim 21 in the Applicant’s response dated 22 January 2026. The new claim has been addressed below.
The Examiner acknowledges the amendment to the specification in the Applicant’s response dated 22 January 2026 in lieu of the drawing objection presented in the previous office action. The previous drawing objection presented on 24 October 2025 has been withdrawn.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the second “another PCB” as described in claim 2, which is in addition to “another PCB” as described in claim 1, must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2, 13 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 2, the claim recites “wherein the at least one connection component includes another PCB”, wherein claim 1 recites, “at least one connection component that is configured to connect the PCB and the semiconductor package; another PCB that is disposed within the opening of the stiffener”. Therefore, it is unclear to one of ordinary skill in the art prior to the effective filing date of the claimed invention, if the recitation of “another PCB” in claim 2 describes a third PCB which couples a first PCB to a second PCB in the opening of the stiffener, or if it is the same “another PCB” as described in claim 1. For the purpose of examination, the Examiner is interpreting the “another PCB” of claim 2 as the same “another PCB” of claim 1 as the drawings of the instant application do not provide for a third PCB disposed between a first PCB and a second PCB.
Regarding Claim 13, the claim recites “wherein the at least one connection component includes another PCB”, wherein claim 12 recites, “at least one connection component that is configured to connect the PCB to at least one of the stiffener or the substrate; and another PCB that is disposed within the opening of the stiffener”. Therefore, it is unclear to one of ordinary skill in the art prior to the effective filing date of the claimed invention, if the recitation of “another PCB” in claim 13 describes a third PCB which couples a first PCB to a second PCB in the opening of the stiffener, or if it is the same “another PCB” as described in claim 12. For the purpose of examination, the Examiner is interpreting the “another PCB” of claim 13 as the same “another PCB” of claim 12 as the drawings of the instant application do not provide for a third PCB disposed between a first PCB and a second PCB.
Regarding Claim 17, the claim recites “wherein the at least one connection component includes another PCB”, wherein claim 16 recites, “at least one connection component that is configured to connect the PCB to at least one of the substrate or stiffener of the semiconductor package; and another PCB that is disposed within the opening of the stiffener”. Therefore, it is unclear to one of ordinary skill in the art prior to the effective filing date of the claimed invention, if the recitation of “another PCB” in claim 17 describes a third PCB which couples a first PCB to a second PCB in the opening of the stiffener, or if it is the same “another PCB” as described in claim 16. For the purpose of examination, the Examiner is interpreting the “another PCB” of claim 17 as the same “another PCB” of claim 16 as the drawings of the instant application do not provide for a third PCB disposed between a first PCB and a second PCB.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 12-13, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Christopher C. Jones et al. (US 2008/0142961 A1; hereinafter “Jones”) in view of Yong Joon Kim et al. (US 2021/0185815 A1; hereinafter “Kim”).
Regarding Claim 1, Jones teaches an apparatus, comprising:
a printed circuit board (PCB) (108, Fig. 2, para [0022] described a PCB 108);
a semiconductor package (104, Fig. 2, para [0022] describes a package substrate 104) disposed on a top surface of the PCB (Fig. 2 depicts wherein package substrate 104 is disposed on a top surface of the PCB 108) that includes a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of package substrate 104 that may include vias and traces) and a stiffener (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104),
wherein a top surface of the stiffener is disposed on a bottom surface of the substrate (306 and 304, Fig. 5 depicts wherein a top surface of the stiffener layers 306 are disposed on a bottom surface of the substrate layer 304),
wherein a bottom surface of the stiffener is disposed on a top surface of the PCB (104 and 306, Fig. 2 depicts wherein a bottom surface of the stiffener layers 306 comprised in package substrate 104 on either side of cavity 150 are disposed on a top surface of the PCB 108),
wherein the stiffener has an opening extending through the top surface of the stiffener and the bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface), and
wherein the PCB spans at least from one end of the stiffener to the other end of the stiffener (108, Fig. 2 depicts wherein PCB 108 spans from one end of the stiffener layers 306 comprised in package substrate 104 to the other end opposite the recess 150);
at least one connection component that is configured to connect the PCB and the semiconductor package (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104);
another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306),
wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and
wherein the stiffener surrounds the other component on all sides (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308).
Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB.
However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]).
Regarding Claim 2, the combination of Jones and Kim teaches the apparatus of claim 1, wherein the at least one connection component includes another PCB (Jones, 106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306 wherein Kim teaches a second printed circuit board 200 disposed in an opening 410H between first structures 410 which may be stiffener components wherein the resulting at least one connection component 106 would include a PCB), wherein:
a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106 including another PCB is disposed on the top surface of the PCB 108), and
a top surface of the other PCB is disposed on a bottom surface of the substrate (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106 including another PCB is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304).
Regarding Claim 3, the combination of Jones and Kim teaches the apparatus of claim 1, wherein:
the bottom surface of the other PCB is connected to the top surface of the PCB via a first ball grid array (BGA) (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the bottom surface of the connection component 106 including another PCB to a top surface of the PCB 108), and
the top surface of the other PCB is connected to the bottom surface of the substrate via a second BGA (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the top surface of the connection component 106 including another PCB to a bottom surface of the package substrate 104 comprised in the hole 308 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304).
Regarding Claim 12, Jones teaches an apparatus, comprising:
a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of a package substrate 104 that may include vias and traces);
a stiffener with an opening disposed on a bottom surface of the substrate (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104),
wherein the opening of the stiffener extends through a top surface of the stiffener and the bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface);
a printed circuit board (PCB) disposed on a bottom surface of the stiffener (108, Fig. 2, para [0022] described a PCB 108 which can be seen disposed on a bottom surface of the stiffener layers 306 of the package substrate 104 in Fig. 2),
wherein the PCB spans at least from one end of the stiffener to the other end of the stiffener (108, Fig. 2 depicts wherein PCB 108 spans from one end of the stiffener layers 306 comprised in package substrate 104 to the other end opposite the recess 150);
at least one connection component that is configured to connect the PCB to at least one of the stiffener or the substrate (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104 comprising substrate layers 302 and 304 and stiffener layers 306); and
another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306),
wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and
wherein the stiffener surrounds the other component (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308).
Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB.
However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]).
Regarding Claim 13, the combination of Jones and Kim teaches the apparatus of claim 12, wherein the at least one connection component includes another PCB (Jones, 106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306 wherein Kim teaches a second printed circuit board 200 disposed in an opening 410H between first structures 410 which may be stiffener components wherein the resulting at least one connection component 106 would include a PCB), wherein:
a top surface of the other PCB is disposed on a portion of the bottom surface of the substrate that is associated with the opening of the stiffener (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106 including another PCB is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 associated with the opening 150 of the stiffener layers 306 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304), and
a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106 including another PCB is disposed on the top surface of the PCB 108).
Regarding Claim 16, Jones teaches an apparatus, comprising:
a printed circuit board (PCB) (108, Fig. 2, para [0022] described a PCB 108);
a semiconductor package (104, Fig. 2, para [0022] describes a package substrate 104) that includes a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of package substrate 104 that may include vias and traces) and a stiffener (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104),
wherein the stiffener is disposed on a top surface of the PCB (104 and 306, Fig. 2 depicts wherein a bottom surface of the stiffener layers 306 comprised in package substrate 104 on either side of cavity 150 are disposed on a top surface of the PCB 108),
wherein the stiffener has an opening extending through the top surface of the stiffener and a bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface), and
wherein the PCB spans at least from one end of the stiffener to the other end of the stiffener (108, Fig. 2 depicts wherein PCB 108 spans from one end of the stiffener layers 306 comprised in package substrate 104 to the other end opposite the recess 150);
at least one connection component that is configured to connect the PCB to at least one of the substrate or the stiffener of the semiconductor package (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104 comprising the substrate layers 302 and 304 and stiffener layers 306); and
another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306),
wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and
wherein the stiffener surrounds the other component on all sides (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308).
Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB.
However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]).
Regarding Claim 17, the combination of Jones and Kim teaches the apparatus of claim 16, wherein the at least one connection component includes another PCB (Jones, 106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306 wherein Kim teaches a second printed circuit board 200 disposed in an opening 410H between first structures 410 which may be stiffener components wherein the resulting at least one connection component 106 would include a PCB), wherein:
a top surface of the other PCB is disposed on a portion of a bottom surface of the substrate that is associated with the opening of the stiffener (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106 including another PCB is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 associated with the opening 150 of the stiffener layers 306 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304), and
a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106 including another PCB is disposed on the top surface of the PCB 108).
Regarding Claim 21, the combination of Jones and Kim teaches the apparatus of claim 1, wherein the bottom surface of the other PCB is connected to the top surface of the PCB via a first ball grid array (BGA) (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the bottom surface of the connection component 106 including another PCB to a top surface of the PCB 108), and
wherein the first BGA spans across the bottom surface of the other PCB without another component between BGA components of the first BGA (Jones, Fig. 2 depicts wherein the first BGA of solder balls spanning across the bottom surface of the connection component 106 including another PCB has no other component between solder ball components of the first BGA of solder balls).
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 12-13, 16-17 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Thursday 7:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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