Prosecution Insights
Last updated: October 01, 2026
Application No. 18/165,790

CONNECTION COMPONENTS FOR CONNECTING A SEMICONDUCTOR PACKAGE WITH A BOTTOM STIFFENER TO A PRINTED CIRCUIT BOARD

Non-Final OA §103
Filed
Feb 07, 2023
Examiner
MILLER, ALEXANDER MICHAEL
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Juniper Networks Inc.
OA Round
3 (Non-Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
6 granted / 7 resolved
+17.7% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
39 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
65.3%
+25.3% vs TC avg
§102
23.1%
-16.9% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 7 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 18 June 2026 has been entered. Claim and Specification Status The Examiner acknowledges the amendments to claims 1, 12 and 16 in the Applicant’s response dated 18 June 2026. The claim amendments have been addressed below. The Examiner acknowledges the amendments to claims 2, 13 and 17 in the Applicant’s response dated 18 June 2026 in lieu of the 35 U.S.C. 112(a) rejection presented in the previous office action. The 35 U.S.C. 112(a) rejection has therefore been withdrawn. The Examiner acknowledges the amendments to claims 2, 13 and 17 in the Applicant’s response dated 18 June 2026 in lieu of the drawing objection presented in the previous office action. The drawing objection has therefore been withdrawn. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, 12-13, 16-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Christopher C. Jones et al. (US 2008/0142961 A1; hereinafter “Jones”) in view of Yong Joon Kim et al. (US 2021/0185815 A1; hereinafter “Kim”) and in further view of Glenn G. Daves et al. (US 2006/0060636 A1; hereinafter “Daves”). Regarding Claim 1, Jones teaches an apparatus, comprising: a printed circuit board (PCB) (108, Fig. 2, para [0022] described a PCB 108); a semiconductor package (104, Fig. 2, para [0022] describes a package substrate 104) disposed on a top surface of the PCB (Fig. 2 depicts wherein package substrate 104 is disposed on a top surface of the PCB 108) that includes a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of package substrate 104 that may include vias and traces) and a stiffener (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104), wherein a top surface of the stiffener is disposed on a bottom surface of the substrate (306 and 304, Fig. 5 depicts wherein a top surface of the stiffener layers 306 are disposed on a bottom surface of the substrate layer 304), wherein a bottom surface of the stiffener is disposed on a top surface of the PCB (104 and 306, Fig. 2 depicts wherein a bottom surface of the stiffener layers 306 comprised in package substrate 104 on either side of cavity 150 are disposed on a top surface of the PCB 108), wherein the stiffener has an opening extending through the top surface of the stiffener and the bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface), and at least one connection component that is configured to connect the PCB and the semiconductor package (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104); another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306), wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and wherein the stiffener surrounds the other component on all sides (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308). Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB. However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]). Jones and Kim fail to explicitly disclose wherein the PCB extends beyond the stiffener on all sides. However, Daves teaches a similar apparatus, wherein the PCB (180, Fig. 10 and Fig. 12A, para [0052] describes a printed circuit board 180) extends beyond the stiffener on all sides (180 and 300, Fig. 10 and Fig. 12A, para [0073] describes support brackets or frames 300 acting as stiffeners between PCB 180 and substrate 130 wherein the PCB 180 can be seen surrounding the stiffener 300 on all sides as shown by Fig. 12A which may be a top down view of Fig. 10). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones and Kim with Daves to further disclose an apparatus wherein the PCB extends beyond the stiffener on all sides in order to provide the well-known advantage of providing a surface of a PCB large enough for stiffeners to be mounted on in order to ensure the stiffeners have been mounted securely therefore increasing their effectiveness as mechanical supports (Daves, para [0073]) and to further provide the well-known advantage of providing a PCB which is large enough to accommodate multiple chips and substrates being mounted onto a surface thereof increasing a device density on a PCB and further increasing its potential functionality. Regarding Claim 2, the combination of Jones, Kim and Daves teaches the apparatus of claim 1, wherein a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the top surface of the PCB 108), and wherein a top surface of the other PCB is disposed on a bottom surface of the substrate (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304). Regarding Claim 3, the combination of Jones, Kim and Daves teaches the apparatus of claim 1, wherein: the bottom surface of the other PCB is connected to the top surface of the PCB via a first ball grid array (BGA) (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the bottom surface of the connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, to a top surface of the PCB 108), and the top surface of the other PCB is connected to the bottom surface of the substrate via a second BGA (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the top surface of the connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, to a bottom surface of the package substrate 104 comprised in the hole 308 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304). Regarding Claim 12, Jones teaches an apparatus, comprising: a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of a package substrate 104 that may include vias and traces); a stiffener with an opening disposed on a bottom surface of the substrate (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104), wherein the opening of the stiffener extends through a top surface of the stiffener and the bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface); a printed circuit board (PCB) disposed on a bottom surface of the stiffener (108, Fig. 2, para [0022] described a PCB 108 which can be seen disposed on a bottom surface of the stiffener layers 306 of the package substrate 104 in Fig. 2), at least one connection component that is configured to connect the PCB to at least one of the stiffener or the substrate (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104 comprising substrate layers 302 and 304 and stiffener layers 306); and another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306), wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and wherein the stiffener surrounds the other component (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308). Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB. However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]). Jones and Kim fail to explicitly disclose wherein the PCB extends beyond the stiffener on all sides. However, Daves teaches a similar apparatus, wherein the PCB (180, Fig. 10 and Fig. 12A, para [0052] describes a printed circuit board 180) extends beyond the stiffener on all sides (180 and 300, Fig. 10 and Fig. 12A, para [0073] describes support brackets or frames 300 acting as stiffeners between PCB 180 and substrate 130 wherein the PCB 180 can be seen surrounding the stiffener 300 on all sides as shown by Fig. 12A which may be a top down view of Fig. 10). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones and Kim with Daves to further disclose an apparatus wherein the PCB extends beyond the stiffener on all sides in order to provide the well-known advantage of providing a surface of a PCB large enough for stiffeners to be mounted on in order to ensure the stiffeners have been mounted securely therefore increasing their effectiveness as mechanical supports (Daves, para [0073]) and to further provide the well-known advantage of providing a PCB which is large enough to accommodate multiple chips and substrates being mounted onto a surface thereof increasing a device density on a PCB and further increasing its potential functionality. Regarding Claim 13, the combination of Jones, Kim and Daves teaches the apparatus of claim 12, wherein a top surface of the other PCB is disposed on a portion of the bottom surface of the substrate that is associated with the opening of the stiffener (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 associated with the opening 150 of the stiffener layers 306 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304), and wherein a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the top surface of the PCB 108). Regarding Claim 16, Jones teaches an apparatus, comprising: a printed circuit board (PCB) (108, Fig. 2, para [0022] described a PCB 108); a semiconductor package (104, Fig. 2, para [0022] describes a package substrate 104) that includes a substrate (302 and 304, Fig. 5, para [0026] describes layers 302 and 304 of package substrate 104 that may include vias and traces) and a stiffener (306, Fig. 5, para [0028] describes wherein multiple layers 306 may be formed on substrate layers 302 and 304 with a hole in the center wherein layers 306 support package substrate 104), wherein the stiffener is disposed on a top surface of the PCB (104 and 306, Fig. 2 depicts wherein a bottom surface of the stiffener layers 306 comprised in package substrate 104 on either side of cavity 150 are disposed on a top surface of the PCB 108), wherein the stiffener has an opening extending through the top surface of the stiffener and a bottom surface of the stiffener (150 and 308, Fig. 2 and Fig. 5, para [0027] describes wherein stiffener layers 306 have a hole 308 which may form recess 150 extending from a top surface of the stiffener layers 306 to a bottom surface), and at least one connection component that is configured to connect the PCB to at least one of the substrate or the stiffener of the semiconductor package (Fig. 2, para [0022] describes wherein at least one connection component, such as solder balls, is used to connect the PCB 108 to the semiconductor package 104 comprising the substrate layers 302 and 304 and stiffener layers 306); and another component that is disposed within the opening of the stiffener (106, Fig. 2, para [0018] describes an electrical device 106 disposed in the opening 150 of the stiffener layers 306), wherein the other component spans within inner walls of the opening of the stiffener (106, Fig. 2, para [0021] describes wherein the device 106 is located in the opening 150 spanning within the inner walls of the opening as shown in Fig. 2), and wherein the stiffener surrounds the other component on all sides (306 and 106, Fig. 4 depicts wherein stiffener layers 306 surround the hole 308 on all sides wherein component 106 is disposed in said hole 308). Jones fails to explicitly describe wherein the component that is disposed within the opening of the stiffener is a PCB. However, Kim teaches a similar apparatus, comprising another PCB that is disposed within the opening of the stiffener (200, 410 and 410H, Fig. 3, para [0040] describes wherein a second printed circuit board 200 is disposed in an opening 410H between first structures 410 which may be stiffener components). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones with Kim to further disclose an apparatus comprising a second PCB disposed within the opening of the stiffener in order to provide the advantage of providing a structure with high degrees of layering and a large size through the use of a first and second printed circuit board, reducing the difficulty of the technology, increasing yield and reducing manufacturing costs (Kim, para [0041]). Jones and Kim fail to explicitly disclose wherein the PCB extends beyond the stiffener on all sides. However, Daves teaches a similar apparatus, wherein the PCB (180, Fig. 10 and Fig. 12A, para [0052] describes a printed circuit board 180) extends beyond the stiffener on all sides (180 and 300, Fig. 10 and Fig. 12A, para [0073] describes support brackets or frames 300 acting as stiffeners between PCB 180 and substrate 130 wherein the PCB 180 can be seen surrounding the stiffener 300 on all sides as shown by Fig. 12A which may be a top down view of Fig. 10). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Jones and Kim with Daves to further disclose an apparatus wherein the PCB extends beyond the stiffener on all sides in order to provide the well-known advantage of providing a surface of a PCB large enough for stiffeners to be mounted on in order to ensure the stiffeners have been mounted securely therefore increasing their effectiveness as mechanical supports (Daves, para [0073]) and to further provide the well-known advantage of providing a PCB which is large enough to accommodate multiple chips and substrates being mounted onto a surface thereof increasing a device density on a PCB and further increasing its potential functionality. Regarding Claim 17, the combination of Jones, Kim and Daves teaches the apparatus of claim 16, wherein a top surface of the other PCB is disposed on a portion of a bottom surface of the substrate that is associated with the opening of the stiffener (Jones, 106, Fig. 2 depicts wherein a top surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the bottom surface of the package substrate 104 comprised in the hole 308 associated with the opening 150 of the stiffener layers 306 as shown in Fig. 5 wherein the bottom surface in the hole 308 is a bottom surface of the substrate layer 304), and wherein a bottom surface of the other PCB is disposed on the top surface of the PCB (Jones, 106, Fig. 2 depicts wherein a bottom surface of the at least one connection component 106, which may be another PCB after combining the connection component 106 of Jones with the PCB 180 of Kim, is disposed on the top surface of the PCB 108). Regarding Claim 21, the combination of Jones, Kim and Daves teaches the apparatus of claim 1, wherein the bottom surface of the other PCB is connected to the top surface of the PCB via a first ball grid array (BGA) (Jones, Fig. 2, para [0022] describes wherein solder balls which can be seen disposed in the shape of an array in Fig. 2, may be used to connect the bottom surface of the connection component 106 including another PCB to a top surface of the PCB 108), and wherein the first BGA spans across the bottom surface of the other PCB without another component between BGA components of the first BGA (Jones, Fig. 2 depicts wherein the first BGA of solder balls spanning across the bottom surface of the connection component 106 including another PCB has no other component between solder ball components of the first BGA of solder balls). Response to Arguments Applicant’s arguments with respect to claims 1-3, 12-13, 16-17 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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Prosecution Timeline

Show 6 earlier events
Apr 21, 2026
Final Rejection mailed — §103
May 21, 2026
Interview Requested
Jun 10, 2026
Applicant Interview (Telephonic)
Jun 10, 2026
Examiner Interview Summary
Jun 18, 2026
Response after Non-Final Action
Jul 21, 2026
Request for Continued Examination
Jul 23, 2026
Response after Non-Final Action
Sep 09, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+33.3%)
3y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 7 resolved cases by this examiner. Grant probability derived from career allowance rate.

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