Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1, 8, and 9 have been amended. Claims 5, 7, and 11 have been canceled.
Response to Amendment
Amendments to claim 1 is acknowledged and is determined to overcome the 35 U.S.C §112(b) rejection of claim 1.
Response to Arguments
Applicant’s arguments with respect to claims 1 and its dependent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In this case, the applicant argues that Wang fails to teach wherein the semiconductor structure has N wiring layers where N is an integer greater than 2 and that Kim’s peripheral wiring layer also does not exceed two layers. However, the examiner submits that Wang does disclose a semiconductor device that includes an N amount of wiring layers where N can be greater than 2 (Wang Fig. 1 and Fig. 2B), and furthermore, the examiner introduces the disclosure of Kuono as evidence that additional metal wiring layer are known implementations in the art, which can also include peripheral wiring layers with annular patterns (Kuono Fig. 16-18).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4,6, 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 10453803 B2), referred to as Wang in further view of Kuono et al. (US 20020190382 A1), hereinafter referred to as Kuono.
Regarding the independent Claim 1:
[AltContent: textbox (Exhibit 1: Wang Fig. 7 showing semiconductor structure 800 with substrate 830, and wiring substrate 821)]
PNG
media_image1.png
604
453
media_image1.png
Greyscale
A semiconductor structure, configured to form a pad, the semiconductor structure comprising: a substrate (Wang Fig. 7, Substrate 830),
a top-layer conductive line, N layers of secondary-top-layer conductive lines and a plurality of dielectric layers (Wang Fig. 1, Col. 3 Line 22, “…the semiconductor wiring substrate 10 includes an upper contact layer 20…a plurality of wiring layers 40 and a plurality of dielectric layers 50.” Where wiring substrate 10 is labeled as wiring substrate 821 in Fig. 7.)
wherein the top-layer conductive line and the N layers of the secondary-top-layer conductive lines are arranged above the substrate (Wang Fig. 7, Interposer 820 which includes wiring substrate 821 (10 of Fig. 1), shown to be disposed on top of substrate 830.)
the N layers of the secondary-top-layer conductive lines are arranged on a side of the top-layer conductive line close to the substrate (Wang Fig. 1, N layers of secondary-top-layer conductive lines 40, disposed on the side of top-layer-conductive line close to the substrate),
and each of the plurality of dielectric layers is located between two respective adjacent layers of the secondary-top-layer conductive lines in a vertical direction (Wang Fig. 1, dielectric layers 50 in between layers of secondary-top-layer conductive lines),
[AltContent: textbox (Exhibit 2: Wang Fig. 1 showing wiring substrate 10 with plurality of dielectric layers 50 and wiring layers 40 sandwiched between upper and lower contacts (20, 30).)]
PNG
media_image2.png
648
550
media_image2.png
Greyscale
and wherein for the N layers of the secondary-top-layer conductive lines, an area in which projections of any two layers of the secondary-top-layer conductive lines on a top surface of the substrate overlap with each other is 0 (Wang Fig. 2A where the projections of any two layers secondary-top-layer conductive lines do not overlap (203, 202) and (103, 102)).
Wang fails to explicitly teach N being an integer greater than 2. However, the examiner notes that fig. 1 of Wang depicts a plurality of wiring layers 40 where the breaks indicate the ability to add additional layers.
Furthermore, in a related field of endeavor, Kuono teaches a semiconductor structure with N layers of secondary-top-layer conductive lines and a plurality of dielectric layers and N being an integer greater than 2 (Kuono Fig. 16 depicting N layers conductive lines 16 and plurality of dielectric layers, where N is greater than 2.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kuono to the disclosure of Wang in order to implement more layer of conductive lines. This is obvious to try as the implementation of additional layers of conductive lines is a known way of improving device characteristics and improving the quality of the planarization process (Kuono [0030] “The semiconductor device of the seventh aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of metal dummy patterns while maintaining the essential effect (planarization) of the metal CMP.”)
Regarding Claim 2: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 1.
Wang further teaches the semiconductor structure wherein the semiconductor structure further comprises a first region configured to form a redistribution layer (Wang Fig. 7 823, Col. 8 Line 15, “The upper terminal layer 822 includes a plurality of first contacts 823 including soldering pad and balls.” Which is consistent with the applicant’s definition of a redistribution layer and as is known in the art (¶[0041])),
wherein the first region is arranged on a side of the top-layer conductive line away from the substrate (Wang Fig. 7, 823 on a side of top-layer conductive line 822 away from the substrate,
and wherein a projection of the N layers of the secondary-top-layer conductive lines on the top surface of the substrate at least partially overlaps with a projection of the first region on the top surface of the substrate (Wang Fig. 7, wherein the region of 823 would clearly overlap with the projection of the wiring layers within 821).
Regarding Claim 3: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 2.
Wang teaches the semiconductor structure, wherein the N layers of the secondary-top-layer conductive lines comprise a first secondary-top-layer conductive line (Wang Fig. 1, wherein the wiring substrate include a first secondary-top-layer conductive line among the wiring layers 40),
the first secondary-top-layer conductive line being closest to the top-layer conductive line among the N layers of the secondary-top-layer conductive lines (Wang Fig. 1, wherein the first secondary-top-layer conductive line would be the one closest to the top-layer conductive line among the wiring layers 40),
and wherein a projection of the first secondary-top-layer conductive line on the top surface of the substrate covers the projection of the first region on the top surface of the substrate (Wang Fig. 7, wherein the region of 823 would clearly overlap with the projection of the wiring layers within 821).
Regarding Claim 4: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 1.
Wang further teaches the semiconductor structure, wherein the N layers of secondary-top-layer conductive lines comprise central area wires (Wang Fig. 1, wherein one of the many wiring layers could be central wires relative to other layers),
and wherein a projection of the central area wires on the top surface of the substrate comprises a plurality of patterns extending in a first direction (Wang Fig. 5 wherein signal lines and grounding wires (202, 103, 102,203) are shown to extend in a first direction (x). Since this is representative of the configuration of each wiring layer, the examiner interprets that the projection of this wiring pattern would also apply to the central area wires.),
the plurality of patterns are spaced in a second direction, and the second direction is perpendicular to the first direction (Wang Fig. 5, wherein the wires are spaced in a second direction (y) perpendicular to the first direction (x), the examiner notes that the choice of x and y is based on the disclosure of Wang).
Re: Claim 6: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 4.
Wang fails to explicitly teach wherein the N layers of the secondary-top-layer conductive lines further comprise peripheral area wires, and wherein a projection of the peripheral area wires on the top surface of the substrate comprises a first annular pattern, and the first annular pattern surrounds the projection of the central area wires on the top surface of the substrate.
However, in a related field of endeavor, Kuono teaches a semiconductor structure teach wherein the N layers of the secondary-top-layer conductive lines further comprise peripheral area wires (Kuono Fig. 18, peripheral area wires 23)
and wherein a projection of the peripheral area wires on the top surface of the substrate comprises a first annular pattern (Kuono Fig. 18, wherein the peripheral area wires 23 comprise a first annular pattern).
and the first annular pattern surrounds the projection of the central area wires on the top surface of the substrate (Kuono Fig. 18 depicting a top view of the semiconductor structure, thereby representing a projection of the central area wires being surrounded by the projection of the first annular pattern of 23).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kuono to the disclosure of Wang to understand that peripheral wiring with annular patterns are known implementations in the art that serves a variety of purposes such as routing signals to auxiliary devices, or as integrated devices such as inductors or guard rings (Kuono [0226] “As shown in FIG. 18, a metal guard ring 27 may be so provided as to surround the inductor 23 in an outer peripheral region 25 of the formation region of the inductor 2”)
Regarding Claim 12: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 1.
Wang further teaches wherein a material of the plurality of dielectric layers is an insulating material (Wang Col. 6 Line 10 “The first dielectric layer and the second dielectric layer include materials such as oxides, nitrides, or oxynitrides, however, the disclosure is not limited thereto.” Where the examiner notes that these dielectric materials are well-known insulators in the art).,
and a material of the top-layer conductive line and a material of the N layers of the secondary-top-layer conductive lines are metal (Wang Col. 6 Line 13 “The first grounding line, the second grounding line, the third grounding line, the first signal line, the second signal line and the third signal line respectively include a conductive material (for example, metal or indium tin, however, the disclosure is not limited thereto)”).
Regarding Claim 13: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 4.
Wang further teaches the semiconductor structure wherein N is equal to 3 (Wang Fig. 2B depicting three layers of metal wiring layer 200, hence N=3),
wherein the central area wires comprise first central area wires, second central area wires, and third central area wires (Wang Fig. 2B has three wiring layers that can be disposed underneath a device 810 of Fig. 7 (hence being a central wiring layer)),
and the first central area wires, the second central area wires and the third central area wires are continuously arranged in the vertical direction (Wang Fig. 2B has three wiring layers which are continuously arranged in the vertical direction),
wherein a projection of the first central area wires on the top surface of the substrate comprises a first pattern (Wang Fig. 5 wherein a sample projection of first central wires (103, 102) comprises a first pattern),
a projection of the second central area wires on the top surface of the substrate comprises a plurality of second patterns extending in the first direction (Wang Fig. 5 wherein a sample projection of second central wires (203, 202) comprises a second pattern extending in a first direction x),
and a projection of the third central area wires on the top surface of the substrate comprises a plurality of third patterns extending in the first direction (Wang Fig. 5 wherein a third central wiring layer would be expected to also have a projection comprising a third pattern extending in a first direction x similar to the first and second wiring layers.).
Regarding Claim 14: The combined disclosure of Wang and Kuono teaches the semiconductor device of claim 13
Wang further teaches wherein the first pattern comprises first strip patterns (Wang Fig. 5 wherein a projection of first wires (103, 102) creates a first pattern comprises a first strip pattern),
the plurality of second patterns are second strip patterns (Wang Fig. 5 wherein a projection of second wires (203, 202) creates a plurality second pattern which is a second strip pattern),
and the plurality of third patterns are third strip patterns (Wang Fig. 2B Fig. 5 wherein an additional metal layer would also have projection of additional wires (such as 203, 202) creating a plurality additional pattern which is a third strip pattern),
wherein the first strip patterns extend in the first direction, and the first strip patterns, the second strip patterns and the third strip patterns are alternately arranged in a predetermined order in the second direction (Wang Fig. 5 wherein the strip patterns are shown to be arranged in a alternating pattern (203-102-203, 103-202-103) wherein another layer could easily be arranged in such a manner using known methods in the art).
Wang fails to teach wherein the first pattern comprises a second annular pattern, the second annular pattern surrounds the first strip patterns, the second strip patterns, and the third strip patterns
However, in a related field of endeavor, Kuono teaches the use of a guard ring which may enclose wiring patterns within (Kuono Fig. 19 guard ring with annular pattern 27). The examiner interprets the disclosure of Kuono as an indication that strip patterns and annular patterns are wiring patterns that are implemented in semiconductor devices using known methods in the art.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Kuono to the disclosure of Wang to know that Wang could have implemented an annular wiring pattern surrounding a central wiring pattern. This is obvious to try as such structures can be used as guard rings or as an way to preserve the structure of the device during a CMP process (Kuono [0117] “By providing the metal guard ring 27,
it is possible to prevent deterioration in characteristics of elements provided outside the inductor
23 and since the metal guard ring 27 serves as a metal dummy pattern, an advantage of preventing the planeness obtained by the CMP from being impaired”)
Regarding Claim 15: The combined disclosure of Wang and Kuono teaches the semiconductor device of Claim 13.
Wang further teaches the plurality of second patterns are second strip patterns (Wang Fig. 5 wherein a projection of second wires (203, 202) creates a plurality second pattern which is a second strip pattern),
and the plurality of third patterns are third strip patterns (Wang Fig. 2B Fig. 5 wherein an additional metal layer would also have projection of additional wires ( such as 203, 202) creating a plurality additional pattern which is a third strip pattern),
and the second strip patterns and the third strip patterns are alternately arranged in the second direction (Wang Fig. 5 wherein the strip patterns are shown to be arranged in a alternating pattern (203-102-203, 103-202-103) wherein another layer could easily be arranged in such a manner using known methods in the art).
Wang fails to teach the device wherein the first pattern is a second annular pattern, wherein the second annular pattern surrounds the second strip patterns and the third strip patterns However, in a related field of endeavor, Kuono teaches the use of a guard ring which may enclose wiring patterns within (Kuono Fig. 19 guard ring with annular pattern 27). The examiner interprets the disclosure of Kuono as an indication that strip patterns and annular patterns are wiring patterns that are implemented in semiconductor devices using known methods in the art.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Kuono to the disclosure of Wang to know that Wang could have implemented an annular wiring pattern surrounding a central wiring pattern. This is obvious to try as such structures can be used as guard rings or as an way to preserve the structure of the device during a CMP process (Kuono [0117] “By providing the metal guard ring 27,
it is possible to prevent deterioration in characteristics of elements provided outside the inductor
23 and since the metal guard ring 27 serves as a metal dummy pattern, an advantage of preventing the planeness obtained by the CMP from being impaired”).
With regards to Claim 16: The combined disclosure of Wang and Kuono teach the semiconductor device of Claim 14.
Wang further teaches the semiconductor structure, wherein the predetermined order comprises at least one of: a sequence or reverse sequence of the first strip patterns, the second strip patterns and the third strip patterns; a sequence or reverse sequence of the second strip patterns, the first strip patterns and the third strip patterns; or a sequence or reverse sequence of the first strip patterns, the third strip patterns and the second strip patterns (Wang Fig. 2A or 2B, where the projected patterns on a top substrate is expected to be a sequence or reverse sequence of first, second, third, or any combination thereof, modifiable with methods known in the art).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Kuono in further view of Kim et al. (US 20200357811 A1), hereinafter referred to as Kim.
Regarding Claim 8: The combined disclosure of Wang and Kuono teaches the semiconductor structure of claim 6.
Wang fails to teach the semiconductor device, wherein N is greater than 2. However, the examiner notes that fig. 1 of Wang depicts a plurality of wiring layers 40 where the breaks indicate the ability to add additional layers.
Furthermore, in a related field of endeavor, Kuono teaches a semiconductor structure with N layers of secondary-top-layer conductive lines and a plurality of dielectric layers and N being an integer greater than 2 (Kuono Fig. 16 depicting N layers conductive lines 16 and plurality of dielectric layers, where N is greater than 2.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kuono to the disclosure of Wang in order to implement more layer of conductive lines. This is obvious to try as the implementation of additional layers of conductive lines is a known way of improving device characteristics and improving the quality of the planarization process (Kuono [0030] “The semiconductor device of the seventh aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of metal dummy patterns while maintaining the essential effect (planarization) of the metal CMP.”
The disclosure of Wang and Kuono, fails to explicitly teach the first peripheral area wires, the at least one layer of the third peripheral area wires and the second peripheral area wires are continuously arranged in the vertical direction.
and wherein a first end of the first peripheral area wires is connected to the top-layer conductive line, a second end of the first peripheral area wires is connected to a first end of the at least one layer of the third peripheral area wires, a first end of the second peripheral area wires is connected to a second end of the at least one layer of the third peripheral area wires,
and a second end of the second peripheral area wires is connected to a semiconductor test device formed in the substrate.
However, the examiner notes that the inventions of Wang and Kuono depict wire layers that are continuously arranged in a vertical direction and are connected to each other via intermediary layers.
Furthermore, in a related field of endeavor, Kim teaches a device wherein this layers can be electrically connected, wherein the first peripheral area wires, the at least one layer of the third peripheral area wires and the second peripheral area wires are continuously arranged in the vertical direction (Kim Fig. 21A, depicting vias 782, 786, 488, connecting peripheral area wires in various layers that includes metal structures 186, 498, 784)
and wherein a first end of the first peripheral area wires is connected to the top-layer conductive line (Kim Fig. 21A, wires 788 connected to 186 or 498 with via 488),
a second end of the first peripheral area wires is connected to a first end of the at least one layer of the third peripheral area wires (Kim Fig. 21A wires 788 connected to third layer 784 with via 786),
a first end of the second peripheral area wires is connected to a second end of the at least one layer of the third peripheral area wires (Kim Fig. 21A third layer 784 connected to second peripheral wire 784 with via 786),
and a second end of the second peripheral area wires is connected to a semiconductor test device formed in the substrate (Kim Fig. 18A, second end of the second peripheral wires and semiconductor test device comprising 742, connected by a via structure 782.)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, that the disclosure of Wang or Kuono would have included a peripheral area wiring with 2 levels of wiring layer that may include an additional third layer that is configured similar to what is taught by Kim. This is obvious to try as IC packages are known in the art to contain multiple semiconductor devices that must communicate with each other via peripheral wiring as taught by Kim.
Regarding Claim 9: The combined disclosure of Wang, Kuono, and Kim teaches the semiconductor structure of claim 8.
Wang further teaches the device wherein the semiconductor structure further comprises conductive vias, the conductive vias extend in the vertical direction, the conductive vias penetrate the plurality of dielectric layers, so as to conductively connect adjacent peripheral area wires, and the conductive vias conductively connect the first peripheral area wires and the top-layer conductive line and conductively connect the second peripheral area wires and the semiconductor test device (Wang Col. 1 Line 32, Col. 7 Line 52 “integrated circuit is characterized by respectively stacking chips having different functions or properties onto a silicon interposer. The stacked chips are electrically connected to each other through inner wiring and 35 through-silicon via (TSV) of the silicon interposer”. “…and each of the conductive through-hole portions 720 is connected to each of the first grounding lines 103 and each of the second grounding lines 203 which are adjacent to each other.”)
Where the examiner notes that conductive vias are known structures in the art implemented to establish electrical connection in a vertical direction between adjacent layers that may contain devices, chips, or interposers that contain wiring layers, rails, or distribution layers.
For example, Kim, in a related field of endeavor teaches a device wherein the semiconductor structure further comprises conductive vias (Kim Fig. 21A, conductive vias 488. 786, 782),
the conductive vias extend in the vertical direction, the conductive vias penetrate the plurality of dielectric layers (Kim fig. 21A. vias extending in a vertical direction, penetrating dielectric layers 764, 766, 165, 265),
so as to conductively connect adjacent peripheral area wires (Kim Fig. 21A, vias 286 conductively connect adjacent peripheral wires 784,),
and the conductive vias conductively connect the first peripheral area wires and the top-layer conductive line (Kim Fig. 21A, vias 488 conductively connect 186, 498 to peripheral wires 788),
and conductively connect the second peripheral area wires and the semiconductor test device (Kim Fig. 21A, vias 782 conductively connect semiconductor test device comprising active layer 720).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Kim to the disclosure of Wang to understand that the wiring layers of Wang could be configured in an IC device of Kim where multiple wiring layers and devices are connected to each other with conductive vias as is known in the art.
Regarding Claim 10: The combined disclosure of Wang, Kuono, and Kim teaches the semiconductor structure of claim 9.
Wang further teaches wherein the conductive vias further conductively connect at least one the following: adjacent central area wires; or the central area wires and the top-layer conductive line (Wang Col. 1 Line 32 “integrated circuit is characterized by respectively stacking chips having different functions or properties onto a silicon interposer. The stacked chips are electrically connected to each other through inner wiring and 35 through-silicon via (TSV) of the silicon interposer”.)
Similar to the rejection of claim 9, the examiner notes that conductive vias are known structures in the art implemented to establish electrical connection in a vertical direction between adjacent layers that may contain devices, chips, or interposers that contain wiring layers, rails, or distribution layers and these layer may be located in a central region directly beneath the active device (Wang Fig. 7, with device 810 shown to have wiring layers underneath.).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ARDEO whose telephone number is (703)756-1235. The examiner can normally be reached Mon-Fri EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899