Prosecution Insights
Last updated: July 17, 2026
Application No. 18/166,126

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Final Rejection §102§112
Filed
Feb 08, 2023
Priority
Sep 14, 2022 — JP 2022-146368
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
438 granted / 572 resolved
+8.6% vs TC avg
Moderate +5% lift
Without
With
+5.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
49 currently pending
Career history
610
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
9.9%
-30.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Re claim 1, the phrase “a side surface of the third semiconductor layer facing a side surface of the first semiconductor layer via the second semiconductor layer, a distance between the side surface of the third semiconductor layer and the side surface of the first semiconductor layer in a normal direction of the side surface of the first semiconductor layer decreasing, and not increasing, as approaching the first insulating film upward” was not described in the original specification. Note: see below figure shown in red (at least the distance of this region is increasing, NOT decreasing). PNG media_image1.png 606 546 media_image1.png Greyscale The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Re claim 1, the phrase “a side surface of the third semiconductor layer facing a side surface of the first semiconductor layer via the second semiconductor layer, a distance between the side surface of the third semiconductor layer and the side surface of the first semiconductor layer in a normal direction of the side surface of the first semiconductor layer decreasing, and not increasing, as approaching the first insulating film upward” is unclear and indefinite since at least the phrase “the first insulating film” lacks antecedent basis. Re claim 1, line 20, the phrase “the third electrode facing the portion via a first insulating film” is unclear and indefinite (e.g., is this the same as the one recited line 15 or different?). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IIJIMA, US Pub. No. 2013/0248871 A1. Due to the 112 issues, the instant claims are interpreted as following: Re claim 1. IIJIMA discloses a semiconductor device, comprising: a first electrode D2 (e.g., fig. 1A); a first semiconductor layer 40/12/10 (fig. 1A) connected to the first electrode, the first semiconductor layer 10 (e.g., fig. 1B) being of a first conductivity type and including silicon and carbon (e.g., SiC); a second semiconductor layer 20 (fig. 1A, 1B) located on a portion of the first semiconductor layer, the second semiconductor layer 20 being of a second conductivity type and including silicon and carbon (e.g, SiC) ; a third semiconductor layer 30 (e.g., figs. 1A & 1B) located on a portion of the second semiconductor layer 20, a side surface of the third semiconductor layer 30 facing a side surface of the first semiconductor layer 10 via the second semiconductor layer 20 (e.g., fig. 1A&1B), a distance between the side surface of the third semiconductor layer 30 and the side surface of the first semiconductor layer 10 (e.g., fig. 1B) in a normal direction of the side surface of the first semiconductor layer decreasing (e.g. from left to right, see below figure more details), and not increasing (e.g., figs. 1A & 1B), the third semiconductor layer being of a first conductivity type and including silicon and carbon (e.g., SiC); a second electrode D1 (e.g., fig. 1A) connected to the third semiconductor layer; and a third electrode G (e.g., figs. 1A&1B) located in a region directly above at least a portion of the second semiconductor layer between the first semiconductor layer and the third semiconductor layer, the third electrode G facing the portion via a first insulating film 60 (e.g., figs. 1A & 1B), see figs. 1A-15 and pages 1-7 for more details. PNG media_image2.png 348 390 media_image2.png Greyscale Re claim 2. The device according to claim 1, wherein a cross-sectional shape of the side surface of the third semiconductor layer 30 (fig. 1B) is a shape along a virtual circular arc having a center positioned above the third semiconductor layer (fig. 1B). Re claim 3. The device according to claim 1, wherein a distance between an upper edge and a lower edge of the side surface when viewed from above (e.g., fig. 1B) is greater than a thickness of the third semiconductor layer when viewed laterally (e.g., fig. 1B). Re claim 4. The device according to claim 1, wherein the third electrode G (fig. 1A) is located, with the first insulating film 60 interposed, on a portion of the first semiconductor layer where the second semiconductor layer is not located (fig. 1A & 1B) and on a portion of the third semiconductor layer at the second semiconductor layer side (fig. 1A & 1B). Re claim 5. The device according to claim 1, wherein the second electrode D1 contacts the third semiconductor layer 30 (fig. 1A), and the second electrode D1 covers the third electrode G via a second insulating film (fig. 1A). Re claim 6. The device according to claim 1, wherein the first semiconductor layer 40 is located on the first electrode D2 and contacts the first electrode (fig. 1A). Response to Arguments Applicant's arguments filed 1/28/2026 have been fully considered but they are not persuasive for reasons herein above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Feb 08, 2023
Application Filed
Oct 28, 2025
Non-Final Rejection mailed — §102, §112
Jan 16, 2026
Interview Requested
Jan 26, 2026
Applicant Interview (Telephonic)
Jan 26, 2026
Examiner Interview Summary
Jan 28, 2026
Response Filed
Jun 23, 2026
Final Rejection mailed — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
82%
With Interview (+5.2%)
2y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allowance rate.

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