DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over SHIMIZU (US 20210288147 A1) of record in view of Kumada et al. (US 20180233564 A1, hereinafter Kumada‘564).
Regarding independent claim 1, SHIMIZU teaches, “A semiconductor device (fig. 1-35; ¶¶ [0052] - [0293]), comprising:
a first electrode (42, fig. 13);
a second electrode (44);
a semiconductor layer (10) provided between the first electrode (42) and the second electrode (44), having a first face facing the first electrode (42) and a second face facing the second electrode (44), and containing silicon (Si);
a first semiconductor region of n-type (56) provided in the semiconductor layer (10);
a second semiconductor region of p-type (58) provided in the semiconductor layer (10) and disposed between the first semiconductor region of n-type (56) and the first face;
a third semiconductor region of n-type (60) provided in the semiconductor layer (10) and disposed between the second semiconductor region of p-type (58) and the first face;
a gate electrode (50) provided on the first face side of the semiconductor layer (56) and facing the second semiconductor region of p-type (58);
a gate insulating layer (46) provided between the second semiconductor region of p-type (58) and the gate electrode (42); and
a metal silicide layer (43) provided between the first electrode (42) and the second semiconductor region of p-type (58) and between the first electrode (42) and the third semiconductor region of n-type (60), including a top surface in contact with the first electrode (42), a first bottom surface in contact with the third semiconductor region of n-type (60), and a first side surface in contact with the third semiconductor region of n-type (60), and containing at least one metal element selected from a group consisting of gold (Au), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Qs), iridium (Ir), and platinum (Pt) (¶ 0204),
wherein, in a first direction from the first electrode (42) toward the second electrode (44), an n-type impurity concentration in the third semiconductor region of n-type (60) monotonically decreases from the first bottom surface toward the second electrode (fig. 12, P curve),
((the first semiconductor region of n-type contains the at least one metal element))”.
But SHIMIZU is silent upon the provision of wherein,
the first semiconductor region of n-type contains the at least one metal element”.
However, Kumada‘564 teaches a similar planar gate type vertical MOSFET (fig. 1; ¶ [0047] - ¶ [0048]), wherein the first semiconductor region of n-type (2) contains the at least one metal element (10).
SHIMIZU and Kumada‘564 are analogous art because they both are directed to vertical planar-gate MOSFET and one of ordinary skill in the art would have had a reasonable expectation of success to modify SHIMIZU with the features of Kumada‘564 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of SHIMIZU and Kumada‘564 to include lifetime killer region containing metal Platinum in the drift region according to the teachings of Kumada‘564 as “This lifetime killer region 10 reduces the number of minority carriers and thereby reduces the current that passes directly beneath the gate electrode 7 and flows through the p-n junction between the p-type base layer 3 and the n-type silicon carbide epitaxial layer 2” and “thereby reduce the reverse recovery loss of the built-in p-n diode”. See Kumada‘564, ¶ [0009], ¶ [0047] - ¶ [0048].
Note: Kumada‘564 in above can also be replaced by using any of the below prior arts:
NAITO; Tatsuya (US 20180350962 A1),
OHTA; Tsuyoshi et al. (US 20120241854 A1),
Dainese; Matteo et al. (US 20240136353 A1),
IMAGAWA; Tetsutaro (US 20220149150 A1) and
Nishiura; Masaharu et al. (US 4987098 A).
Regarding claim 2, SHIMIZU modified with Kumada‘564 further teaches, “The semiconductor device according to claim 1, wherein a position of the first bottom surface (43, SHIMIZU) in the first direction is closer to the second face than a position of the first face in the first direction”.
Regarding claim 3, SHIMIZU modified with Kumada‘564 further teaches, “The semiconductor device according to claim 2, wherein a distance between the first face and the first bottom surface in the first direction is equal to or more than 10 nm and equal to or less than 100 nm (fig. 1; ¶ [0074]-[0076], SHIMIZU)”.
Regarding claim 4, SHIMIZU modified with Kumada‘564 further teaches, “The semiconductor device according to claim 2,
wherein the metal silicide layer (43, fig. 13, SHIMIZU) further includes a second bottom surface in contact with the second semiconductor region of p-type (58, 62), and
a position of the second bottom surface in the first direction is closer to the second face than a position of the first bottom surface in the first direction”.
Regarding claim 8, SHIMIZU modified with Kumada‘564 further teaches, “The semiconductor device according to claim 1, wherein the n-type impurity concentration in the third semiconductor region at a position in contact with the first bottom surface is equal to or more than 2 x 1019 atoms/cm3 and equal to or less than 1 x 1021 atoms/cm3” (¶ [0146], SHIMIZU).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over SHIMIZU modified with Kumada‘564 as applied to claim 1 as above, and further in view of Xu (US 20210280680 A1).
Regarding claim 11, SHIMIZU modified with Kumada‘564 teaches all the limitations described in claim 1.
But SHIMIZU modified with Kumada‘564 is silent upon the provision of wherein the semiconductor layer is single crystal silicon (Si).
However, Xu teaches a similar semiconductor device (fig. 1a), wherein the semiconductor layer is single crystal silicon (Si).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of SHIMIZU modified with Kumada‘564 and Xu to heavily dope the source/drain extension regions according to the teachings of Xu with a motivation of exploiting the advantage of the single crystalline Silicon substrate, e.g., excellent machinability, mechanical stability, and the potential to combine sensing elements and electronics on the same substrate.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817