DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed November 24, 2025 has been entered.
The Examiner notes an apparent typo in the Remarks indicating an Amendment to Fig. 4 (only). An updated Drawing was received for Fig. 1.
Claims 1-30 remain pending in the application.
Response to Arguments
Applicant’s arguments, see pages 12-15 of Remarks, filed November 24, 2025 with respect to the rejections of claims 1 -30 under 35 U.S.C. 103 have been fully considered in view of the Amendment and some of the grounds are persuasive.
Specifically, the Applicant comments that Kato fails to disclose bonding between two dies, and Haba fails to disclose two chips are directly bonded together through the protection layers thereof. However, the rejection is based on obviousness that the disclosed elements of Kato and Haba may be combined to arrive at the structure of claim 1. Applicant has not made a specific argument regarding the combination of these two references to arrive at an optically assembly, or method of manufacturing the optical assembly, which combines the above-mentioned elements from each of the two references.
Regarding the positional relationship between the processor circuit and the reader circuit, the Examiner is persuaded that the cited prior art does not disclose it, and the rejections are withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of additional prior art, in combination with that previously cited. Please see the updated claim rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-14, 18, and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Kato; Atsushi (US 2023/0007202; hereinafter Kato) in view of Haba; Belgacem (US 2022/0077087; hereinafter Haba) and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na).
Regarding claim 1, Kato discloses a heterogeneously substrate-bonded optical assembly (1A; Figs 9A-9B; ¶ [0121-157], entire document), comprising:
a processor chip (readout integrated circuit {ROIC} substrate 200A; Figs 9A-9B; ¶ [0123,0154-157]), comprising: a silicon-containing substrate (71; Fig 9B; ¶ [0148]); a processor circuit; reader circuits (for example, 20; Fig 3; ¶ [0154-155]) electrically connected to the processor circuit (ROIC reads out a charge signal {¶ [0002]} and performs signal processing {a processor circuit} on the read signal {[0002]); a first protection layer (72A/70W; Fig 9B; ¶ [0148-149]) disposed on the processor circuit and the reader circuits; and first vias (72E; Fig 9B; ¶ [0150]) penetrating through the first protection layer and being electrically connected to the reader circuits;
an optical chip (photoelectric conversion unit 100A; Figs 9A-9B; ¶ [0123-147]) containing a non-silicon substrate (III-V compound semiconductor; ¶ [0121,0134]) and comprising: a second protection layer (69B/60W; Fig 9B; ¶ [0127-128]) bonded (¶ [0144]) to the first protection layer; second vias (69E; Fig 9B; ¶ [0127-129]) penetrating through the second protection layer and being bonded (69E connected to 72E by direct joining; ¶ [0144]) to the first vias; and optical pixels (P; Fig 9B; ¶ [0121]) formed in the non-silicon substrate, and electrically connected to the reader circuits respectively through the second vias and the first vias (¶ [0150,0154]), wherein the optical pixels correspond to the reader circuits in a one-to-one manner (¶ [0154,0042]).
Kato does not disclose:
(1) a transversal dimension of the processor chip is greater than a transversal dimension of the optical chip;
(2) a molding compound layer surrounding the optical chip and being disposed on a top surface of the first protection layer, wherein the molding compound layer has a top surface flush with a backside of the optical chip;
(3) a first area of the processor circuit orthogonally projecting onto the top surface of the first protection layer is located outside a second area of the optical chip and a third area of the reader circuits both orthogonally projecting onto the top surface of the first protection layer, and the third area overlaps with the second area.
Regarding (1) and (2), in the same field of endeavor, Haba discloses a method of manufacturing a bonded structure, comprising a die (12; Figs 1A-1D; ¶ [0023]) bonded (¶ [0024]) to a wafer (11, comprising 10; Figs 1A-1D; ¶ [0023]), wherein a transversal dimension of the wafer 11 is greater than a transversal dimension of the die 12 (as shown in Fig 1A); and a molding compound layer (16; Fig 1C; ¶ [0025]) surrounding the die 12 and being disposed on a top surface of the wafer 11 (in this case, the layer 18 is between a top surface of 11{10} and 16), wherein the molding compound layer has a top surface flush with a backside of the die (16; Fig 1D; ¶ [0025]). Accordingly, it would have been obvious to a person having ordinary skill in the art to have included elements of the method of Haba with the optical assembly of Kato. One would have been motivated to do this in order to enable wafer level processing of the bonded structure (using a so-called, reconstituted wafer comprising the die 12 bonded to the wafer 11; as known in the art), to improve reliability of the bonded structures (Haba; ¶ [0013-14]), and/or possibly to facilitate a planarized top surface to enable additional optical elements such as, for example an anti-reflection film, color filter and/or lens as exemplified in a fourth embodiment of Kato (Kato; optical elements 45,46,47 respectively; Fig 10; ¶ [0163,0165]). One would have had a reasonable expectation of success because the type of die and wafer used in Haba’s method is not limited (Haba; ¶ [0029]), and may readily apply to the processor chip and optical chip of Kato.
Regarding (3), Na discloses a sensor wafer (3130; Fig 33A; ¶ [0404]) comprising a pixel array (3010; Fig 33A; ¶ [0373]) bonded (¶ [0387]) to an IC wafer (3110; Fig 33A; ¶ [0404]), wherein a reader circuit (pixel transistor array 3320; Fig 33A; ¶ [0404]) is positioned such that an orthogonal projection of a third area of the reader circuit 3320 upon a common interface surface shared by 3130 and 3110 overlaps with an orthogonal projection of a second area of the pixel array 3320, and a variety of other exemplary circuit blocks which may comprise processor functions (for example ADC’s 3030; Figs 33A-33C; ¶ [0376,0404]); DSP; Fig 32; ¶ [0399]) positioned in a variety of configurations (Figs 33A-33C) such that an orthogonal projection of a first area each of the other exemplary circuit blocks projected upon the common interface is located outside the second area and the third area.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined Na’s disclosure of positional relationships between circuit blocks of a bonded assembly of chips to the assembly of Kato in view of Haba (wherein the pixel array corresponds to the optical chip; the pixel transistors array corresponds to the reader circuit; and the various exemplary circuit blocks corresponds to the processor circuit) to arrive at the assembly of claim 1. One would have been motivated to do this, with a reasonable expectation of success, because the circuit blocks are well known in the art both in standalone chip form and integrated chip form, and are commonly combined in various alternate integrated and/or assembled configurations depending upon a variety of performance and application requirements.
Regarding claim 2, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein the first protection layer (Kato; 72A/70W; Fig 9B) is fusion-bonded (Kato; the bonding of insulating layers through direct joining shown in Fig 9B {¶ [0144]} constitutes fusion bonding) to the second protection layer (Kato; 69B/70W; Fig 9B), and the first vias (Kato; 72E; Fig 9B) are diffusion-bonded (Kato; the bonding of electrodes through direct joining shown in Fig 9B {¶ [0144,0151]} constitutes diffusion bonding) to the second vias (Kato; 69E; Fig 9B; further, Haba discloses fusion-bonded dielectrics and diffusion-bonded conductive materials {Haba; ¶ [0016-22]}), and the first vias, when being orthogonally projecting onto the top surface of the first protection layer, are located outside the first area (of the processor circuit) and within the second area (of the optical chip, analogous to the pixel array 3010 of Fig 33A of Na; in the same manner as the interconnects 3170 {Na; Fig 33A}, since the first vias and second vias are necessarily between processor chip and the reader circuit which they connect, and which have the overlapping projections as explained for claim 1).
Regarding claim 3, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein a vertical boundary of the molding compound layer is aligned with a vertical boundary of the processor chip (along singulation line 37; Fig 1C; ¶ [0025]), and the processor circuit is disposed beside the reader circuits (as explained for claim 1 in regards to the positional relationships, the various exemplary circuit blocks {processor circuit} of Na being beside the pixel transistors array 3320 {the reader circuit}, the reader circuits overlapping with the optical chip as applied to claim 1).
Regarding claim 4, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not specifically disclose wherein the molding compound layer has a molding compound structure having a dicing mark or dicing marks formed after wafer-level package dicing; however, this would have been obvious. In the method of Haba, a dicing mark may have been used as a guide for dicing the die 12 (optical chip) from a wafer form prior to bonding the singulated die to the wafer 11 (processor chip) and forming the molding compound. Another set of dicing marks may then have been formed on the molding compound layer to guide the singulation (Haba; Fig 1C; ¶ [0025]) of the bonded structure. This would be known to one of ordinary skill in the art.
Regarding claim 6, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein a transversal dimension of each of the first vias is smaller than or equal to 1 micron. (Haba; a pitch {line/width and space} of conductive pads {equivalent to vias: see Haba; 30; Fig 1A; ¶ [0019]} may be as small as 2 microns or less, and a ratio of the pitch to a dimension of the pad {width} may be 2 to 5, therefore less than 1 micron).
Regarding claim 7, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but as applied to claim 1 does not specifically disclose further comprising an optical structure disposed on the backside of the optical chip. However, in another example embodiment, Kato discloses an optical structure disposed on the backside of the optical chip (Kato; for example, optical elements 45,46,47 respectively; Fig 10; ¶ [0163,0165]). It would have been obvious to include one or more of 45-47 in the optical assembly as applied to claim 1. One would have been motivated to do this in order to improve image quality by minimizing reflection and improving light transmission to an optical sensor (anti-reflection film 45), to control the wavelength of light reaching an optical sensor (color filter 46) or any number of other optical influences well-known in the art. One would have had a reasonable expectation of success because Kato has disclosed this in the alternate example embodiment, and it is well-known in the art.
Regarding claim 8, Kato in view of Haba and Na discloses the optical assembly according to claim 7, wherein the optical structure is selected from a group consisting of a collimator, a micro lens (Haba; 47; Fig 10), a filter (Haba; 46; Fig 10) and a partial light shielding layer.
Regarding claim 9, Kato in view of Haba and Na discloses the optical assembly according to claim 7, but does not disclose wherein a portion of the optical structure is further disposed on the molding compound layer. However, it would have been obvious to a person having ordinary skill in the art to have done this. As one example, in the case of an optical structure formed by a blanket film formation method, such as some filters or anti-reflection films, one may be motivated by convenience and efficiency to form the optical structure by blanket formation over the entire exposed top surface, which includes the backside of the optical chip and the molding layer as applied to claim 1. In a final optical assembly, the optical structure may then remain over the entire top surface, or on at least a portion of the molding compound layer. One would have had a reasonable expectation of success because such film formation methods, and reconstituted wafer level processing are well-known in the art.
Regarding claim 10, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein the optical pixels sense infrared light having a wavelength longer than 1 micron (Kato; sensitivity to wavelengths from 0.8 to 1.7 microns; ¶ [0034]).
Regarding claim 11, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein the optical pixels sense infrared light having a wavelength longer than 1.3 microns (Kato; sensitivity to wavelengths from 0.8 to 1.7 microns; ¶ [0034]).
Regarding claim 12, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein incident infrared light transmits through the non-silicon substrate and reaches the optical pixels. (Kato; Fig 9B; light is incident at surface S1 and penetrates substrate 63 comprising the optical pixels P; ¶ [0134])
Regarding claim 13, Kato in view of Haba and Na discloses the optical assembly according to claim 1 being selected from a group consisting of an optical sensor device (Kato; infrared sensor; ¶ [0121]), an optical filter, a polarizer, a curved-surface optical device, a digital optical device, a diffraction optical element and a metalens.
Regarding claim 14, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein an outermost surface of the first protection layer (Kato; 72A; Fig 9B) is made of a material of silicon oxide or a silicon dioxide (Kato; ¶ [0149]).
Regarding claim 18, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein a transversal dimension of each of the first vias is equal to a transversal dimension of each of the second vias (Kato; as shown in Fig 9B, and well-known in the art.)
Regarding claim 20, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose further comprising an optical structure disposed on or above the optical pixels , wherein optical devices of the optical structure correspond to the optical pixels in a one-to-one, one-to-many or many-to-many relationship.
However, in another example embodiment, Kato discloses an optical structure disposed on the backside of the optical chip (Kato; for example, optical elements 47; Fig 10; ¶ [0165]) corresponding one-to-one to optical pixels 111B (Kato; Fig 10; ¶ [0159]). It would have been obvious to include optical elements 47 in the optical assembly as applied to claim 1. One would have been motivated to do this in order to focus incoming light with the lens 47 and increase light-gathering efficiency. One would have had a reasonable expectation of success because Kato has disclosed this in the alternate example embodiment, and it is well-known in the art.
Regarding claim 21, Kato in view of Haba and Na discloses the optical assembly according to claim 1, wherein the top surface of the molding compound layer and backsides of the optical pixels are disposed on a same plane. As applied to claim 1, the backside of the optical pixels (Kato; P; Fig 9B) are at the backside of the optical chip (Kato; 100A; Fig 9B), and as combined with Haba the molding compound layer (Haba; 16; Fig 1D) has a top surface flush with a backside of the optical chip (Haba; die 12; Fig 1D); that is, the top surface of the molding compound layer and backsides of the optical pixels are disposed on a same plane.
Claims 5, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kato; Atsushi (US 2023/0007202; hereinafter Kato) in view of Haba; Belgacem (US 2022/0077087; hereinafter Haba) and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na), and further in view of Katkar; Rajesh et al. (US 2021/0181510; hereinafter Katkar).
Regarding claim 5, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein a transversal dimension of each of the optical pixels is smaller than or equal to 10 microns.
In the same field of endeavor, Katkar discloses an optical device containing a non-Si substrate (singulated {202a-c; Fig 2; ¶ [0023]} optical wafers formed of III-V materials; ¶ [0020]) bonded to a silicon wafer (Si or CMOS processor; ¶ [0020]; 204; Fig 2; die-to wafer; ¶ [0023]) wherein a transversal dimension of each of the optical pixels is smaller than or equal to 10 microns (less than 5 microns, or less than 1 micron; ¶ [0022]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the same dimension may be attained in Kato in view of Haba as applied to claim 1. One would have been motivated to use these dimensions in order to attain higher, more detailed, image resolution and/or to enable a smaller device, which are desirable attributes for a number of applications known in the art. One would have had a reasonable expectation of success because of the similar bonding methods and endeavors of Katkar (direct, hybrid bonding; Figs 2-3; ¶ [0022]), Kato and Haba.
Regarding claim 15, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein a transversal dimension of each of the optical pixels is smaller than or equal to 8 microns.
In the same field of endeavor, Katkar discloses an optical device containing a non-Si substrate (singulated {202a-c; Fig 2; ¶ [0023]} optical wafers formed of III-V materials; ¶ [0020]) bonded to a silicon wafer (Si or CMOS processor; ¶ [0020]; 204; Fig 2; die-to wafer; ¶ [0023]) wherein a transversal dimension of each of the optical pixels is smaller than or equal to 8 microns (less than 5 microns, or less than 1 micron; ¶ [0022]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the same dimension may be attained in Kato in view of Haba as applied to claim 1. One would have been motivated to use these dimensions in order to attain higher, more detailed, image resolution and/or to enable a smaller device, which are desirable attributes for a number of applications known in the art. One would have had a reasonable expectation of success because of the similar bonding methods and endeavors of Katkar (direct, hybrid bonding; Figs 2-3; ¶ [0022]), Kato and Haba.
Regarding claim 16, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein a transversal dimension of each of the optical pixels is smaller than or equal to 6 microns.
In the same field of endeavor, Katkar discloses an optical device containing a non-Si substrate (singulated {202a-c; Fig 2; ¶ [0023]} optical wafers formed of III-V materials; ¶ [0020]) bonded to a silicon wafer (Si or CMOS processor; ¶ [0020]; 204; Fig 2; die-to wafer; ¶ [0023]) wherein a transversal dimension of each of the optical pixels is smaller than or equal to 6 microns (less than 5 microns, or less than 1 micron; ¶ [0022]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the same dimension may be attained in Kato in view of Haba as applied to claim 1. One would have been motivated to use these dimensions in order to attain higher, more detailed, image resolution and/or to enable a smaller device, which are desirable attributes for a number of applications known in the art. One would have had a reasonable expectation of success because of the similar bonding methods and endeavors of Katkar (direct, hybrid bonding; Figs 2-3; ¶ [0022]), Kato and Haba.
Regarding claim 17, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein a transversal dimension of each of the optical pixels is smaller than or equal to 5 microns.
In the same field of endeavor, Katkar discloses an optical device containing a non-Si substrate (singulated {202a-c; Fig 2; ¶ [0023]} optical wafers formed of III-V materials; ¶ [0020]) bonded to a silicon wafer (Si or CMOS processor; ¶ [0020]; 204; Fig 2; die-to wafer; ¶ [0023]) wherein a transversal dimension of each of the optical pixels is smaller than or equal to 5 microns (less than 5 microns, or less than 1 micron; ¶ [0022]). Accordingly, it would have been obvious to a person having ordinary skill in the art that the same dimension may be attained in Kato in view of Haba as applied to claim 1. One would have been motivated to use these dimensions in order to attain higher, more detailed, image resolution and/or to enable a smaller device, which are desirable attributes for a number of applications known in the art. One would have had a reasonable expectation of success because of the similar bonding methods and endeavors of Katkar (direct, hybrid bonding; Figs 2-3; ¶ [0022]), Kato and Haba.
Claims 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kato; Atsushi (US 2023/0007202; hereinafter Kato) in view of Haba; Belgacem (US 2022/0077087; hereinafter Haba), and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na), and further in view of Haba; Belgacem (US 2021/0407941; hereinafter Haba941).
Regarding claim 19, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein a transversal dimension of each of the first vias is different from a transversal dimension of each of the second vias. However, it would have been obvious to a person having ordinary skill in the art that this may be the case. One may have been motivated to use vias of different dimensions in order to ensure good alignment of one via on the other, and/or when bonding the frontside of one die/wafer to the backside of another die/wafer. For example, see Haba941; Figs 7A-7B, 9A-9D, wherein a frontside via (6a; Figs 9A-9D) has greater transversal dimension than a backside via (6b; Figs 9A-9D), and when bonding a frontside via (e.g. first via ) to a backside via (e.g. second via), the dimensions are different. One would have had a reasonable expectation of success because of the similarity in the bonding methods disclosed, and the differing via sizes being well-known in the art.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kato; Atsushi (US 2023/0007202; hereinafter Kato) in view of Haba; Belgacem (US 2022/0077087; hereinafter Haba) and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na), and further in view of Kwangkaew; Vanapong et al. (US 2019/0353518 A1; hereinafter Kwangkaew).
Regarding claim 22, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not disclose wherein the molding compound layer (Haba; 16; Fig 1D) has a property of shielding infrared light.
In the same field of endeavor, Kwangkaew discloses a molding compound layer having a property of shielding infrared light (light blocking compound 112; Fig 2; ¶ [0005-7] or the compound comprising ink {layer} 312; Figs 4a-4b; ¶ [0025]). Accordingly, it would have been obvious to a person having ordinary skill in the art for the molding compound layer of Kato in view of Haba to have a property of shielding infrared light. One would have been motivated to use such molding compound layer in order to control the region through which infrared light may pass, for example for use in a proximity sensor, such as disclosed by Kwangkaew. One would have had a reasonable expectation of success due to the similar structures and materials disclosed by Kwangkaew and Kato in view of Haba, the light blocking compound, such as 112 disclosed by Kwangkaew, being well-known in the art.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kato; Atsushi (US 2023/0007202; hereinafter Kato) in view of Haba; Belgacem (US 2022/0077087; hereinafter Haba) and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na), further in view of Kwangkaew; Vanapong et al. (US 2019/0353518 A1; hereinafter Kwangkaew), and still further in view of Sul; Sang-Chul et al. (US 2011/0001205; hereinafter Sul).
Regarding claim 23, Kato in view of Haba and Na discloses the optical assembly according to claim 1, but does not specifically disclose wherein the infrared light has a wavelength smaller than or equal to 20 μm.
A person having ordinary skill in the art would expect the term infrared, as it is typically used, to include wavelengths smaller than or equal to 20 μm. In addition, Sul discloses a number of light filters for use with an image sensor which shield passage (reduce or prevent transmittance) of desired wavelength ranges. Fig. 6, for example, shows a filter which has near zero transmittance for wavelengths above 900 nm (0.9 μm; ¶ [0071]), that is, smaller than 20 μm, in the infrared range. Accordingly, it would have been obvious that the optical assembly according to claim 23 having the property of shielding infrared light may include a wavelength smaller than or equal to 20 μm, since Sul has shown it is possible to provide such shielding. One would have been motivated to include such wavelengths in order for the optical assembly to work as intended with a desired wavelength range. One would have had a reasonable expectation of success because Sul discloses that the light filter includes polymer or dye that selectively blocks a light of a desired wavelength (¶ [0017]), and since a polymer or dye are commonly used in mold compounds and/or inks respectively, it would be reasonable to expect them to be compatible with the materials used by Kwangkaew, as applied to claim 23.
Claims 24-30 are rejected under 35 U.S.C. 103 as being unpatentable over Haba; Belgacem (US 2022/0077087; hereinafter Haba) in view of Kato; Atsushi (US 2023/0007202; hereinafter Kato), Haba; Belgacem (US 2021/0407941; hereinafter Haba941), and Na; Yun-Chung et al. (US 2018/0247968; hereinafter Na).
Regarding claim 24, Haba discloses a method of manufacturing a heterogeneously substrate-bonded optical assembly, the method comprising steps of:
(a) providing initial optical chips (optical device 12; Figs 1A-1D; ¶ [0023,0029]) and a processing wafer (11; Figs 1A-1D; ¶ [0023]), wherein: each of the initial optical chips comprises: a second protection layer (dielectric field region, non-conductive material 32; Figs 1A-1D; ¶ [0016,0023,0029]); and second vias (30; Figs 1A-1D; ¶ [0030]) penetrating through the second protection layer; a first protection layer (non-conductive region 26; Figs 1B-1D; ¶ [0028]); and first vias (24a; Figs 1A-1D; ¶ [0023]), penetrating through the first protection layer;
(b) respectively flipping and bonding the initial optical chips to the processor chips in an aligned manner (Fig 1B; ¶ [0024]), so that the first vias and second vias are bonded to one another; ¶ [0030]);
(c) forming a molding compound structure layer (16; Fig 1C; ¶ [0025]) on the initial optical chips and the processing wafer;
(d) removing a portion of the molding compound structure layer (Fig 1D; ¶ [0025]); and
(e) dicing the molding compound structure layer and separating singulated processing wafer portions to form optical assemblies (singulated along singulation lines 38; Fig 1C; ¶ [0025]), wherein in each of the optical assemblies, a transversal dimension of the processor chip is greater than a transversal dimension of the initial optical chip (as shown in Fig 1C, the singulated processing wafer portions comprised between singulation lines 37 have a greater horizontal dimension than initial optical chip 12),
the molding compound structure layer surrounds the initial optical chip and is disposed on a top surface of the first protection layer (in this case, the layer 18 is between a top surface of 26 and 16), the molding compound structure layer has a top surface flush with a backside of the optical chip (Fig 1D; ¶ [0025]).
Haba does not disclose:
(1) wherein: each of the initial optical chips comprises: a non-silicon substrate layer; optical pixels formed on the non-silicon substrate layer; the second protection layer is formed on the optical pixels; the second vias are electrically connected to the optical pixels;
(2) the processing wafer has processor chips each comprising: a silicon-containing substrate; a processor circuit; reader circuits electrically connected to the processor circuit; the first protection layer is disposed on the processor circuit and the reader circuits; the optical pixels are electrically connected to the reader circuits through the second vias and the first vias, respectively;
(3) removing a portion of each of the initial optical chips; the singulated processing wafer portions comprise the processor chips, and wherein in each of the optical assemblies, the optical pixels correspond to the reader circuits in a one-to-one manner; and
(4) a first area of the processor circuit orthogonally projecting onto the top surface of the first protection layer is located outside a second area of the optical chip and a third area of the reader circuits both orthogonally projecting onto the top surface of the first protection layer, and the third area overlaps with the second area.
In the same field of endeavor, Kato discloses a heterogeneously substrate-bonded optical assembly (1A; Figs 9A-9B; ¶ [0121-157], entire document), including wherein:
each of initial optical chips (photoelectric conversion unit 100A; Figs 9A-9B; ¶ [0123-147]) comprises: a non-silicon substrate layer (III-V compound semiconductor; ¶ [0121,0134]); optical pixels (P; Fig 9B; ¶ [0121]) formed on the non-silicon substrate layer; a second protection layer formed on the optical pixels (69B/60W; Fig 9B; ¶ [0127-128]); second vias (69E; Fig 9B; ¶ [0127-129]) electrically connected to the optical pixels;
a processing wafer having processor chips (readout integrated circuit {ROIC} substrate 200A; Figs 9A-9B; ¶ [0123,0154-157]) each comprising: a silicon-containing substrate (71; Fig 9B; ¶ [0148]); a processor circuit; reader circuits (for example, 20; Fig 3; ¶ [0154-155]) electrically connected to the processor circuit (ROIC reads out a charge signal {¶ [0002]} and performs signal processing {a processor circuit} on the read signal {[0002]); a first protection layer disposed on the processor circuit and the reader circuits (72A/70W; Fig 9B; ¶ [0148-149]); the optical pixels are electrically connected to the reader circuits through the second vias and the first vias (¶ [0150,0154]), respectively; and, in each of the optical assemblies, the optical pixels correspond to the reader circuits in a one-to-one manner (¶ [0154,0042]).
Accordingly, it would have been obvious to a person having ordinary skill in the art to have used the method of Haba to manufacture the optical assembly of Kato, wherein the singulated processing wafer portions of Haba comprise the processor chips of Kato, the optical assembly being the heterogeneously substrate-bonded optical assembly and comprising the processor chip, an optical chip corresponding to the initial optical chip and a molding compound layer corresponding to the molding compound structure layer.
One would have been motivated to do this (1) in order to efficiently manufacture the optical assembly using wafer level processing (using a wafer comprising the optical device 12 bonded to the processing wafer 11), (2) to improve reliability of the bonded structures of Kato (Haba; ¶ [0013-14]), and/or (3) possibly to facilitate a planarized top surface to enable additional optical elements such as, for example an anti-reflection film, color filter and/or lens as exemplified in a fourth embodiment of Kato (Kato; optical elements 45,46,47 respectively; Fig 10; ¶ [0163,0165]). One would have had a reasonable expectation of success because the type of die (optical device) and processing wafer used in Haba’s method is not limited (Haba; ¶ [0029]), and may readily apply to the processor chip and optical chip of Kato.
Haba in view of Kato does not disclose removing a portion of each of the initial optical chips.
In the same field of endeavor, Haba941 discloses a method for forming a reconstituted wafer comprising dice (2; Fig 3A,4A,5A; ¶ [0037]) bonded to a wafer (3; Fig 3A4A,5A; ¶ [0037]), wherein the dice are surrounded by a molding compound structure layer (7; Fig 3A,4A,5A; ¶ [0039]), and wherein the method comprises removing a portion of the molding compound layer and a portion each die (Fig 5A; ¶ [0040]).
Accordingly, it would have been obvious to a person having ordinary skill in the art for the method of Haba in view of Kato include removing a portion of each of the initial optical chips, as taught by Haba941. One would have been motivated to do this (1) as a well-known method in the art when making use of both a front-side and back-side surface of a wafer or die, in order to reduce the thickness of the wafer or die once its mechanical support is no longer required (such as when bonded to another wafer), and (2), for example, in order to provide a flush surface to an upper side of each of the optical chips and molding compound structure layer to enable additional optical elements such as, for example an anti-reflection film, color filter and/or lens as exemplified in a fourth embodiment of Kato (Kato; optical elements 45,46,47 respectively; Fig 10; ¶ [0163,0165]). One would have had a reasonable expectation of success because the similarity in the methods of Haba and Haba941, and because the removal is well-known in the art.
Regarding (4), Na discloses a sensor wafer (3130; Fig 33A; ¶ [0404]) comprising a pixel array (3010; Fig 33A; ¶ [0373]) bonded (¶ [0387]) to an IC wafer (3110; Fig 33A; ¶ [0404]), wherein a reader circuit (pixel transistor array 3320; Fig 33A; ¶ [0404]) is positioned such that an orthogonal projection of a third area of the reader circuit 3320 upon a common interface surface shared by 3130 and 3110 overlaps with an orthogonal projection of a second area of the pixel array 3320, and a variety of other exemplary circuit blocks which may comprise processor functions (for example ADC’s 3030; Figs 33A-33C; ¶ [0376,0404]); DSP; Fig 32; ¶ [0399]) positioned in a variety of configurations (Figs 33A-33C) such that an orthogonal projection of a first area each of the other exemplary circuit blocks projected upon the common interface is located outside the second area and the third area.
Accordingly, it would have been obvious to a person having ordinary skill in the art to have combined Na’s disclosure of positional relationships between circuit blocks of a bonded assembly of chips to the assembly of Haba in view of Kato and Haba941 (wherein the pixel array corresponds to the optical chip; the pixel transistors array corresponds to the reader circuit; and the various exemplary circuit blocks corresponds to the processor circuit) to arrive at the method of claim 24. One would have been motivated to do this, with a reasonable expectation of success, because the circuit blocks are well known in the art both in standalone chip form and integrated chip form, and are commonly combined in various alternate integrated and/or assembled configurations depending upon a variety of performance and application requirements.
Regarding claim 25, Haba in view of Kato, Haba941, and Na discloses the method according to claim 24, wherein in the step (d), a portion of each of the non-silicon substrate layers is removed and a non-silicon substrate is correspondingly left. (The initial optical chips comprises the non-silicon substrate layers {Kato; 63; Fig 9B; ¶ [0134} at a side away from the bonding interface. When, as applied to claim 24, a portion of that side of the optical chips is removed in view of Haba941, it would necessarily be in accordance with claim 25 since the non-silicon substrate layers are at the upper side of the chip, and a non-silicon substrate must remain as the photoelectric conversion layer for the device to function as intended.)
Regarding claim 26, Haba in view of Kato, Haba941, and Na discloses the method according to claim 25, but, as applied to claim 25 does not specifically disclose further comprising: forming an optical structure on each of the non-silicon substrates in the step (d).
However, in another example embodiment, Kato discloses an optical structure disposed on the backside of the optical chip (Kato; for example, optical elements 45,46,47 respectively; Fig 10; ¶ [0163,0165]). It would have been obvious to include one or more of 45-47 in the optical assembly as applied to claim 25. One would have been motivated to do this in order to improve image quality by minimizing reflection and improving light transmission to an optical sensor (anti-reflection film 45), to control the wavelength of light reaching an optical sensor (color filter 46) or any number of other optical influences well-known in the art. One would have had a reasonable expectation of success because Kato has disclosed this in the alternate example embodiment, and it is well-known in the art.
Regarding claim 27, Haba in view of Kato, Haba941, and Na discloses the method according to claim 24, but does not specifically disclose wherein in the step (d), each of the non-silicon substrate layers is removed so that the optical pixels are exposed. However, this would have been obvious from the structure disclosed by Kato (Fig 9B), wherein no non-silicon substrate (Kato; 63; Fig 9B) is above the pixels (Kato; P; Fig 9B), as applied to claim 24 in view of Haba and Haba941, and to a person having ordinary skill in the art.
Regarding claim 28, Haba in view of Kato, Haba941, and Na discloses the method according to claim 25, but as applied to claim 26 does not specifically disclose further comprising: forming optical structures on the optical pixels in the step (d).
However, in another example embodiment, Kato discloses an optical structure disposed on the optical pixels (Kato; for example, optical elements 45,46,47 respectively, formed on layer 44 of optical pixels 111B; Fig 10; ¶ [0160-0165]). It would have been obvious to include one or more of 45-47 in the optical assembly as applied to claim 27. One would have been motivated to do this in order to improve image quality by minimizing reflection and improving light transmission to an optical sensor (anti-reflection film 45), to control the wavelength of light reaching an optical sensor (color filter 46) or any number of other optical influences well-known in the art. One would have had a reasonable expectation of success because Kato has disclosed this in the alternate example embodiment, and it is well-known in the art.
Regarding claim 29, Haba in view of Kato, Haba941, and Na discloses the method according to claim 24, wherein in the step (b), the first protection layer (Kato; 72A/70W; Fig 9B) is fusion-bonded (Kato; the bonding of insulating layers through direct joining shown in Fig 9B {¶ [0144]} constitutes fusion bonding) to the second protection layer (Kato; 69B/70W; Fig 9B), and the first vias (Kato; 72E; Fig 9B) are diffusion-bonded (Kato; the bonding of electrodes through direct joining shown in Fig 9B {¶ [0144,0151]} constitutes diffusion bonding) to the second vias (Kato; 69E; Fig 9B). (Further, Haba discloses fusion-bonded dielectrics and diffusion-bonded conductive materials {Haba; ¶ [0016-22]}).
Regarding claim 30, Haba in view of Kato, Haba941, and Na discloses the method according to claim 24, wherein each of the optical assemblies is selected from a group consisting of an optical sensor device (Kato; infrared sensor; ¶ [0121]), an optical filter, a polarizer, a curved-surface optical device, a digital optical device, a diffraction optical element and a metalens.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang; Liang et al. (US 2021/0265331; the prior art discloses a direct bonded optical assembly);
Liff; Shawna M. et al. (US 2020/0286871; the prior art discloses an optical assembly comprising hybrid bonding).
Enquist; Paul M. et al. (US 2019/0355706; the prior art discloses a bonded assembly of a smaller die over a larger die, the smaller die being surrounded by a mold compound).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817