DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election
Applicant’s election without traverse of Group II, claims 1-9 and 16-20, in the reply filed on 11/12/2025 is acknowledged.
IDS
The IDS document(s) filed on 08/24/2023 and 01/09/2026 have been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okawa (US 2016/0380091 A1), hereafter “Okawa”.
As to claim 1, Okawa teaches a hybrid gate field effect transistor, comprising:
a channel layer (Fig. 1, 18, ⁋ [0025]);
a source (30, ⁋ [0030]), a drain (32), and a gate structure (34+36) disposed on the channel layer, wherein the source, the drain, and the gate structure are disposed in a same layer (Fig.1), wherein the gate structure comprises a first structural layer (35, ⁋ [0063]) and a second structural layer (34, ⁋ [0030]) that are disposed in a same layer, and the second structural layer wraps the first structural layer (Fig. 2+15, ⁋ [0066], “an arrangement such as those shown in FIGS. 2, 7, and 8 may be employed”), wherein the first structural layer is an N-type gallium nitride layer (⁋ [0063], “n-type gate layers 35 provided as a part of the surface layer portion of the p-type gate layer 34”) or an intrinsic gallium nitride layer, and the second structural layer is a P-type gallium nitride layer (⁋ [0033], “p-type gate layer 34 is made of p-type GaN”); and
a gate metal layer (Fig. 15, 36, ⁋ [0030) in ohmic contact with at least the first structural layer (⁋ [0063], “each of these n-type gate layers 35 are in ohmic contact with the gate electrode 36”).
As to claim 2, Okawa teaches the hybrid gate field effect transistor according to claim 1, wherein the channel layer comprises a gallium nitride layer and an aluminum gallium nitride barrier layer (⁋ [0029]); and
the source, the drain, and the gate structure are disposed on the aluminum gallium nitride barrier layer (Fig. 1).
As to claim 3, Okawa teaches the hybrid gate field effect transistor according to claim 2, further comprising:
a substrate (12, Fig, 1, ⁋ [0026]) and a buffer layer (14, ⁋ [0027]) disposed on the substrate, wherein
the gallium nitride layer is on the buffer layer (Fig 1. shows 18 formed on 14).
As to claim 4, Okawa teaches the hybrid gate field effect transistor according to claim 3, wherein a material of the substrate is silicon, sapphire, silicon carbide, or a gallium nitride material (⁋ [0026]).
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Okawa, and further in view of Saito et al. (US 2016/0225886 A1), hereafter “Saito”.
As to claim 5, Okawa teaches the hybrid gate field effect transistor according to claim 2, but fails to teach further comprising:
a passivation layer, wherein the passivation layer and the aluminum gallium nitride barrier layer are stacked; and
wherein the source, the drain, and the gate structure run through the passivation layer, and are exposed outside of the passivation layer.
Saito is a similar device which teaches a barrier layer 16 made of undoped AlGaN (Fig. 1, 16, ⁋ [0030]) with a source electrode 18, drain electrode 10, a gate electrode 24, and a passivation layer 32 (⁋ [0026]) on the AlGaN layer 16 (see Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the passivation layer of Saito into the device of Okawa in order to protect the surface of the barrier layer 16 (⁋ [0037]).
As to claim 6, Okawa teaches the hybrid gate field effect transistor according to claim 3, but fails to teach further comprising: a passivation layer, wherein the passivation layer and the aluminum gallium nitride barrier layer are stacked; and wherein the source, the drain, and the gate structure run through the passivation layer, and are exposed outside of the passivation layer.
Saito is a similar device which teaches a barrier layer 16 made of undoped AlGaN (Fig. 1, 16, ⁋ [0030]) with a source electrode 18, drain electrode 10, a gate electrode 24, and a passivation layer 32 (⁋ [0026]) on the AlGaN layer 16 (see Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the passivation layer of Saito into the device of Okawa in order to protect the surface of the barrier layer 16 (⁋ [0037]).
As to claim 7, Okawa teaches the hybrid gate field effect transistor according to claim 4, but fails to teach further comprising: a passivation layer, wherein the passivation layer and the aluminum gallium nitride barrier layer are stacked; and wherein the source, the drain, and the gate structure run through the passivation layer, and are exposed outside of the passivation.
Saito is a similar device which teaches a barrier layer 16 made of undoped AlGaN (Fig. 1, 16, ⁋ [0030]) with a source electrode 18, drain electrode 10, a gate electrode 24, and a passivation layer 32 (⁋ [0026]) on the AlGaN layer 16 (see Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the passivation layer of Saito into the device of Okawa in order to protect the surface of the barrier layer 16 (⁋ [0037]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Okawa.
As to claim 8, Okawa teaches the hybrid gate field effect transistor according to claim 1, but fails to teach wherein the first structural layer is cylindrical, square columnar, or cylindroid.
On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As to claim 9, Okawa teaches the hybrid gate field effect transistor according to claim 1, however, fails to teach wherein the gate metal layer is in Schottky contact with the second structural layer in Embodiment 6.
Okawa does teach in another embodiment, Embodiment 1, the gate electrode 36 in contact with a p-type gate layer 34 and including a Schottky electrode portion 37 (⁋ [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the Schottky contact as taught by Okawa into Embodiment 6 for the benefit of suppressing the gate-leakage current (⁋ [0044]).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Okawa, and further in view of Ramaswamy et al. (US 2020/0219772 A1), hereafter “Ramaswamy”.
As to claim 16, Okawa teaches a switch circuit, a hybrid gate field effect transistor, the hybrid gate field effect transistor comprising:
a channel layer (Fig. 1, 18, ⁋ [0025])
a source (30, ⁋ [0030]), a drain (32), and a gate structure (34+36) that disposed on the channel layer, wherein the source, the drain, and the gate structure are disposed in a same layer (Fig. 1), wherein the gate structure comprises a first structural layer (35, ⁋ [0063]) and a second structural layer (34, ⁋ [0030]) that are disposed in a same layer, and the second structural layer wraps the first structural layer (Fig. 2+15, ⁋ [0066], “an arrangement such as those shown in FIGS. 2, 7, and 8 may be employed”), wherein the first structural layer is an N-type gallium nitride layer (⁋ [0063], “n-type gate layers 35 provided as a part of the surface layer portion of the p-type gate layer 34”) or an intrinsic gallium nitride layer, and the second structural layer is a P-type gallium nitride layer layer (⁋ [0033], “p-type gate layer 34 is made of p-type GaN”); and
a gate metal layer (Fig. 15, 36, ⁋ [0030) in ohmic contact with at least the first structural layer (⁋ [0063], “each of these n-type gate layers 35 are in ohmic contact with the gate electrode 36”).
Okawa fails to teach a mainboard.
Ramaswamy teaches a similar device with a main board (⁋ [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching of Ramaswamy’s main board into the device of Okawa in order to provide electrical support and control proper functionality.
As to claim 17, Okawa in view of Ramaswamy teach the switch circuit according to claim 16, wherein the channel layer comprises a gallium nitride layer and an aluminum gallium nitride barrier layer (⁋ [0029]); and
the source, the drain, and the gate structure are disposed on the aluminum gallium nitride barrier layer (Fig. 1).
As to claim 18, Okawa in view of Ramswamy teach the switch circuit according to claim 17, wherein the hybrid gate field effect transistor further comprises:
a substrate (12, Fig, 1, ⁋ [0026]) and a buffer layer (14, ⁋ [0027]), wherein
the gallium nitride layer is on the buffer layer (Fig. 1 shows 18 formed on 14).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Okawa, in view of Ramaswamy, and further in view of Saito.
As to claim 19, Okawa in view of Ramaswamy teach the switch circuit according to claim 17, but fail to teach wherein the hybrid gate field effect transistor further comprises:
a passivation layer, wherein the passivation layer and the aluminum gallium nitride barrier layer are stacked; and
wherein the source, the drain, and the gate structure run through the passivation layer, and are exposed outside of the passivation layer.
Saito is a similar device which teaches a barrier layer 16 made of undoped AlGaN (Fig. 1, 16, ⁋ [0030]) with a source electrode 18, drain electrode 10, a gate electrode 24, and a passivation layer 32 (⁋ [0026]) on the AlGaN layer 16 (see Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the passivation layer of Saito into the device of Okawa and Ramaswamy in order to protect the surface of the barrier layer 16 (⁋ [0037]).
As to claim 20, Okawa in view of Ramaswamy teach the switch circuit according to claim 18, but fail to teach wherein the hybrid gate field effect transistor further comprises:
a passivation layer, wherein the passivation layer and the aluminum gallium nitride barrier layer are stacked; and
wherein the source, the drain, and the gate structure run through the passivation layer, and are exposed outside of the passivation layer (see claim 19 and see claim objection above).
Saito is a similar device which teaches a barrier layer 16 made of undoped AlGaN (Fig. 1, 16, ⁋ [0030]) with a source electrode 18, drain electrode 10, a gate electrode 24, and a passivation layer 32 (⁋ [0026]) on the AlGaN layer 16 (see Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the passivation layer of Saito into the device of Okawa and Ramaswamy in order to protect the surface of the barrier layer 16 (⁋ [0037]).
Conclusion
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/CARNELL HUNTER III/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893