Prosecution Insights
Last updated: May 29, 2026
Application No. 18/166,473

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING PACKAGE STRUCTURE

Non-Final OA §103§112
Filed
Feb 08, 2023
Priority
Jun 27, 2022 — CN 202210745228.8 +1 more
Examiner
HANUMASAGAR, SHAMITA S
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Changxin Memory Technologies Inc.
OA Round
2 (Non-Final)
82%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
71%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
9 granted / 11 resolved
+13.8% vs TC avg
Minimal -11% lift
Without
With
+-10.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
33 currently pending
Career history
63
Total Applications
across all art units

Statute-Specific Performance

§103
75.6%
+35.6% vs TC avg
§102
13.4%
-26.6% vs TC avg
§112
11.0%
-29.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 11 resolved cases

Office Action

§103 §112
Attorney Docket Number: 2210808PCT-US-CXMT-CT Filing Date: 02/08/2023 Claimed Priority Dates: 07/27/2022 (PCT/CN2022/108351) 06/27/2022 (CN 202210745228.8) Inventor: Dai Examiner: Shamita S. Hanumasagar DETAILED ACTION This Office action responds to the amendment filed on 07/12/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Amendment Status The amendment filed on 07/12/2025 in reply to the previous Office action mailed on 04/22/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-6, 8-12, 15-16, and 19-23. Annotated Figure Depicted below is an annotated version of Figure 4 of Hsu (US 2009/02494962), henceforth referred to as “annotated fig. 4”. No changes besides annotations have been made to the figure. PNG media_image1.png 373 520 media_image1.png Greyscale Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 21 recites the limitation “the top layer welding layer”. There is insufficient antecedent basis for this limitation in the claim. Claim 22 recites the limitation “a top surface of the second pad”. There is insufficient antecedent basis for the limitation “the second pad” in the claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 8-12, and 19-23 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 2009/0294962) in view of Lee (US 2013/0256876), Fang (US 2003/0122255), and Shih (US 2009/0308652). Regarding claim 1, Hsu (see, e.g., annotated fig. 4) shows most aspects of the instant invention, including a package structure comprising: a substrate 20, wherein at least one welding pad 24a is disposed on a surface of the substrate; a chip 25a located on the substrate and spaced apart from the substrate; and at least one solder ball 254; and a solder resist layer 21a disposed on the surface of the substrate wherein: the at least one welding pad 24a comprises a bottom layer welding pad and a top layer welding pad; at least two of peripheral surfaces of the top layer welding pad are protruded relative to peripheral surfaces of the bottom layer welding pad; the at least one solder ball is connected to the substrate 20 and the chip 25a; the at least one solder ball 254 wraps the top layer welding pad; and the bottom layer welding pad penetrates through the solder resist layer 21a Although Hsu demonstrates that Hsu’s package structure comprises a top layer welding pad and a bottom layer welding pad, Hsu fails to specify that they are stacked onto one another. Lee, in a similar device to Hsu, illustrates a welding pad 246a, 424a, 230 comprising a top layer welding pad 246a and a bottom layer welding pad 242a, 230, wherein Lee’s top layer welding pad and bottom layer welding pad are stacked onto one another (see, e.g., Lee: fig. 3). Lee is evidence showing that one of ordinary skill in the art would have appreciated that having a unitary welding pad comprising a top layer welding pad and a bottom layer welding pad would have been equivalent to a welding pad comprising a top layer welding pad and a bottom layer welding pad stacked onto one another, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the welding pad structures of Hsu and Lee would yield the predictable result of providing a welding pad to connect a solder ball and substrate. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the simultaneously-formed top and bottom layer welding pads of Hsu or the stacked top and bottom layer welding pads of Lee, because both these structures were recognized in the semiconductor art as equivalents for their use as welding pad structures and both would yield the predictable result of providing a welding pad to connect a solder ball and substrate. Furthermore, although Hsu teaches that solder ball 254 is connected to the substrate 20 and chip 25a, Hsu fails to specify that this connection was formed through welding. Fang, in a similar device to Hsu, teaches welding to be a conventional method for connecting solder balls to chips and substrates (see, e.g., Fang: par.0010/ll.6-8). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the solder ball welded to the substrate and chip, as taught by Fang, or to have the solder ball connected to the substrate and chip by another method, because both these structures were recognized in the semiconductor art as equivalents for their use as solder ball connection structures and both would yield the predictable result of connecting the solder ball to the chip and substrate. Additionally, Hsu shows a structure having a bottom layer welding pad in direct contact with a solder resist layer and therefore fails to explicitly specify that a gap is formed between the solder resist layer and the bottom layer welding pad. Shih, in a similar device to Hsu, teaches that there are multiple methods for a solder resist layer to expose a welding pad, and illustrates a device having a solder resist layer 27a and a welding pad comprising a top layer welding pad 25a stacked on top of a bottom layer welding pad 24a, wherein a gap 270a is formed between the solder resist layer and the bottom layer welding pad (see, e.g., Shih: figs. 2J and 2K and pars.0037/ll.4-8 and 0038). Shih further shows another embodiment of the same device wherein the solder resist layer 27a directly contacts the bottom layer welding pad 24a (see, e.g., Shih: fig. 2J’), whereby Shih asserts that the two designs are interchangeable (see, e.g., Shih: pars.0037/ll.4-8 and 0038). Accordingly, Shih teaches that a device having a gap formed between a solder resist layer and a bottom layer welding pad (see, e.g., Shih: fig. 2J) functions equivalently to a device having a solder resist layer in direct contact with a bottom layer welding pad (see, e.g., Shih: fig. 2J’), as both designs equally support exposing a welding pad for external electrical connection (see, e.g., Shih: pars.0038/ll.1-5, 0062/ll.5-7, and 0073/ll.6-12). Shih is evidence showing that one of ordinary skill in the art would have appreciated that a structure having a gap formed between a solder resist layer and a bottom layer welding pad would have been equivalent to a structure having a solder resist layer directly contacting a bottom layer welding pad, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the solder resist layer structures of Hsu and Shih would yield the predictable result of appropriately exposing welding pads for external electrical connection while inhibiting undesired bridging. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a solder resist layer comprising a gap between the solder resist layer and a bottom layer welding pad, as taught by Shih’s figure 2J, or to have a solder resist layer and bottom layer welding pad directly contact, as taught by Hsu and Shih’s figure 2J’, because both these structures were recognized in the semiconductor art as equivalents for their use as solder resist layer structures and both would yield the predictable result of appropriately exposing welding pads for external connection while inhibiting undesired bridging. Regarding claim 19, Hsu (see, e.g., annotated fig. 4) shows most aspects of the instant invention, including a package structure comprising: a substrate 20, wherein at least one welding pad 24a is disposed on a surface of the substrate; a solder resist layer 21a disposed on the surface of the substrate at least one solder ball 254 wherein: the at least one welding pad 24a comprises a bottom layer welding pad and a top layer welding pad; at least two of peripheral surfaces of the top layer welding pad are protruded relative to peripheral surfaces of the bottom layer welding pad; the bottom layer welding pad penetrates through the solder resist layer 21a Although Hsu demonstrates that Hsu’s package structure comprises a top layer welding pad and a bottom layer welding pad, Hsu fails to specify that they are stacked onto one another. Lee, in a similar device to Hsu, illustrates a welding pad 246a, 424a, 230 comprising a top layer welding pad 246a and a bottom layer welding pad 242a, 230, wherein Lee’s top layer welding pad and bottom layer welding pad are stacked onto one another (see, e.g., Lee: fig. 3). Lee is evidence showing that one of ordinary skill in the art would have appreciated that having a unitary welding pad comprising a top layer welding pad and a bottom layer welding pad would have been equivalent to a welding pad comprising a top layer welding pad and a bottom layer welding pad stacked onto one another. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the simultaneously-formed top and bottom layer welding pads of Hsu or the stacked top and bottom layer welding pads of Lee, because both these structures were recognized in the semiconductor art as equivalents for their use as welding pad structures and both would yield the predictable result of providing a welding pad to connect a solder ball and substrate. Furthermore, Hsu shows a structure having a bottom layer welding pad in direct contact with a solder resist layer and therefore fails to explicitly specify that a gap is formed between the solder resist layer and the bottom layer welding pad. Shih, in a similar device to Hsu, teaches that there are multiple methods for a solder resist layer to expose a welding pad, and illustrates a device having a solder resist layer 27a and a welding pad comprising a top layer welding pad 25a stacked on top of a bottom layer welding pad 24a, wherein a gap 270a is formed between the solder resist layer and the bottom layer welding pad (see, e.g., Shih: figs. 2J and 2K and pars.0037/ll.4-8 and 0038). Shih further shows another embodiment of the same device wherein the solder resist layer 27a directly contacts the bottom layer welding pad 24a (see, e.g., Shih: fig. 2J’), whereby Shih asserts that the two designs are interchangeable (see, e.g., Shih: pars.0037/ll.4-8 and 0038). Accordingly, Shih teaches that a device having a gap formed between a solder resist layer and a bottom layer welding pad (see, e.g., Shih: fig. 2J) functions equivalently to a device having a solder resist layer in direct contact with a bottom layer welding pad (see, e.g., Shih: fig. 2J’), as both designs equally support exposing a welding pad for external electrical connection (see, e.g., Shih: pars.0038/ll.1-5, 0062/ll.5-7, and 0073/ll.6-12). Shih is evidence showing that one of ordinary skill in the art would have appreciated that a structure having a gap formed between a solder resist layer and a bottom layer welding pad would have been equivalent to a structure having a solder resist layer directly contacting a bottom layer welding pad, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the solder resist layer structures of Hsu and Shih would yield the predictable result of appropriately exposing welding pads for external electrical connection while inhibiting undesired bridging. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a solder resist layer comprising a gap between the solder resist layer and a bottom layer welding pad, as taught by Shih’s figure 2J, or to have a solder resist layer and bottom layer welding pad directly contact, as taught by Hsu and Shih’s figure 2J’, because both these structures were recognized in the semiconductor art as equivalents for their use as solder resist layer structures and both would yield the predictable result of appropriately exposing welding pads for external connection while inhibiting undesired bridging. Regarding claim 2, Hsu (see, e.g., annotated fig. 4) shows that all the peripheral surfaces of the top layer welding pad are protruded relative to all the peripheral surfaces of the bottom layer welding pad. Regarding claim 3, Hsu (see, e.g., annotated fig. 4) shows that an orthographic projection of the bottom layer welding pad on the surface of the substrate 20 is located at a center within an orthographic projection of the top layer welding pad on the surface of the substrate. Regarding claim 4, Hsu (see, e.g., annotated fig. 4) shows that a bottom surface of the top layer welding pad is located higher than a top surface of the solder resist layer 21a. Regarding claim 5, Hsu (see, e.g., annotated fig. 4) shows that the package structure comprises a plurality of welding pads 24a, and that the solder resist layer 21a is located between any adjacent bottom layer welding pads of bottom layer welding pads of the plurality of welding pads. Regarding claim 6, Hsu is silent with respect to a difference between a height of the bottom surface of the top layer welding pad and a height of the top surface of the solder resist layer. However, height differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). Since the applicant has not established the criticality (see next paragraph below) of the claimed height difference, i.e., 3 µm to 7 µm, it would have been obvious to one of ordinary skill in the art to use these values in the device of Hsu. CRITICALITY The specification contains no disclosure of either the critical nature of the claimed height difference or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Regarding claim 8, Hsu (see, e.g., annotated fig. 4) fails to explicitly specify that a gap is formed between Hsu’s solder resist layer and bottom layer welding pad, and thus fails to explicitly specify that that the peripheral surfaces of Hsu’s top layer welding pad are protruded by a distance less than or equal to a width of the gap relative to the peripheral surfaces of the bottom layer welding pad. Shih, in a similar device to Hsu, teaches that there are multiple methods for a solder resist layer to expose a welding pad, and illustrates as such through a device having a solder resist layer 27a and a welding pad comprising a top layer welding pad 25a stacked on top of a bottom layer welding pad 24a, wherein a gap 270a is formed between the solder resist layer and the bottom layer welding pad, and wherein the peripheral surfaces of the top layer welding pad are protruded by a distance less than or equal to a width of the gap relative to the peripheral surfaces of the bottom layer welding pad (see, e.g., Shih: figs. 2J and 2K and pars.0037/ll.4-8 and 0038). Shih further shows another embodiment of the same device wherein the solder resist layer 27a directly contacts the bottom layer welding pad 24a (see, e.g., Shih: fig. 2J’), thus negating a gap formed between the solder resist layer and the bottom layer welding pad, whereby Shih asserts that the two designs are interchangeable (see, e.g., Shih: pars.0037/ll.4-8 and 0038). Accordingly, Shih teaches that a device having a gap formed between a solder resist layer and a bottom layer welding pad, wherein the peripheral surfaces of a top layer welding pad are protruded by a distance less than or equal to a width of the gap relative to the peripheral surfaces of the bottom layer welding pad (see, e.g., Shih: fig. 2J), functions equivalently to a device having a solder resist layer in direct contact with a bottom layer welding pad and thereby negating a gap (see, e.g., Shih: fig. 2J’), as both designs equally support exposing a welding pad for external electrical connection (see, e.g., Shih: pars.0038/ll.1-5, 0062/ll.5-7, and 0073/ll.6-12). Shih is evidence showing that one of ordinary skill in the art would have appreciated that a structure having a gap formed between a solder resist layer and a bottom layer welding pad, wherein the peripheral surfaces of a top layer welding pad are protruded by a distance less than or equal to a width of the gap relative to the peripheral surfaces of the bottom layer welding pad, would have been equivalent to a structure having a solder resist layer directly contacting a bottom layer welding pad and thus negating a gap, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the solder resist layer structures of Hsu and Shih would yield the predictable result of appropriately exposing welding pads for external electrical connection while inhibiting undesired bridging. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a solder resist layer comprising a gap between the solder resist layer and a bottom layer welding pad, wherein the peripheral surfaces of a top layer welding pad are protruded by a distance less than or equal to a width of the gap relative to the peripheral surfaces of the bottom layer welding pad, as taught by Shih’s figure 2J, or to have a solder resist layer and bottom layer welding pad directly contact, as taught by Hsu and Shih’s figure 2J’, because both these structures were recognized in the semiconductor art as equivalents for their use as solder resist layer structures and both would yield the predictable result of appropriately exposing welding pads for external connection while inhibiting undesired bridging. Regarding claim 9, Hsu (see, e.g., annotated fig. 4) shows that at least one support bump 253a is disposed on a surface of the chip 25a facing toward the substrate 20, and the at least one solder ball 254 is connected to the at least one support bump. Regarding claim 10, Hsu (see, e.g., annotated fig. 4) shows that a width of the at least one support bump 253a is greater than a width of the top layer welding pad. Regarding claim 11, Hsu is silent regarding a difference between the width of the at least one support bump and the width of the top layer welding pad. However, width differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the difference of the claimed widths, i.e., greater than 10 µm, it would have been obvious to one of ordinary skill in the art to use these values in the support bump and top layer welding pad of Hsu. See also the comments stated above in paragraphs 27-29 with respect to claim 6 regarding criticality, which are considered to be repeated here. Regarding claim 12, Hsu is silent regarding a difference between a width of the top layer welding pad and a width of the bottom layer welding pad. However, width differences will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such differences are critical. Since the applicant has not established the criticality of the difference of the claimed widths, i.e., greater than 10 µm, it would have been obvious to one of ordinary skill in the art to use these values in the top and bottom layer welding pads of Hsu. See also the comments stated above in paragraphs 27-29 with respect to claim 6, which are considered to be repeated here. Regarding claim 20, Hsu (see, e.g., annotated fig. 4) shows that a bottom surface of the top layer welding pad is located higher than a top surface of the solder resist layer 21a. Regarding claim 21, Hsu shows a structure having a bottom layer welding pad in direct contact with a solder resist layer and therefore fails to explicitly specify that a gap is formed between Hsu’s solder resist layer and bottom layer welding pad, and that such a gap has a width. Shih, in a similar device to Hsu, teaches that there are multiple methods for a solder resist layer to expose a welding pad, and illustrates a device having a solder resist layer 27a and a welding pad comprising a top layer welding pad 25a stacked on top of a bottom layer welding pad 24a, wherein a gap 270a is formed between the solder resist layer and the bottom layer welding pad, and wherein the gap has a defined width (see, e.g., Shih: figs. 2J and 2K and pars.0037/ll.4-8 and 0038). Shih further shows another embodiment of the same device wherein the solder resist layer 27a directly contacts the bottom layer welding pad 24 (see, e.g., Shih: fig. 2J’ and par.0038/ll.1-5), whereby Shih asserts that the two designs are interchangeable (see, e.g., Shih: pars.0037/ll.4-8 and 0038). Accordingly, Shih teaches that a device having a gap formed between a solder resist layer and a bottom layer welding pad, wherein the gap has a width (see, e.g., Shih: fig. 2J), functions equivalently to a device having a solder resist layer in direct contact with a bottom layer welding pad (see, e.g., Shih: fig. 2J’), as both designs equally support exposing a welding pad for external electrical connection (see, e.g., Shih: pars.0038/ll.1-5, 0062/ll.5-7, and 0073/ll.6-12). Shih is evidence showing that one of ordinary skill in the art would have appreciated that a structure having a gap formed between a solder resist layer and a bottom layer welding pad, wherein the gap has a width, would have been equivalent to a structure having a solder resist layer directly contacting a bottom layer welding pad, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the solder resist layer structures of Hsu and Shih would yield the predictable result of appropriately exposing welding pads for external electrical connection while inhibiting undesired bridging. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a solder resist layer comprising a gap between the solder resist layer and a bottom layer welding pad, wherein the gap has a width, as taught by Shih’s figure 2J, or to have a solder resist layer and bottom layer welding pad directly contact, as taught by Hsu and Shih’s figure 2J’, because both these structures were recognized in the semiconductor art as equivalents for their use as solder resist layer structures and both would yield the predictable result of appropriately exposing welding pads for external connection while inhibiting undesired bridging. Regarding claim 22, Hsu (see, e.g., annotated fig. 4) shows most aspects of the instant invention, including a bottom layer welding pad, a top layer welding pad located on the bottom layer welding pad, and a top surface of a solder resist layer 21a (see also paragraphs 48-37 above). However, Hsu fails to show that the bottom layer welding pad comprises a first welding and a second welding pad which are stacked onto one another and that the top layer welding pad is located on the second welding pad. Lee, in a similar device to Hsu, teaches a bottom layer welding pad 242a, 230 comprising a first welding pad 230 and a second welding pad 242a which are stacked onto one another, wherein a top layer welding pad 246a is located on the second welding pad (see, e.g., Lee: fig. 3). Lee is evidence showing that one of ordinary skill in the art would have appreciated that having a bottom layer welding pad comprising a unitary structure with a top layer welding pad located on the bottom layer welding pad would have been equivalent to a bottom layer welding pad comprising first and second welding pad stacked onto one another with a top layer welding pad is located on the second welding pad, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the bottom layer welding pad structures of Hsu and Lee would yield the predictable result of providing a base for a top layer welding pad. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the bottom layer welding pad comprise a unitary structure, as taught by Hsu, or to have the bottom layer welding pad comprise stacked first and second welding pads, wherein the top layer welding pad is located on the second welding pad, as taught by Lee, because both these structures were recognized in the semiconductor art as equivalents for their use as bottom layer welding pad structures and both would yield the predictable result of providing a base for a top layer welding pad. Regarding claim 23, Hsu fails to explicitly specify that the bottom layer welding pad comprises a first welding pad and a second welding pad stacked on the first welding pad. Furthermore, Hsu shows a structure having a bottom layer welding pad in direct contact with a solder resist layer and therefore fails to explicitly specify that a gap is at least located between a second welding pad and the solder resist layer. Shih, in a similar device to Hsu, teaches that there are multiple methods for a solder resist layer to expose a welding pad, and illustrates as such through a device having a solder resist layer 27a and a welding pad comprising a top layer welding pad 25a stacked on a bottom layer welding pad 24a, wherein the bottom layer welding pad comprises a first welding pad 21 and a second welding pad 24 stacked on the first welding pad, and wherein a gap 270a is at least located between the solder resist layer and the second welding pad (see, e.g., Shih: figs. 2J and 2K and pars.0037/ll.4-8 and 0038). Shih further shows another embodiment of the same device wherein the solder resist layer 27a directly contacts the second welding pad 24 (see, e.g., Shih: fig. 2J’), whereby Shih asserts that the two designs are interchangeable (see, e.g., Shih: pars.0037/ll.4-8 and 0038). Accordingly, Shih teaches that a device having a gap at least located between a solder resist layer and a second welding pad (see, e.g., Shih: fig. 2J) functions equivalently to a device having a solder resist layer in direct contact with a second welding pad (and thus bottom layer welding pad) (see, e.g., Shih: fig. 2J’), as both designs equally support exposing a welding pad for external electrical connection (see, e.g., Shih: pars.0038/ll.1-5, 0062/ll.5-7, and 0073/ll.6-12). Shih is evidence showing that one of ordinary skill in the art would have appreciated that having a bottom layer welding pad comprising a unitary structure would have been equivalent to a bottom layer welding pad comprising a second welding pad stacked on a first welding pad, and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the bottom layer welding pad structures of Hsu and Shih would yield the predictable result of providing a base for a top layer welding pad. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the bottom layer welding pad comprise a unitary structure, as taught by Hsu, or to have the bottom layer welding pad comprise a second welding pad stacked on a first welding pad, as taught by Shih, because both these structures were recognized in the semiconductor art as equivalents for their use as bottom layer welding pad structures and both would yield the predictable result of providing a base for a top layer welding pad. Furthermore, Shih is evidence showing that one of ordinary skill in the art would have appreciated that a structure having a gap at least located between a solder resist layer and a second welding pad would have been equivalent to a structure having a solder resist layer directly contacting a second welding pad (or bottom layer welding pad), and that such differences would result in no unexpected change in the performance of the device of Hsu. That is, both the solder resist layer structures of Hsu and Shih would yield the predictable result of appropriately exposing welding pads for external electrical connection while inhibiting undesired bridging. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have a solder resist layer comprising a gap at least located between a solder resist layer and a second welding pad, as taught by Shih’s figure 2J, or to have a solder resist layer and second (or bottom) welding pad directly contact, as taught by Hsu and Shih’s figure 2J’, because both these structures were recognized in the semiconductor art as equivalents for their use as solder resist layer structures and both would yield the predictable result of appropriately exposing welding pads for external connection while inhibiting undesired bridging. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Lee, Fang, Shih, and Lin (US 2013/0161810). Regarding claim 15, Hsu/Lee/Fang/Shih shows most aspects of the instant invention (see paragraphs 10-16 above). However, Hsu fails to show that the bottom layer welding pad comprises a first welding and a second welding pad which are stacked onto one another. Lee, in a similar device to Hsu, teaches a bottom layer welding pad 242a, 230 comprising a first welding pad 230 and a second welding pad 242a which are stacked onto one another (see, e.g., Lee: fig. 3). Lee is evidence showing that one of ordinary skill in the art would have appreciated that having a bottom layer welding pad comprising a unitary structure would have been equivalent to a bottom layer welding pad comprising first and second welding pad stacked onto one another. Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the bottom layer welding pad comprise a unitary structure, as taught by Hsu, or to have the bottom layer welding pad comprise stacked first and second welding pads, as taught by Lee, because both these structures were recognized in the semiconductor art as equivalents for their use as bottom layer welding pad structures and both would yield the predictable result of providing a base for a top layer welding pad. Furthermore, Hsu teaches that a plurality of conductive layers 202 are disposed on the surface of the substrate 20 and spaced apart from each other, and that the plurality of conductive layers are disposed on a same layer as the first welding pad. Hsu also teaches that a solder resist layer 21a is disposed on the surface of the substrate 20 and covers the plurality of conductive layers 202. However, Hsu fails to teach that the plurality of conductive layers are spaced apart from the first welding pad. Lin, like Hsu, teaches having a plurality of conductive layers 304a disposed on a surface of a substrate 300 and spaced apart from each other, wherein the plurality of conductive layers are disposed on a same layer as a welding pad 302 and are covered by a solder resist layer 308, wherein the solder resist layer 306 is also disposed on the surface of the substrate (see, e.g., Lin: fig. 5). Lin teaches that this structure allows for the conductive layers 304a to serve as signal/ground trace segments and facilitate the routing of the semiconductor package 500b (see, e.g., Lin: par.0025/ll.19-22). Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to use conductive layer arrangement taught by Lin in the device of Hsu, so as to facilitate the routing capabilities of Hsu’s semiconductor package. Regarding claim 16, Lin (see, e.g., Lin: fig. 5) teaches that the package structure 500b comprises a plurality of welding pads 302, and at least one conductive layer 304a is disposed between any adjacent first welding pads of first welding pads. Response to Arguments Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection. Conclusion Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action. Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000. /Shamita S. Hanumasagar/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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Prosecution Timeline

Feb 08, 2023
Application Filed
Apr 22, 2025
Non-Final Rejection mailed — §103, §112
Jul 12, 2025
Response Filed
Oct 01, 2025
Final Rejection mailed — §103, §112
Nov 24, 2025
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

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MULTI-THRESHOLD VOLTAGE INTEGRATION SCHEME FOR SEMICONDUCTOR DEVICES
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CHIP PACKAGING STRUCTURE AND CHIP PACKAGING METHOD
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Gate-all-around integrated structures having gate height reduction and dielectric capping material with shoulder portions inside gate stack
4y 8m to grant Granted Feb 24, 2026
Patent 12482777
COPPER PILLAR BUMP STRUCTURE AND METHOD OF MANUFACTURING THE SAME
3y 2m to grant Granted Nov 25, 2025
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METAL OXIDE SEMICONDUCTOR WITH MULTIPLE DRAIN VIAS
2y 10m to grant Granted Sep 02, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
82%
Grant Probability
71%
With Interview (-10.7%)
3y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 11 resolved cases by this examiner. Grant probability derived from career allowance rate.

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