DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of group I, species I(a), claims 1-10, in the reply filed on July 14, 2025 is acknowledged. The traversal is on the ground(s) that “search and examination of all the claims may be made without serious burden”. This is not found persuasive because examining several distinct and separated inventions impose serious burden on the examiner due to the uniqueness of each invention.
The requirement is still deemed proper and is therefore made FINAL.
Claims 11-17 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on July 14, 2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on February 9, 2023 and April 11, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "VS" and "VSP" have both been used to designate “vertical semiconductor layer”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “VS” has been used to designate “vertical structure”, “vertical channel structure” and “vertical semiconductor layer”. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: symbols (i.e. “x”) in chemical symbols/formulas should be in subscript format (first occurrence: [0028]).
Appropriate correction is required.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 2 and 3 are objected to because of the following informalities: 1) “HfOx” should read “HfOx”; 2) Undefined acronyms/symbols, such as “HfOx”. The examiner suggests that applicant spell out all the acronyms/symbols when using them for the first time in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-3, 8 and 9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There appears to be no adequate description in the specification on how this feature was done for the claim limitation of "the ferroelectric layer is doped with at least one material of HfOx", as recited in claim 2. There is no adequate description in the elected embodiment of Figs. 12-19, 4 and 6 for the claim limitation of "the vertical channel layer is directly provided on the ferroelectric layer, in response to the stress control layer being completely removed through the process of removing the at least the portion of the stress control layer", as recited in claim 8; and “the forming of the vertical structure … includes: sequentially forming a gate insulating layer, the vertical channel layer, and the vertical semiconductor layer on the ferroelectric layer”, as recited in claim 9.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitations of "… at least one material of HfOx, Al, Zr, or Si", as recited in claim 2, are unclear as to whether the listed elements are alternative dopants or dopant sources; also it is unclear as to what “x” is stand for.
The claimed limitation of “the performing of the gate electrodes”, as recited in claim 10, is unclear as to which step is “the performing of the gate electrodes” applicant refers.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3, 6, 7, 9 and 10, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (2021/0091204) in view of Lu et al. (2023/0154998).
As for claims 1, 3, 6 and 7, Rabkin et al. show in Figs. 1-4A, 5A-5H, 6, 7A, 8, 9A-9C, 10 and related text a method for fabricating a semiconductor memory device, the method comprising:
forming a channel hole 49 inside a temporary stack structure including sacrificial layers 42 and insulating layers 32 alternately stacked on each other (Fig. 4A);
forming a ferroelectric layer 54 inside the channel hole (Fig. 5C);
forming a vertical structure 56/601/602 by sequentially forming a vertical channel layer 601 and a vertical semiconductor layer 602 on the ferroelectric layer (Figs. 5G-5H); and
removing the sacrificial layers from the temporary stack structure (Fig. 8) and forming gate electrodes (Figs. 9A-9C).
Rabkin et al. do not disclose forming a stress control layer on an inner sidewall of the ferroelectric layer; performing a cooling process on an inner sidewall of the stress control layer; removing at least a portion of the stress control layer after the cooling process is performed (claim 1); the stress control layer includes: a material causing stress together with the ferroelectric layer during the cooling process (claim 3); a thickness of the stress control layer, which remains between the ferroelectric layer and the vertical channel layer, is less than a thickness of the ferroelectric layer after removing the at least the portion of the stress control layer (claim 6); and the thickness of the stress control layer, which remains between the ferroelectric layer and the vertical channel layer, is in a range of 5 nanometer to 50 nanometers (claim 7).
Lu et al. teach in Figs. 2A-2D and related text:
As for claim 1, forming a stress control layer 40/a-Si on the ferroelectric layer;
performing a cooling process on the stress control layer;
removing at least a portion of the stress control layer after the cooling process is performed ([0050]).
As for claim 3, the stress control layer includes: a material causing stress together with the ferroelectric layer during the cooling process ([0046]).
As for claim 6, a thickness of the stress control layer, which remains on the ferroelectric layer, is less than a thickness of the ferroelectric layer after removing the at least the portion of the stress control layer (Fig. 2C).
As for claim 7, the thickness of the stress control layer, which remains on the ferroelectric layer, is in a range of 5 nanometer to 50 nanometers ([0045]).
Rabkin et al. and Lu et al. are analogous art because they are directed to a method of forming a ferroelectric structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lu et al. with the specified feature(s) of Rabkin et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form a stress control layer on the ferroelectric layer; perform a cooling process on the stress control layer; and remove at least a portion of the stress control layer after the cooling process being performed, the stress control layer including a material causing stress together with the ferroelectric layer during the cooling process; the thickness of the stress control layer, which remains on the ferroelectric layer and the vertical channel layer, being in a range of 5 nanometer to 50 nanometers, as taught by Lu et al., in Rabkin et al.'s device, in order to obtain a desired type crystalline oriented ferroelectric structure, improve ferroelectric properties and optimize the performance of the device.
Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Therefore, the combined device shows:
As for claim 1, forming a stress control layer on an inner sidewall of the ferroelectric layer; and
performing a cooling process on an inner sidewall of the stress control layer.
As for claim 6, a thickness of the stress control layer, which remains between the ferroelectric layer and the vertical channel layer, is less than a thickness of the ferroelectric layer after removing the at least the portion of the stress control layer.
As for claim 7, the thickness of the stress control layer, which remains between the ferroelectric layer and the vertical channel layer, is in a range of 5 nanometer to 50 nanometers
As for claim 2, the combined device shows the ferroelectric layer is doped with at least one material of HfOx, Al, Zr, or Si to have an orthorhombic crystal structure (Rabkin: [0068]; Lu: [0048]-[0049]).
As for claim 9, the combined device shows the forming of the vertical structure by sequentially forming the vertical channel layer and the vertical semiconductor layer on the ferroelectric layer includes:
sequentially forming a gate insulating layer 56, the vertical channel layer, and the vertical semiconductor layer on the ferroelectric layer (Rabkin: Figs. 5G-5H).
As for claim 10, the combined device shows the forming the gate electrodes includes forming the gate electrodes after forming the vertical structure (Rabkin: Figs. 9A-9C).
Claim(s) 4 and 5, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Rabkin et al. (2021/0091204) and Lu et al. (2023/0154998) in view of.
As for claims 4 and 5, Rabkin et al. and Lu et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the performing of the cooling process includes: rapidly cooling the stress control layer and the ferroelectric layer by injecting cooling water into the inner sidewall of the stress control layer (claim 4); and the performing of the cooling process includes: performing the cooling process by directly providing the cooling water into an entire portion of the inner sidewall of the stress control layer (claim 5).
Garland et al. teach in related text:
As for claim 4, the performing of the cooling process includes: rapidly cooling by injecting cooling water into an entire portion of the structure ([0061]).
As for claim 5, the performing of the cooling process includes: performing the cooling process by directly providing the cooling water on the structure ([0061]).
Rabkin et al., Lu et al. and Garland et al. are analogous art because they are directed to a method of forming a ferroelectric structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Garland et al. with the specified feature(s) of Rabkin et al. and Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to rapidly cool by injecting cooling water into the structure; and directly provide the cooling water on the structure, as taught by Garland et al., in Rabkin et al. and Lu et al.’s device, in order to improve ferroelectric properties.
Therefor the combined device shows:
As for claim 4, the performing of the cooling process includes: rapidly cooling the stress control layer and the ferroelectric layer by injecting cooling water into the inner sidewall of the stress control layer.
As for claim 5, the performing of the cooling process includes: performing the cooling process by directly providing the cooling water into an entire portion of the inner sidewall of the stress control layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811