DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because one of Fig. 5 has the misspelled label such as -VE STACK and +VE STACK instead of -VE SLACK and +VE SLACK. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered, and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter Chandrasekar in view of Smita Bakshi et. al. (US 20150012898 A1) hereinafter Bakshi.
Regarding claim 1
Chandrasekar discloses sections a-c and e of claim 1
At least one non-transitory computer readable medium comprising computer readable instructions to cause at least one processor circuit to at least
(Chandrasekar, col. 9, lines 47-55 “Those skilled in the art will appreciate that various alternative computing arrangements, including one or more processors and a memory arrangement configured with program code, would be suitable for hosting the processes and data structures disclosed herein. In addition, the processes may be provided via a variety of computer-readable storage media or delivery channels such as magnetic or optical disks or tapes, electronic storage devices, or as application services over a network.”)
partition a circuit design into a plurality of contexts based on output data from a first execution iteration of an electronic design automation (EDA) tool, the output data including a netlist representative of the circuit design, the output data based on a first set of configuration parameters applied globally to the circuit design by the EDA tool to synthesize the circuit design
(Chandrasekar, col. 1, lines 56-59 “A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instructions that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
(Chandrasekar, col 3, lines 60-61 “At block 124, the EDA tool generates a netlist from the mapped circuit design.”)
(Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 1, lines 49-54 “According to other disclosed methods, during the first synthesis, the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions.”)
(Chandrasekar, col 3, lines 45-48 “At block 220, the EDA tool generates a netlist, places and routes the netlist, generates configuration data, and implements a circuit as described for blocks 124, 126, and 128 of FIG. 1.”)
identify an outlier context in the plurality of contexts based on the output data
(Chandrasekar, col. 1, lines 37-43 “According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions.”)
and cause the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of the second set of configuration parameters to the outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers.
(Chandrasekar, col. 1, lines 43-45 “The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions”)
(Chandrasekar, col. 1, lines 49-54 “According to other disclosed methods, during the first synthesis, the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions.”)
(Chandrasekar, col. 1, lines 59-66 “The instructions further cause the computer processor to determine after a modification of the circuit design, changed partitions and unchanged partitions of the circuit design. The computer processor in executing the instructions determines dependent partitions of the changed partitions and re-synthesizes the changed partitions and the dependent partitions into respective re-synthesized partitions.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
(Chandrasekar, col. 2, lines 21-22 “FIG. 4 shows a partition dependency graph from an initial synthesis of a circuit design.”)
(Chandrasekar, col. 2, lines 23-24 “FIG. 5 shows the incremental partition dependency graph generated from incremental synthesis.”)
(Chandrasekar, col 3, lines 45-48 “At block 220, the EDA tool generates a netlist, places and routes the netlist, generates configuration data, and implements a circuit as described for blocks 124, 126, and 128 of FIG. 1.”)
Chandrasekar does not explicitly teach
modify at least one configuration parameter of the first set of configuration parameters based on the outlier context to generate a second set of configuration parameters to be applied locally to the outlier context to synthesize the circuit design
However Bakshi discloses
modify at least one configuration parameter of the first set of configuration parameters based on the outlier context to generate a second set of configuration parameters to be applied locally to the outlier context to synthesize the circuit design
(Bakshi, p. 1, [0016] “FIG. 7 is a flowchart illustrating a process to budget top-level constraints according to one embodiment of the invention.”)
(Bakshi, p. 3, [0036] “The synthesizer 220 receives the top-level constraints and synthesizes the partitions in a hierarchical manner, from the bottom-level partitions to the top-level partition. The synthesizer 220 divide or budget the top-level constraints into lower partition constraints. … The synthesizer 220 performs a bottom-up synthesis, replacing a parent partition with its lower level synthesized netlists. As the synthesizer 220 progresses from the bottom up, the optimizer 227 optimizes the partition based on the partition constraints. The optimizer 227 also optimizes the top-level partition to satisfy the top-level constraints.”)
(Bakshi, p. 3, [0037] “Typically, a design process may go through several design cycles, passes, or iterations. At each pass, the user may modify the circuit description, the constraints, or the interface model of a partition. When the design is modified or changed, the synthesizer 220 only re-synthesizes those partitions that contain a change.”)
(Bakshi, p. 3, [0046] “Next, the process 400 synthesizes the lower partitions hierarchically from the bottom-level partition up to the top-level partition to create lower partition netlists based on the top-level constraints (Block 420). The details of Block 420 will be described in FIG. 6. Then, the process 400 optimizes the top-level netlist corresponding to the top-level partition to satisfy the top-level constraints and every compile point (CP) at lower level partitions to satisfy the corresponding partition constraints (Block 430) and is then terminated.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and of Bakshi to yield predictable result of optimized design at the local level as well as at the global level.
Regarding claim 2
Chandrasekar and Bakshi teach all features of claim 1 as disclosed above and Chandrasekar further discloses
The at least one non-transitory computer readable medium of claim 1, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design.
(Chandrasekar, col. 3, lines 1-5 “The EDA tool partitions the circuit design at block 112. Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114.”)
(Chandrasekar, col. 2, lines 25-26 “FIG. 6 shows a module instance hierarchy of an exemplary circuit design.”)
(Chandrasekar, col. 3, lines 48-52 “The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information,
D
M
is shown as block 122. The top skeleton is a data structure, e.g., a file that specifies the hierarchy of module instances and partitions forming circuit design
D
E
110.”)
Regarding claim 3
Chandrasekar and Bakshi teach all features of claim 1 as disclosed above and Chandrasekar further discloses
The at least one non-transitory computer readable medium of claim 1, wherein the outlier context is identified based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data.
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Regarding claim 7
Chandrasekar and Bakshi teach all features of claim 1 as disclosed above and Chandrasekar further discloses
The at least one non-transitory computer readable medium of claim 1,
wherein the second set of parameters is to specify a transition region between the outlier context and the other ones of the contexts, the EDA tool is to apply the second set of parameters to the outlier context, the EDA tool is to apply the first set of parameters outside the transition region, and the EDA tool is to apply a third set of parameters in the transition region, the third set of parameters based on the first set of parameters and the second set of parameters.
(Chandrasekar, col. 3, lines 5-15 “FIG. 2 shows a flowchart of a process for incrementally re-synthesizing portions of a circuit design through use of a partition dependency graph to determine partitions that should be re-synthesized because of optimizations to changed partitions; A changed circuit design D′ is input to an EDA tool as shown by block 200, and the EDA tool elaborates the changed circuit design at block 202, producing elaborated, changed circuit design
D
E
'
, which is shown as block 204. At block 206, the EDA tool validates constraints of the modified circuit design.”)
(Chandrasekar, col. 3, lines 16-25 “The EDA tool prepares for incremental synthesis at block 208. The EDA tool inputs the elaborated circuit design
D
E
and modified, elaborated circuit design
D
E
'
, to determine which modules have changed and require re-synthesis. The partition dependency graph G is used to determine additional partitions (“dependent partitions”) to re-synthesize due to optimizations that cover pins in changed partitions and extend to pins in unchanged partitions. The top skeleton
D
M
122 and saved unchanged partitions are used in combining re-synthesized partitions with unchanged partitions.”)
(Chandrasekar, col. 3, lines 26-34 “At block 210, the EDA tool selects the changed partitions and dependent partitions and initiates optimization of the selected partitions at block 212. In optimizing the selected partitions, the EDA tool generates a modified partition dependency graph G′, which is shown as block 214, as optimization dependencies may change due to the changes to the design. The EDA tool performs technology mapping of the optimized partitions and generates an incremental netlist at block 216.”)
Regarding claim 8
Chandrasekar and Bakshi teach all features of claim 1 as disclosed above and Chandrasekar further discloses
The at least one non-transitory computer readable medium of claim 1, wherein the circuit design corresponds to a system on a chip.
(Chandrasekar, col. 8, lines 39-44 “FIG. 11 shows a programmable integrated circuit (IC) 800 on which a circuit can be implemented according to the incremental synthesis approaches described herein. The programmable IC may also be referred to as a System On Chip (SOC) that includes field programmable gate array logic (FPGA) along with other programmable resources.”)
Regarding claim 17
Chandrasekar discloses sections a-f and h of claim 17
A method to operate an electronic design automation (EDA) tool, the method comprising
(Chandrasekar, col 7, lines 31-34 “The disclosed methods and system reduce the time required to perform incremental synthesis and thereby improve performance of the computer system hosting the EDA tool.”)
partitioning, by executing an instruction with at least one processor circuit
(Chandrasekar, col 1, lines 55-59 “A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instructions that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis.”)
a circuit design into a plurality of contexts based on output data from a first execution iteration of the EDA tool
(Chandrasekar, col. 1, lines 56-59 “A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instructions that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
the output data including a netlist representative of the circuit design
(Chandrasekar, col 3, lines 60-61 “At block 124, the EDA tool generates a netlist from the mapped circuit design.”)
the output data based on a first set of configuration parameters applied globally to the circuit design by the EDA tool to synthesize the circuit design
(Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col 1., lines 37-48 “ According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions. The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions, and the computer processor then combines the respective re-synthesized partitions and the unchanged partitions into a complete synthesized circuit design in a memory.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
identifying, by executing an instruction with one or more of the at least one processor circuit, at least one outlier context in the plurality of contexts based on the output data
(Chandrasekar, col. 1, lines 37-43 “According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions.”)
and causing the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of the second set of configuration parameters to the at least one outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers.
(Chandrasekar, col. 1, lines 43-45 “The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions”)
(Chandrasekar, col. 1, lines 49-54 “According to other disclosed methods, during the first synthesis, the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions.”)
(Chandrasekar, col. 1, lines 59-66 “The instructions further cause the computer processor to determine after a modification of the circuit design, changed partitions and unchanged partitions of the circuit design. The computer processor in executing the instructions determines dependent partitions of the changed partitions and re-synthesizes the changed partitions and the dependent partitions into respective re-synthesized partitions.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
(Chandrasekar, col. 2, lines 21-22 “FIG. 4 shows a partition dependency graph from an initial synthesis of a circuit design.”)
(Chandrasekar, col. 2, lines 23-24 “FIG. 5 shows the incremental partition dependency graph generated from incremental synthesis.”)
Chandrasekar does not explicitly teach
modifying, by executing an instruction with one or more of the at least processor circuit, at least one configuration parameter of the first set of configuration parameters based on the at least one outlier context to generate a second set of configuration parameters to be applied locally to the at least one outlier context to synthesize the circuit design
However Bakshi discloses
modifying, by executing an instruction with one or more of the at least processor circuit, at least one configuration parameter of the first set of configuration parameters based on the at least one outlier context to generate a second set of configuration parameters to be applied locally to the at least one outlier context to synthesize the circuit design
(Bakshi, p. 1, [0016] “FIG. 7 is a flowchart illustrating a process to budget top-level constraints according to one embodiment of the invention.”)
(Bakshi, p. 3, [0036] “The synthesizer 220 receives the top-level constraints and synthesizes the partitions in a hierarchical manner, from the bottom-level partitions to the top-level partition. The synthesizer 220 divide or budget the top-level constraints into lower partition constraints. … The synthesizer 220 performs a bottom-up synthesis, replacing a parent partition with its lower level synthesized netlists. As the synthesizer 220 progresses from the bottom up, the optimizer 227 optimizes the partition based on the partition constraints. The optimizer 227 also optimizes the top-level partition to satisfy the top-level constraints.”)
(Bakshi, p. 3, [0037] “Typically, a design process may go through several design cycles, passes, or iterations. At each pass, the user may modify the circuit description, the constraints, or the interface model of a partition. When the design is modified or changed, the synthesizer 220 only re-synthesizes those partitions that contain a change.”)
(Bakshi, p. 3, [0043] “The lower partitions may be synthesized separately and independently. This aspect makes effective use of multiprocessing to speed up the synthesis process. The lower partitions may be allocated and assigned to a group of processors. If there are more partitions than the number of processors, the partitions may be grouped in groups such that the synthesis run time of the longest group is minimized.”)
(Bakshi, p. 3, [0046] “Next, the process 400 synthesizes the lower partitions hierarchically from the bottom-level partition up to the top-level partition to create lower partition netlists based on the top-level constraints (Block 420). The details of Block 420 will be described in FIG. 6. Then, the process 400 optimizes the top-level netlist corresponding to the top-level partition to satisfy the top-level constraints and every compile point (CP) at lower level partitions to satisfy the corresponding partition constraints (Block 430) and is then terminated.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and of Bakshi to yield predictable result of optimized design at the local level as well as at the global level.
Regarding claim 18
Chandrasekar and Bakshi teach all features if claim 17 as disclosed above and Chandrasekar further discloses
The method of claim 17, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design.
(Chandrasekar, col. 3, lines 1-5 “The EDA tool partitions the circuit design at block 112. Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114.”)
(Chandrasekar, col. 2, lines 25-26 “FIG. 6 shows a module instance hierarchy of an exemplary circuit design.”)
(Chandrasekar, col. 3, lines 48-52 “The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information,
D
M
is shown as block 122. The top skeleton is a data structure, e.g., a file that specifies the hierarchy of module instances and partitions forming circuit design
D
E
110.”)
Regarding claim 19
Chandrasekar and Bakshi teach all features if claim 17 as disclosed above and Chandrasekar further discloses
The method of claim 17, wherein the identifying of the at least one outlier context is based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data.
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Claims 4 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekar and Bakshi as applied to claim 1 and 17 above, and further in view of Jeanne P. Bickford et. al. (US 9767240 B2) hereinafter Bickford1.
Regarding claim 4
Chandrasekar and Bakshi teach all features if claim 1 as disclosed above and Chandrasekar further discloses
The at least one non-transitory computer readable medium of claim 1, wherein the instructions are to cause one or more of the at least one processor circuit to:
determine, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Chandrasekar and Bakshi do not teach
normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
and compare the normalized power characteristics to a threshold to identify the outlier context.
However Bickford1 discloses
normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
(Bickford1, col. 7, line 7-15 “This per section total power consumption threshold (
I
t
) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in μW/
m
m
2
(e.g., 3 μW/
m
m
2
, 4 μW/
m
m
2
, etc.). For example, if the sections are 2
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in terms of μW/2
m
m
2
(e.g., 6 μW/2
m
m
2
, 8 μW/2
m
m
2
, etc.).”)
(Bickford1, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
and compare the normalized power characteristics to a threshold to identify the outlier context.
(Bickford1, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Chandrasekar and Bakshi and of Bickford1 for the purpose of optimizing area, time, and power consumption both locally and globally and to yield predictable result of highly optimized circuit design.
Regarding claim 20
Chandrasekar and Bakshi teach all features if claim 17 as disclosed above and Chandrasekar further discloses
The method of claim 17, wherein the identifying of the at least one outlier context includes
determining, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Chandrasekar and Bakshi do not teach
normalizing the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
and comparing the normalized power characteristics to one or more thresholds to identify the at least one outlier context.
However Bickford1 discloses
normalizing the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
(Bickford, col. 7, line 7-15 “This per section total power consumption threshold (
I
t
) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in μW/
m
m
2
(e.g., 3 μW/
m
m
2
, 4 μW/
m
m
2
, etc.). For example, if the sections are 2
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in terms of μW/2
m
m
2
(e.g., 6 μW/2
m
m
2
, 8 μW/2
m
m
2
, etc.).”)
(Bickford, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
and comparing the normalized power characteristics to one or more thresholds to identify the at least one outlier context.
(Bickford, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Chandrasekar and Bakshi and of Bickford1 for the purpose of optimizing area, time, and power consumption both locally and globally and to yield predictable result of highly optimized circuit design.
Claims 5-6 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekar and Bakshi as applied to claim 1 and 17 respectively above, and further in view of Jeanne P. Bickford et. al. (US 20170212977 A1), hereinafter Bickford2.
Regarding claim 5
Chandrasekar and Bakshi teach all features of claim 1 as disclosed above.
Chandrasekar and Bakshi do not teach
The at least one non-transitory computer readable medium of claim 1,
wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value.
However Bickford2 discloses
wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value.
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 4, 0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and Bakshi and of Bickford2 to choose the slack threshold appropriate for the respective partition/design block to yield predictable result of highly optimized circuit design.
Regarding claim 6
Chandrasekar, Bakshi, and Bickford2 teach all features of claim 5 as disclosed above.
Chandrasekar and Bakshi do not teach
The at least one non-transitory computer readable medium of claim 5, wherein the instructions are to cause one or more of the at least one processor circuit to:
determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram.
However Bickford2 discloses
determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram.
(Bickford2, p. 4, [0030] “… This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary.”)
(Bickford2, p. 4, [0031] “For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205a-j associated with each of the different instances 201a-j of the design block 210. These ATs 205a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201g and 201h of the design block 210) to a latest AT of 10 ps (e.g., for instances 201d and 201f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201g and 201h of the design block 210) and 0 ps (e.g., for the instances 201d and 201f of the design block 210).”)
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
It must be noted that histogram is only a visual representation of data.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and Bakshi and of Bickford2 to choose the slack threshold appropriate for the respective partition/design block to yield predictable result of highly optimized circuit design.
Regarding claim 25
Chandrasekar and Bakshi teach all features of claim 17 as disclosed above.
Chandrasekar and Bakshi do not teach
The method of claim 17, wherein the first set of parameters includes a first slack threshold value, the second set of parameters includes a second slack threshold value, and including determining the second slack threshold value based on a histogram of slack values included in the output data for the plurality of contexts.
However Bickford2 discloses
The method of claim 17, wherein the first set of parameters includes a first slack threshold value, the second set of parameters includes a second slack threshold value, and including determining the second slack threshold value based on a histogram of slack values included in the output data for the plurality of contexts.
(Bickford2, p. 4, [0030] “… This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary.”)
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 4, [0031] “For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205a-j associated with each of the different instances 201a-j of the design block 210. These ATs 205a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201g and 201h of the design block 210) to a latest AT of 10 ps (e.g., for instances 201d and 201f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201g and 201h of the design block 210) and 0 ps (e.g., for the instances 201d and 201f of the design block 210).”)
(Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and Bakshi and of Bickford2 to choose the slack threshold appropriate for the respective partition/design block to yield predictable result of highly optimized circuit design.
Claims 9-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter Chandrasekar in view of Jeanne P. Bickford et. al. (US 20170212977 A1) hereinafter Bickford2.
Regarding claim 9
Chandrasekar discloses
An apparatus to operate an electronic design automation (EDA) tool, the apparatus comprising
(Chandrasekar, col. 7, lines 45-47 “FIG. 10 is a block diagram illustrating an exemplary data processing system (system) 700. System 700 is an example of an EDA system.”)
at least one memory
(Chandrasekar, col. 7, lines 47-49 “As pictured, system 700 includes at least one processor circuit (or “processor”), e.g., a central processing unit (CPU) 705 coupled to memory”)
machine readable instructions
(Chandrasekar, col. 7, lines 51-52 “System 700 stores program code and circuit design 102 within memory and storage arrangement 720.”)
and at least one processor circuit to be programmed based on the machine readable instructions to
(Chandrasekar, col. 7, lines 47-54 “As pictured, system 700 includes at least one processor circuit (or “processor”), e.g., a central processing unit (CPU) 705 coupled to memory and storage arrangement 720 through a system bus 715 or other suitable circuitry. System 700 stores program code and circuit design 102 within memory and storage arrangement 720. Processor 705 executes the program code accessed from the memory and storage arrangement 720 via system bus 715.”)
partition a circuit design into a plurality of contexts based on output data from a first execution iteration of the EDA tool, the output data including a netlist representative of the circuit design, the output data based on a first set of configuration parameters applied to the circuit design by the EDA tool
(Chandrasekar, col. 1, lines 56-59 “A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instructions that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis.”)
(Chandrasekar, col. 2, lines 19-20 “FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis;”)
(Chandrasekar, col 3, lines 60-61 “At block 124, the EDA tool generates a netlist from the mapped circuit design.”)
(Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 1, lines 49-54 “According to other disclosed methods, during the first synthesis, the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions.”)
Chandrasekar does not explicitly teach
the first set of configuration parameters including a first value for a slack threshold
determine a second value for the slack threshold, the second value based on a histogram of slack values included in the output data for the plurality of contexts
and cause the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of a second set of configuration parameters to an outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers, the second set of configuration parameters including the second value for the slack threshold.
However Bickford2 discloses
the first set of configuration parameters including a first value for a slack threshold
(Bickford2, p. 4, [0030] “… This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary.”)
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
determine a second value for the slack threshold, the second value based on a histogram of slack values included in the output data for the plurality of contexts
(Bickford2, p. 4, [0031] “For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205a-j associated with each of the different instances 201a-j of the design block 210. These ATs 205a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201g and 201h of the design block 210) to a latest AT of 10 ps (e.g., for instances 201d and 201f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201g and 201h of the design block 210) and 0 ps (e.g., for the instances 201d and 201f of the design block 210).”)
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 6, [0045] “… This timing analysis can be a static timing analysis (STA), such as a statistical static timing analysis (SSTA), which is performed using both the previously generated timing abstract for the design block 210 and other timing information associated with the top-level logic 250 in order to close timing on the initial IC design given the layout. This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary. For example, see the detailed discussion of FIG. 5 above, which shows the layout of the initial design of the IC 200 annotated with the ATs 205a-j).”)
(Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
and cause the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of a second set of configuration parameters to an outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers, the second set of configuration parameters including the second value for the slack threshold.
(Bickford2, p. 6, [0046] “The system 800 disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the processor 830 (or, if applicable, the design editor 830c) can compare (i.e., can be adapted to compare, can be configured to compare and/or can execute a program of instructions 820 to compare) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time and can further modifying (e.g., can be adapted to modify, can be configured to modify, and/or can execute a program of instructions 820 to modify) any one or more of the modifiable periphery section(s) 212 of each specific instance of the design block 210 having an AT that is equal to or less than the preselected threshold arrival time. This modification process can specifically be performed so to reduce power consumption by the specific instance of the design block and/or to reduce an area of the specific instance of the design block.”)
(Bickford2, p. 7 [0050] “… If change(s) have been made to an internal section of the design block 210, thereby requiring a change in the timing abstract, then the processor 830 (or, if applicable, the timing analyzer 830b and the design editor 830c) will repeat the above-described timing analysis and design modification processes. However, if the modification to the design block 210 only contains change(s) to the modifiable periphery section(s) 212, then the timing analysis previously performed by the processor 830 (or timing analyzer 830b) does not need to be repeated. Instead the processor 830 (or, if applicable, the design editor) can simply reassess (i.e., can be adapted to reassess, can be configured to reassess, and/or can execute a program of instructions 820 to reassess) any modifications previously made at to the modifiable periphery section(s) 212 of any instance of the design block 210 in the initial IC design layout 814 in light of the ECO.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Chandrasekar and of Bickford2 to yield predictable result of highly optimized circuit design more specifically with respect to power consumption and area.
Regarding claim 10
Chandrasekar and of Bickford2 teaches all features of claim 9 as disclosed above and Chandrasekar further discloses
The apparatus of claim 9, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design.
(Chandrasekar, col. 3, lines 1-5 “The EDA tool partitions the circuit design at block 112. Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114.”)
(Chandrasekar, col. 2, lines 25-26 “FIG. 6 shows a module instance hierarchy of an exemplary circuit design.”)
(Chandrasekar, col. 3, lines 48-52 “The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information,
D
M
is shown as block 122. The top skeleton is a data structure, e.g., a file that specifies the hierarchy of module instances and partitions forming circuit design
D
E
110.”)
Regarding claim 11
Chandrasekar and of Bickford2 teaches all features of claim 9 as disclosed above and Chandrasekar further discloses
The apparatus of claim 9, wherein one or more of the at least one processor circuit is to identify the outlier context based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data.
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Regarding claim 14
Chandrasekar and Bickford2 teach all features of claim 9 as disclosed above.
Chandrasekar does not teach
The apparatus of claim 9, wherein one or more of the at least one processor circuit is to:
determine the histogram of slack values for the plurality of contexts based on the output data.
However, Bickford2 discloses
determine the histogram of slack values for the plurality of contexts based on the output data.
(Bickford2, p. 4, [0030] “… This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary.”)
(Bickford2, p. 4, [0031] “For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205a-j associated with each of the different instances 201a-j of the design block 210. These ATs 205a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201g and 201h of the design block 210) to a latest AT of 10 ps (e.g., for instances 201d and 201f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201g and 201h of the design block 210) and 0 ps (e.g., for the instances 201d and 201f of the design block 210).”)
(Bickford2, p. 4, [0032] “The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time (110) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time (112). Specifically, at process 112, the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block.”)
(Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Chandrasekar and of Bickford2 to yield predictable result of highly optimized circuit design more specifically with respect to power consumption and area.
Regarding claim 15
Chandrasekar and Bickford2 teach all features of claim 9 as disclosed above and Chandrasekar further discloses
The apparatus of claim 9, wherein the second set of parameters is to specify a transition region between the outlier context and the other ones of the contexts, the EDA tool is to apply the second set of parameters to the outlier context, the EDA tool is to apply the first set of parameters outside the transition region, and the EDA tool is to apply a third set of parameters in the transition region, the third set of parameters based on the first set of parameters and the second set of parameters.
(Chandrasekar, col. 3, lines 5-15 “FIG. 2 shows a flowchart of a process for incrementally re-synthesizing portions of a circuit design through use of a partition dependency graph to determine partitions that should be re-synthesized because of optimizations to changed partitions; A changed circuit design D′ is input to an EDA tool as shown by block 200, and the EDA tool elaborates the changed circuit design at block 202, producing elaborated, changed circuit design
D
E
'
, which is shown as block 204. At block 206, the EDA tool validates constraints of the modified circuit design.”)
(Chandrasekar, col. 3, lines 16-25 “The EDA tool prepares for incremental synthesis at block 208. The EDA tool inputs the elaborated circuit design
D
E
and modified, elaborated circuit design
D
E
'
, to determine which modules have changed and require re-synthesis. The partition dependency graph G is used to determine additional partitions (“dependent partitions”) to re-synthesize due to optimizations that cover pins in changed partitions and extend to pins in unchanged partitions. The top skeleton
D
M
122 and saved unchanged partitions are used in combining re-synthesized partitions with unchanged partitions.”)
(Chandrasekar, col. 3, lines 26-34 “At block 210, the EDA tool selects the changed partitions and dependent partitions and initiates optimization of the selected partitions at block 212. In optimizing the selected partitions, the EDA tool generates a modified partition dependency graph G′, which is shown as block 214, as optimization dependencies may change due to the changes to the design. The EDA tool performs technology mapping of the optimized partitions and generates an incremental netlist at block 216.”)
Regarding claim 16
Chandrasekar and Bickford2 teach all features of claim 9 as disclosed above and Chandrasekar further discloses
The apparatus of claim 9, wherein the circuit design corresponds to a system on a chip.
(Chandrasekar, col. 8, lines 39-44 “FIG. 11 shows a programmable integrated circuit (IC) 800 on which a circuit can be implemented according to the incremental synthesis approaches described herein. The programmable IC may also be referred to as a System On Chip (SOC) that includes field programmable gate array logic (FPGA) along with other programmable resources.”)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekar and Bickford2 as applied to claim 9 above, and further in view of Jeanne P. Bickford et. al. (US 9767240 B2), hereinafter Bickford1.
Chandrasekar and of Bickford2 teaches all features of claim 9 as disclosed above.
Chandrasekar further discloses
The apparatus of claim 9, wherein the instructions are to cause one or more of the at least one processor circuit to:
determine, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts
(Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106, the EDA tool validates constraints of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design
D
E
as shown by block 110.”)
(Chandrasekar, col. 3, lines 10-11 “The optimizations performed by the EDA tool at block 114 can include area and timing optimizations.”)
Chandrasekar and of Bickford2 do not teach
normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
and compare the normalized power characteristics to a threshold to identify the outlier context.
However Bickford1 discloses
normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts
(Bickford1, col. 7, line 7-15 “This per section total power consumption threshold (
I
t
) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in μW/
m
m
2
(e.g., 3 μW/
m
m
2
, 4 μW/
m
m
2
, etc.). For example, if the sections are 2
m
m
2
in size, the per section total power consumption threshold (
I
t
) can be define in terms of μW/2
m
m
2
(e.g., 6 μW/2
m
m
2
, 8 μW/2
m
m
2
, etc.).”)
(Bickford1, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
and compare the normalized power characteristics to a threshold to identify the outlier context.
(Bickford1, col. 4, lines 44-49 “That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Chandrasekar and Bickford2 and of Bickford1 to yield predictable result of highly optimized circuit design more specifically with respect to power consumption, area, and time.
Response to Arguments
Applicant's arguments filed 07/13/2026 have been fully considered but they are not persuasive.
Regarding Argument 1
Independent Claim 1
Independent claim 1 sets forth instructions to cause at least one processor circuit to "modify at least one configuration parameter of the first set of configuration parameters based on the outlier context to generate a second set of configuration parameters to be applied locally to the outlier context to synthesize the circuit design," and "cause the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of the second set of configuration parameters to the outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers." Chandrasekar, individually or in combination with the other references relied upon by the Office Action, does not teach or suggest such instructions.
Chandrasekar describes "a process for incrementally re-synthesizing portions of a circuit design." (Chandrasekar, 4:5-6.) Unlike claim 1, Chandrasekar's process does not synthesize bott outlier contexts and contexts that are not identified as outliers in successive execution iterations. Rather, Chandrasekar's process re-synthesizes portions of a modified circuit design, with the re-synthesized portions corresponding to changed partitions relative to the original circuit design. (Id. at 4:5-44.) Notably, Chandrasekar makes clear that only the changed partitions are re-synthesized, whereas unchanged partitions "are reused but not re-synthesized." (Id. at 6:26-34, emphasis added.) As such, Chandrasekar does not teach or suggest causing an EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of the second set of configuration parameters locally to the outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers, as set forth in claim 1. Furthermore, although Chandrasekar describes a modified circuit design itself, Chandrasekar does not teach or suggest modifying at least one configuration parameter of a first set of configuration parameters based on an outlier context to generate a second set of configuration parameters to be applied locally to the outlier context to synthesize the circuit design, as also set forth in claim 1.
Because Chandrasekar is missing several features of claim 1, Chandrasekar fails to establish a prima facie case of anticipation or obviousness against the claim. The other references relied upon by the Office Action, individually or in combination, do not provide the foregoing features of claim 1 that are missing from Chandrasekar.
Response: (Chandrasekar, col. 1, lines 37-48 “According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions. The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions, and the computer processor then combines the respective re-synthesized partitions and the unchanged partitions into a complete synthesized circuit design in a memory.”)
In essence,
The changed partitions can be consider as the outliers, as the initial optimization identified them and made changes.
Resynthesis is done not simply on the changed partition alone, as incorrectly stated in the above argument, but it included the dependent partitions which may include some of the unchanged partitions.
(Chandrasekar, col 3, lines 45-48 “At block 220, the EDA tool generates a netlist, places and routes the netlist, generates configuration data, and implements a circuit as described for blocks 124, 126, and 128 of FIG. 1.”). Thus, the tool is generating the new configuration data to be applied during the incremental resynthesis.
Because of the amendment to claim 1, new reference has been introduced. See the rejection above.
Considering all of the above, Chandrasekar, Bakshi, Bickford1, and Bickford2 teach all features of claim 1 and its dependent claims.
Regarding Argument 2
Independent Claim 9
Independent claim 9 sets forth "the first set of configuration parameters including a first value for a slack threshold," and at least one processor circuit to "determine a second value for the slack threshold, the second value based on a histogram of slack values included in the output data for the plurality of contexts." Chandrasekar, individually or in combination with the other references relied upon by the Office Action, does not teach or suggest such circuitry.
In its rejection of prior claim 14, the Office Action acknowledged that Chandrasekar does not "determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram." (See the Office Action, p 29.) It follows, therefore, that Chandrasekar does not teach or suggest a first set of configuration parameters including a first value for a slack threshold, and determining a second value for the slack threshold, the second value based on a histogram of slack values included in output data for a plurality of contexts, as set forth in claim 9.
In view of the acknowledged deficiencies of Chandrasekar, the Office Action turned to Bickford2. Although Bickford2 illustrates and describes a design layout "annotated with the ATs" (where ATs refers to arrival times), nowhere does Bickford2 teach or suggest a histogram of such arrival times, much less a histogram of slack values, as set forth in claim 9. (See Bickford2, [0031].) Furthermore, nothing in Bickford2 teaches or suggests determining a second value for a slack threshold based on a histogram of slack values included in output data for a plurality of contexts, as set forth in claim 9.
Bickford is also missing at least the foregoing features of claim 9 that are missing from Chandrasekar and Bickford2. Because Chandrasekar, Bickford and Bickford2 are each missing the same features of claim 9, their alleged combination is likewise missing at least those same features of the claim. In view of those missing features, the alleged Chandrasekar, individually or in combination with Bickford and/or Bickford2, fails to establish a prima facie case of anticipation or obviousness against claim 9. Therefore, claim 9 is allowable, and withdrawal of the rejections of independent claim 9 and all claims depending therefrom is respectfully requested.
Response:
Chandrasekar does not explicitly teach anything related to slack time and slack threshold.
With respect to “nowhere does Bickford2 teach or suggest a histogram of such arrival times, much less a histogram of slack values”
Histogram is only a visual representation of data
Bickford2 teaches not only arrival times but also of slack times (Bickford2, p. 4, [0030] “… This STA can specifically be used to determine (i.e., to predict) the arrival times (ATs) of the data signals at the primary inputs of the design blocks and the results can be compared against established timing requirements (e.g., required arrival times (RATs)) to see if the integrated circuit, as initially designed, will function properly with a sufficiently high probability. As mentioned above with regard to the layout of the exemplary layout of the design of the IC 200 shown in FIG. 2, due to the different locations of the different instances 201a-j of the design block 210, the data signal pathways 202a-j between the top-level logic 250 and the primary inputs 211 may vary (e.g., may be different lengths, may incorporate different numbers or sizes of buffers, etc.). As a result, the ATs at the primary inputs 211 of the different instances 201a-j of the design block are different and, thereby the slack times will vary.”)
With respect to “nothing in Bickford2 teaches or suggests determining a second value for a slack threshold based on a histogram of slack values included in output data for a plurality of contexts”
Histogram is only a visual representation of data
Bickford2 does teach of slack threshold with respect to plurality of contexts (Bickford2, p. 4, [0034] “It should be noted that the preselected threshold arrival time can be selected as some optimal arrival time given the configuration of the modifiable periphery section(s) of the design block and its/their potential for power and/or area recovery. For example, if the modifiable periphery section is relatively small (i.e., includes a small number of devices) so that only a limited number of modifications could be made to that section to provide only a limited amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively early (e.g., closer to the earliest possible AT). However, if the modifiable periphery portion is relatively large (i.e., includes a large number of devices) so that various modifications could be made to that section to provide a significant amount of power and/or area recovery, then the predetermined threshold arrival time will be relatively late (e.g., closer to the latest possible AT).”)
In conclusion, Chandrasekar combined with Bickford2 teaches all features of claim 9. Claim 9 and the dependent claims remain rejected.
Regarding Argument 3
Independent Claim 17
Independent claim 17 sets a method comprising "modifying... at least one configuration parameter of the first set of configuration parameters based on the at least one outlier context to generate a second set of configuration parameters to be applied locally to the at least one outlier context to synthesize the circuit design," and "causing the EDA tool to perform a second execution iteration to synthesize the circuit design based on local application of the second set of configuration parameters to the at least one outlier context and global application of the first set of configuration parameters to other ones of the contexts not identified as outliers." Chandrasekar, individually or in combination with Bickford and/or Bickford2, does not teach or suggest such a method. Therefore, claim 17 is allowable, and withdrawal of the rejections of independent claim 17 and all claims depending therefrom is respectfully requested.
Response:
Bakshi teaches applying top-level constraints to all partitions and in addition applying partition constraints to lower partitions. (Bakshi, p. 3, [0045] “Upon START, the process 400 partitions the design into a hierarchy of partitions (Block 410). The hierarchy of partitions includes a top-level partition and lower partitions. The lower partitions include at least a bottom-level partition. The top-level partition has top-level constraints as described above. The details of Block 410 will be described in FIG. 5.”)
(Bakshi, p. 3, [0046] “Next, the process 400 synthesizes the lower partitions hierarchically from the bottom-level partition up to the top-level partition to create lower partition netlists based on the top-level constraints (Block 420). The details of Block 420 will be described in FIG. 6. Then, the process 400 optimizes the top-level netlist corresponding to the top-level partition to satisfy the top-level constraints and every compile point (CP) at lower level partitions to satisfy the corresponding partition constraints (Block 430) and is then terminated.”)
In essence, Bakshi combined with Chandrasekar teach all features of claim 17. Thus claim 17 and its dependent claims remains rejected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/R.S./ Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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