CTNF 18/166,974 CTNF 101591 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 7-11, and 15-19 are rejected under 35 U.S.C. 102( a)(1) and (a)(2 ) as being anticipated by Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter, Chandrasekar . Regarding claim 1 Chandrasekar discloses At least one non-transitory computer readable medium comprising computer readable instructions to cause processor circuitry to at least ( Chandrasekar, col. 9, lines 47-55 “ Those skilled in the art will appreciate that various alternative computing arrangements, including one or more processors and a memory arrangement configured with program code, would be suitable for hosting the processes and data structures disclosed herein. In addition, the processes may be provided via a variety of computer-readable storage media or delivery channels such as magnetic or optical disks or tapes, electronic storage devices, or as application services over a network .” ) ( Chandrasekar, col. 1, lines 55-59 “ A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instruction s that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis .” ) partition a circuit design into a plurality of contexts based on output data from a first execution iteration of an electronic design automation (EDA) tool, the output data including a netlist representative of the circuit design, the output data based on a first set of configuration parameters applied globally to the circuit design by the EDA tool ( Chandrasekar, col. 1, lines 56-59 “ A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instruction s that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) ( Chandrasekar, col 3, lines 60-61 “ At block 124 , the EDA tool generates a netlist from the mapped circuit design .” ) ( Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106 , the EDA tool validates constraint s of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 1, lines 49-54 “ According to other disclosed methods, during the first synthesis , the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions .” ) identify an outlier context in the plurality of contexts based on the output data; ( Chandrasekar, col. 1, lines 37-43 “ According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis . After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions .” ) and provide the EDA tool with a second set of configuration parameters to be applied locally to the outlier context in a second execution iteration of the EDA tool, the EDA tool to apply the first set of configuration parameters to other ones of the contexts not identified as outliers. ( Chandrasekar, col. 1, lines 43-45 “ The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions ” ) ( Chandrasekar, col. 1, lines 49-54 “ According to other disclosed methods, during the first synthesis , the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions .” ) ( Chandrasekar, col. 1, lines 59-66 “ The instructions further cause the computer processor to determine after a modification of the circuit design, changed partitions and unchanged partitions of the circuit design. The computer processor in executing the instructions determines dependent partitions of the changed partitions and re-synthesizes the changed partitions and the dependent partitions into respective re-synthesized partitions .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) ( Chandrasekar, col. 2, lines 21-22 “ FIG. 4 shows a partition dependency graph from an initial synthesis of a circuit design .” ) ( Chandrasekar, col. 2, lines 23-24 “ FIG. 5 shows the incremental partition dependency graph generated from incremental synthesis .” ) Regarding claim 2 Chandrasekar teaches all aspects of claim 1 and further discloses The at least one non-transitory computer readable medium of claim 1, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design. ( Chandrasekar, col. 3, lines 1-5 “ The EDA tool partitions the circuit design at block 112 . Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114 .” ) ( Chandrasekar, col. 2, lines 25-26 “ FIG. 6 shows a module instance hierarch y of an exemplary circuit design .” ) ( Chandrasekar, col. 3, lines 48-52 “ The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information, D M is shown as block 122 . The top skeleton is a data structure, e.g., a file that specifies the hierarch y of module instances and partitions forming circuit design D E 110 .” ) Regarding claim 3 Chandrasekar teaches all aspects of claim 1 and further discloses The at least one non-transitory computer readable medium of claim 1, wherein the outlier context is identified based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data. ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Regarding claim 7 Chandrasekar discloses all aspects of claim 1. The at least one non-transitory computer readable medium of claim 1, Chandrasekar further discloses wherein the second set of parameters is to specify a transition region between the outlier context and the other ones of the contexts, the EDA tool is to apply the second set of parameters to the outlier context, the EDA tool is to apply the first set of parameters outside the transition region, and the EDA tool is to apply a third set of parameters in the transition region, the third set of parameters based on the first set of parameters and the second set of parameters. ( Chandrasekar, col. 3, lines 5-15 “ FIG. 2 shows a flowchart of a process for incrementally re-synthesizing portions of a circuit design through use of a partition dependency graph to determine partitions that should be re- synthesized because of optimizations to changed partitions; A changed circuit design D′ is input to an EDA tool as shown by block 200 , and the EDA tool elaborates the changed circuit design at block 202 , producing elaborated, changed circuit design D E ' , which is shown as block 204 . At block 206 , the EDA tool validates constraints of the modified circuit design .” ) ( Chandrasekar, col. 3, lines 16-25 “ The EDA tool prepares for incremental synthesis at block 208 . The EDA tool inputs the elaborated circuit design D E and modified, elaborated circuit design D E ' , to determine which modules have changed and require re-synthesis. The partition dependency graph G is used to determine additional partitions (“dependent partitions”) to re-synthesize due to optimizations that cover pins in changed partitions and extend to pins in unchanged partitions. The top skeleton D M 122 and saved unchanged partitions are used in combining re- synthesized partitions with unchanged partitions. ” ) ( Chandrasekar, col. 3, lines 26-34 “ At block 210 , the EDA tool selects the changed partitions and dependent partitions and initiates optimization of the selected partitions at block 212 . In optimizing the selected partitions, the EDA tool generates a modified partition dependency graph G′, which is shown as block 214 , as optimization dependencies may change due to the changes to the design. The EDA tool performs technology mapping of the optimized partitions and generates an incremental netlist at block 216 .” ) Regarding claim 8 Chandrasekar teaches all aspects of claim 1 and further discloses The at least one non-transitory computer readable medium of claim 1, wherein the circuit design corresponds to a system on a chip. ( Chandrasekar, col. 8, lines 39-44 “ FIG. 11 shows a programmable integrated circuit (IC) 800 on which a circuit can be implemented according to the incremental synthesis approaches described herein. The programmable IC may also be referred to as a System On Chip ( SOC ) that includes field programmable gate array logic (FPGA) along with other programmable resources .” ) Regarding claim 9 Chandrasekar discloses An apparatus to operate an electronic design automation (EDA) tool, the apparatus comprising ( Chandrasekar, col. 7, lines 45-47 “ FIG. 10 is a block diagram illustrating an exemplary data processing system (system) 700 . System 700 is an example of an EDA system .” ) at least one memory ( Chandrasekar, col. 7, lines 47-49 “ As pictured, system 700 includes at least one processor circuit (or “processor”), e.g., a central processing unit (CPU) 705 coupled to memory ” ) machine readable instructions ( Chandrasekar, col. 7, lines 51-52 “ System 700 stores program code and circuit design 102 within memory and storage arrangement 720 .” ) and processor circuitry to at least one of instantiate or execute the machine readable instructions to ( Chandrasekar, col. 7, lines 47-54 “ As pictured, system 700 includes at least one processor circuit (or “ processor ”), e.g., a central processing unit (CPU) 705 coupled to memory and storage arrangement 720 through a system bus 715 or other suitable circuitry. System 700 stores program code and circuit design 102 within memory and storage arrangement 720 . Processor 705 executes the program code accessed from the memory and storage arrangement 720 via system bus 715 .” ) partition a circuit design into a plurality of contexts based on output data from a first execution iteration of the EDA tool, the output data including a netlist representative of the circuit design, the output data based on a first set of configuration parameters applied to the circuit design by the EDA tool ( Chandrasekar, col. 1, lines 56-59 “ A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instruction s that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) ( Chandrasekar, col 3, lines 60-61 “ At block 124 , the EDA tool generates a netlist from the mapped circuit design .” ) ( Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106 , the EDA tool validates constraint s of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 1, lines 49-54 “ According to other disclosed methods, during the first synthesis , the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions .” ) and provide the EDA tool with a second set of configuration parameters to be applied to an outlier context in a second execution iteration of the EDA tool, the EDA tool to apply the first set of configuration parameters to other ones of the contexts not identified as outliers. ( Chandrasekar, col. 1, lines 43-45 “ The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions ” ) ( Chandrasekar, col. 1, lines 49-54 “ According to other disclosed methods, during the first synthesis , the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions .” ) ( Chandrasekar, col. 1, lines 59-66 “ The instructions further cause the computer processor to determine after a modification of the circuit design, changed partitions and unchanged partitions of the circuit design. The computer processor in executing the instructions determines dependent partitions of the changed partitions and re-synthesizes the changed partitions and the dependent partitions into respective re-synthesized partitions .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) ( Chandrasekar, col. 2, lines 21-22 “ FIG. 4 shows a partition dependency graph from an initial synthesis of a circuit design .” ) ( Chandrasekar, col. 2, lines 23-24 “ FIG. 5 shows the incremental partition dependency graph generated from incremental synthesis .” ) Regarding claim 10 Chandrasekar discloses all aspects of claim 9 and further discloses The apparatus of claim 9, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design. ( Chandrasekar, col. 3, lines 1-5 “ The EDA tool partitions the circuit design at block 112 . Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114 .” ) ( Chandrasekar, col. 2, lines 25-26 “ FIG. 6 shows a module instance hierarch y of an exemplary circuit design .” ) ( Chandrasekar, col. 3, lines 48-52 “ The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information, D M is shown as block 122 . The top skeleton is a data structure, e.g., a file that specifies the hierarch y of module instances and partitions forming circuit design D E 110 .” ) Regarding claim 11 Chandrasekar discloses all aspects of claim 9 and further discloses The apparatus of claim 9, wherein the processor circuitry is to identify the outlier context based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data. ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Regarding claim 15 Chandrasekar discloses all aspects of claim 9 and further discloses The apparatus of claim 9, wherein the second set of parameters is to specify a transition region between the outlier context and the other ones of the contexts, the EDA tool is to apply the second set of parameters to the outlier context, the EDA tool is to apply the first set of parameters outside the transition region, and the EDA tool is to apply a third set of parameters in the transition region, the third set of parameters based on the first set of parameters and the second set of parameters. ( Chandrasekar, col. 3, lines 5-15 “ FIG. 2 shows a flowchart of a process for incrementally re-synthesizing portions of a circuit design through use of a partition dependency graph to determine partitions that should be re- synthesized because of optimizations to changed partitions; A changed circuit design D′ is input to an EDA tool as shown by block 200 , and the EDA tool elaborates the changed circuit design at block 202 , producing elaborated, changed circuit design D E ' , which is shown as block 204 . At block 206 , the EDA tool validates constraints of the modified circuit design .” ) ( Chandrasekar, col. 3, lines 16-25 “ The EDA tool prepares for incremental synthesis at block 208 . The EDA tool inputs the elaborated circuit design D E and modified, elaborated circuit design D E ' , to determine which modules have changed and require re-synthesis. The partition dependency graph G is used to determine additional partitions (“dependent partitions”) to re-synthesize due to optimizations that cover pins in changed partitions and extend to pins in unchanged partitions. The top skeleton D M 122 and saved unchanged partitions are used in combining re- synthesized partitions with unchanged partitions. ” ) ( Chandrasekar, col. 3, lines 26-34 “ At block 210 , the EDA tool selects the changed partitions and dependent partitions and initiates optimization of the selected partitions at block 212 . In optimizing the selected partitions, the EDA tool generates a modified partition dependency graph G′, which is shown as block 214 , as optimization dependencies may change due to the changes to the design. The EDA tool performs technology mapping of the optimized partitions and generates an incremental netlist at block 216 .” ) Regarding claim 16 Chandrasekar discloses all aspects of claim 9 and further discloses The apparatus of claim 9, wherein the circuit design corresponds to a system on a chip. ( Chandrasekar, col. 8, lines 39-44 “ FIG. 11 shows a programmable integrated circuit (IC) 800 on which a circuit can be implemented according to the incremental synthesis approaches described herein. The programmable IC may also be referred to as a System On Chip ( SOC ) that includes field programmable gate array logic (FPGA) along with other programmable resources .” ) Regarding claim 17 Chandrasekar discloses A method to operate an electronic design automation (EDA) tool, the method comprising ( Chandrasekar, col 7, lines 31-34 “ The disclosed method s and system reduce the time required to perform incremental synthesis and thereby improve performance of the computer system hosting the EDA tool .” ) partitioning, by executing an instruction with processor circuitry ( Chandrasekar, col 1, lines 55-59 “ A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instructions that when executed cause the computer processor to partition a circuit design into a plurality of partition s during a first synthesis .” ) a circuit design into a plurality of contexts based on output data from a first execution iteration of the EDA tool ( Chandrasekar, col. 1, lines 56-59 “ A disclosed system includes a computer processor, and a memory coupled to the computer processor. The memory is configured with instruction s that when executed cause the computer processor to partition a circuit design into a plurality of partitions during a first synthesis .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) the output data including a netlist representative of the circuit design ( Chandrasekar, col 3, lines 60-61 “ At block 124 , the EDA tool generates a netlist from the mapped circuit design .” ) the output data based on a first set of configuration parameters applied globally to the circuit design by the EDA tool identifying ( Chandrasekar, col 2, line 65 – col. 3, line 1 “ At block 106 , the EDA tool validates constraint s of the circuit design, such as through static power, timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) by executing an instruction with the processor circuitry, at least one outlier context in the plurality of contexts based on the output data ( Chandrasekar, col. 1, lines 37-43 “ According to one or more disclosed methods a computer processor partitions a circuit design into a plurality of partitions during a first synthesis . After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions .” ) and providing, by executing an instruction with the processor circuitry, the EDA tool with a second set of configuration parameters to be applied locally to the at least one outlier context in a second execution iteration of the EDA tool, the EDA tool to apply the first set of configuration parameters to other ones of the contexts not identified as outliers. ( Chandrasekar, col. 1, lines 43-45 “ The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions ” ) ( Chandrasekar, col. 1, lines 49-54 “ According to other disclosed methods, during the first synthesis , the computer processor generates a partition dependency graph of the circuit design in a memory. The partition dependency graph specifies optimization dependencies between partitions and may be used in determining dependent partitions of the changed partitions .” ) ( Chandrasekar, col. 1, lines 59-66 “ The instructions further cause the computer processor to determine after a modification of the circuit design, changed partitions and unchanged partitions of the circuit design. The computer processor in executing the instructions determines dependent partitions of the changed partitions and re-synthesizes the changed partitions and the dependent partitions into respective re-synthesized partitions .” ) ( Chandrasekar, col. 2, lines 19-20 “ FIG. 3 shows a flowchart of a process performed by an EDA tool in preparing for incremental synthesis ;” ) ( Chandrasekar, col. 2, lines 21-22 “ FIG. 4 shows a partition dependency graph from an initial synthesis of a circuit design .” ) ( Chandrasekar, col. 2, lines 23-24 “ FIG. 5 shows the incremental partition dependency graph generated from incremental synthesis .” ) Regarding claim 18 Chandrasekar discloses all aspects of claim 17 and further discloses The method of claim 17, wherein the contexts correspond to groups of logic cells partitioned at a hierarchical level of the circuit design. ( Chandrasekar, col. 3, lines 1-5 “ The EDA tool partitions the circuit design at block 112 . Each partition includes a portion of the logic of the circuit design, and the partitions are constructed such that optimizations of the partitions can be performed in parallel at block 114 .” ) ( Chandrasekar, col. 2, lines 25-26 “ FIG. 6 shows a module instance hierarch y of an exemplary circuit design .” ) ( Chandrasekar, col. 3, lines 48-52 “ The EDA tool at block 120 dumps the top skeleton and optimized partitions. The dumped design information, D M is shown as block 122 . The top skeleton is a data structure, e.g., a file that specifies the hierarch y of module instances and partitions forming circuit design D E 110 .” ) Regarding claim 19 Chandrasekar discloses all aspects of claim 17 and further discloses The method of claim 17, wherein the identifying of the at least one outlier context is based on at least one of power characteristics, area characteristics or timing characteristics determined for respective ones of the contexts from the output data. ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter, Chandrasekar in view of Jeanne P. Bickford et. al. (US 9767240 B2), hereinafter Bickford . Chandrasekar teaches all aspects of claim 1. The at least one non-transitory computer readable medium of claim 1, wherein the instructions are to cause the processor circuitry to : Chandrasekar also discloses determine, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Chandrasekar does not teach normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts; and compare the normalized power characteristics to a threshold to identify the outlier context. However, Bickford discloses b. normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts; ( Bickford, col. 7, line 7-15 “This per section total power consumption threshold ( I t ) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in μW/ m m 2 (e.g., 3 μW/ m m 2 , 4 μW/ m m 2 , etc.). For example, if the sections are 2 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in terms of μW/2 m m 2 (e.g., 6 μW/2 m m 2 , 8 μW/2 m m 2 , etc.).” ) ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) and compare the normalized power characteristics to a threshold to identify the outlier context. ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Chandrasekar and Bickford to yield predictable result of highly optimized circuit design . 07-22-aia AIA Claim s 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekar as applied to claim 1 above, and further in view of Jeanne P. Bickford et. al. (US 20170212977 A1), hereinafter Bickford2 . Regarding claim 5 Chandrasekar teaches all aspects of claim 1. The at least one non-transitory computer readable medium of claim 1, Chandrasekar does not teach wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value. However, Bickford2 discloses wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value. ( Bickford2, p. 4, [0032] “ The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time ( 110 ) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time ( 112 ). Specifically, at process 112 , the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Chandrasekar and Bickford2 to yield predictable result of highly optimized circuit design. Regarding claim 6 Chandrasekar and Bickford2 teach all aspects of claim 5 as disclosed above. The at least one non-transitory computer readable medium of claim 5, wherein the instructions are to cause the processor circuitry to: Chandrasekar does not teach determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram. However, Bickford2 discloses determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram. ( Bickford2, p. 4, [0031] “ For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205 a-j associated with each of the different instances 201 a-j of the design block 210 . These ATs 205 a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201 g and 201 h of the design block 210 ) to a latest AT of 10 ps (e.g., for instances 201 d and 201 f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201 g and 201 h of the design block 210 ) and 0 ps (e.g., for the instances 201 d and 201 f of the design block 210 ) .” ) ( Bickford2, p. 4, [0032] “ The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time ( 110 ) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time ( 112 ). Specifically, at process 112 , the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and Bickford2 to choose the slack threshold appropriate for the respective partition/design block to yield predictable result of highly optimized circuit design . 07-21-aia AIA Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter, Chandrasekar in view of Jeanne P. Bickford et. al. (US 9767240 B2), hereinafter Bickford . Chandrasekar teaches all aspects of claim 9. The apparatus of claim 9, wherein the instructions are to cause the processor circuitry to: Chandrasekar further discloses determine, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Chandrasekar does not teach normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts; and compare the normalized power characteristics to a threshold to identify the outlier context. However, Bickford discloses normalize the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts; ( Bickford, col. 7, line 7-15 “This per section total power consumption threshold ( I t ) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in μW/ m m 2 (e.g., 3 μW/ m m 2 , 4 μW/ m m 2 , etc.). For example, if the sections are 2 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in terms of μW/2 m m 2 (e.g., 6 μW/2 m m 2 , 8 μW/2 m m 2 , etc.).” ) ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) and compare the normalized power characteristics to a threshold to identify the outlier context. ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Chandrasekar and Bickford to yield predictable result of highly optimized circuit design . 07-22-aia AIA Claim s 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekar as applied to claim 1 above, and further in view of Jeanne P. Bickford et. al. (US 20170212977 A1), hereinafter Bickford2 . Regarding claim 13 Chandrasekar teaches all aspects of claim 9. The apparatus of claim 9, Chandrasekar does not teach wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value. However, Bickford2 discloses wherein the first set of parameters includes a first value for a slack threshold and the second set of parameters includes a second value for the slack threshold, the second value different from the first value. ( Bickford2, p. 4, [0032] “ The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time ( 110 ) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time ( 112 ). Specifically, at process 112 , the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Chandrasekar and Bickford2 to yield predictable result of highly optimized circuit design. Regarding claim 14 Chandrasekar and Bickford2 teach all aspects of claim 13 as disclosed above. The apparatus of claim 13, wherein the processor circuitry is to: Chandrasekar does not teach determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram. However, Bickford2 discloses determine a histogram of slack values for the plurality of contexts based on the output data; and determine the second value of the slack threshold based on the histogram. ( Bickford2, p. 4, [0031] “ For example, FIG. 5 shows the layout of the initial design of the IC 200 annotated with results of the timing analysis of process 108 and, particularly, annotated with the ATs 205 a-j associated with each of the different instances 201 a-j of the design block 210 . These ATs 205 a-j range from an earliest AT of 2 picoseconds (ps) (e.g., for the instances 201 g and 201 h of the design block 210 ) to a latest AT of 10 ps (e.g., for instances 201 d and 201 f of the design block). Corresponding slack times, thus, range from Bps (e.g., for the instances 201 g and 201 h of the design block 210 ) and 0 ps (e.g., for the instances 201 d and 201 f of the design block 210 ) .” ) ( Bickford2, p. 4, [0032] “ The method disclosed herein takes advantage of the earlier ATs at some of the design blocks and, thereby the greater slack times, in order to recover area and/or power without having to reclose timing. Specifically, the method can further include comparing (e.g., by the processor) the ATs associated with the multiple instances of the design block to a preselected threshold arrival time ( 110 ) and modifying (e.g., by the processor) any one or more of the modifiable periphery section(s) of each specific instance of the design block having an AT that is equal to or less than the preselected threshold arrival time ( 112 ). Specifically, at process 112 , the modifiable periphery section of a specific instance of the design block, which is usually invisible during top-level design, is made visible so that modifications can be made to that modifiable periphery section in order to reduce power consumption by the specific instance of the design block and/or to reduce the area of the chip taken up by the specific instance of the design block .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Chandrasekar and Bickford2 to choose the slack threshold appropriate for the respective partition/design block to yield predictable result of highly optimized circuit design . 07-21-aia AIA Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kameshwar Chandrasekar et. al. (US 10839118 B1) hereinafter, Chandrasekar in view of Jeanne P. Bickford et. al. (US 9767240 B2), hereinafter Bickford . Regarding claim 20: Chandrasekar teaches all aspects of claim 17. The method of claim 17, wherein the identifying of the at least one outlier context includes Chandrasekar further discloses determining, based on the output data, corresponding power characteristics and corresponding area characteristic for respective ones of the contexts ( Chandrasekar, col. 2, line 65 – col. 3 line 1 “ At block 106 , the EDA tool validates constraints of the circuit design, such as through static power , timing, and area analysis, and at block 108 saves the elaborated circuit design D E as shown by block 110 .” ) ( Chandrasekar, col. 3, lines 10-11 “ The optimizations performed by the EDA tool at block 114 can include area and timing optimizations .” ) Chandrasekar does not teach normalizing the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts and comparing the normalized power characteristics to one or more thresholds to identify the at least one outlier context. However, Bickford discloses normalizing the corresponding power characteristics by the corresponding area characteristics to determine normalized power characteristics for the respective ones of the contexts ( Bickford, col. 7, line 7-15 “This per section total power consumption threshold ( I t ) can be specified, for example, in microwatts per an area amount equal to the size of the sections. For example, if the sections are 1 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in μW/ m m 2 (e.g., 3 μW/ m m 2 , 4 μW/ m m 2 , etc.). For example, if the sections are 2 m m 2 in size, the per section total power consumption threshold ( I t ) can be define in terms of μW/2 m m 2 (e.g., 6 μW/2 m m 2 , 8 μW/2 m m 2 , etc.).” ) ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) and comparing the normalized power characteristics to one or more thresholds to identify the at least one outlier context. ( Bickford, col. 4, lines 44-49 “ That is, for each section, a total power consumption amount can be determined and compared to a per section total power consumption threshold. When the total power consumption amount associated with the sections is greater than the threshold, a hotspot is indicated .” ) Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to combine the teachings of Chandrasekar and Bickford to yield predictable result of highly optimized circuit design. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.S./Examiner, Art Unit 2851 /JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851 Application/Control Number: 18/166,974 Page 2 Art Unit: 2851 Application/Control Number: 18/166,974 Page 3 Art Unit: 2851 Application/Control Number: 18/166,974 Page 4 Art Unit: 2851 Application/Control Number: 18/166,974 Page 5 Art Unit: 2851 Application/Control Number: 18/166,974 Page 6 Art Unit: 2851 Application/Control Number: 18/166,974 Page 7 Art Unit: 2851 Application/Control Number: 18/166,974 Page 8 Art Unit: 2851 Application/Control Number: 18/166,974 Page 9 Art Unit: 2851 Application/Control Number: 18/166,974 Page 10 Art Unit: 2851 Application/Control Number: 18/166,974 Page 11 Art Unit: 2851 Application/Control Number: 18/166,974 Page 12 Art Unit: 2851 Application/Control Number: 18/166,974 Page 13 Art Unit: 2851 Application/Control Number: 18/166,974 Page 14 Art Unit: 2851 Application/Control Number: 18/166,974 Page 15 Art Unit: 2851 Application/Control Number: 18/166,974 Page 16 Art Unit: 2851 Application/Control Number: 18/166,974 Page 17 Art Unit: 2851 Application/Control Number: 18/166,974 Page 18 Art Unit: 2851 Application/Control Number: 18/166,974 Page 19 Art Unit: 2851 Application/Control Number: 18/166,974 Page 20 Art Unit: 2851 Application/Control Number: 18/166,974 Page 21 Art Unit: 2851 Application/Control Number: 18/166,974 Page 22 Art Unit: 2851 Application/Control Number: 18/166,974 Page 23 Art Unit: 2851 Application/Control Number: 18/166,974 Page 24 Art Unit: 2851 Application/Control Number: 18/166,974 Page 25 Art Unit: 2851 Application/Control Number: 18/166,974 Page 26 Art Unit: 2851 Application/Control Number: 18/166,974 Page 27 Art Unit: 2851 Application/Control Number: 18/166,974 Page 28 Art Unit: 2851 Application/Control Number: 18/166,974 Page 29 Art Unit: 2851 Application/Control Number: 18/166,974 Page 30 Art Unit: 2851 Application/Control Number: 18/166,974 Page 31 Art Unit: 2851 Application/Control Number: 18/166,974 Page 32 Art Unit: 2851 Application/Control Number: 18/166,974 Page 33 Art Unit: 2851 Application/Control Number: 18/166,974 Page 34 Art Unit: 2851
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