DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 in the reply filed on 08/14/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHOI et al. (US 20200365537 A1, hereinafter Choi)
With regards to claim 1, Choi discloses a semiconductor structure, comprising:
a plurality of bit line stack structures, (bit line BL including dielectric 120, as is consistent with the Specification) wherein the plurality of bit line stack structures are disposed on a substrate; (substrate 102)
wherein each of the plurality of bit line stack structures comprises a bit line insulating layer, (insulating layer 120, 152, and 164) a bit line (bit line 114) and a bit line contact plug (direct contact DC) which are sequentially stacked onto one another from top to bottom. (See FIG. 2)
a plurality of storage contact structures, (bit contact BC and landing pad LP) wherein each of the plurality of storage contact structures is disposed between a pair of bit line stack structures of the plurality of bit line stack structures, (See FIG. 2) each of the plurality of storage contact structures comprises a storage node plug (bit contact BC) and a contact pad (landing pad LP) disposed above the storage node plug, and a topmost surface of the contact pad is lower than a topmost surface of the bit line insulating layers; (see at least FIG. 2, where the bit contacts BC are between adjacent bit lines BL and have a top surface directly under dielectric 152 lower than a topmost surface of the dielectric 164 of the bit line stack) and
a plurality of capacitor structures, (capacitors CAP) wherein a part of a bottom surface of a lower electrode (lower electrode 30) of each of the plurality of capacitor structures is supported on the top surface of a respective one of the plurality of storage contact structures, and another part of the bottom surface of the lower electrode is supported on the top surface of a respective one of the plurality of bit line stack structures, (see FIG. 2, where a portion of the lower electrode 30 is supported by the landing pad LP and the other portion of the electrode is supported by the bit line BL/dielectric 120 via the dielectric 152) a bottommost surface of a lower electrode of each of the plurality of capacitor structures is lower than the topmost surface of the bit line insulating layer. (see FIG. 2, showing the bottommost portion of the lower electrode 30 lower than a topmost surface of dielectric 164, see also response to arguments)
With regards to claim 3, Choi discloses the semiconductor structure of claim 1, wherein the contact pad is connected to the storage node plug by a pad adhesion layer. (barrier layer 150)
With regards to claim 4, Choi discloses the semiconductor structure of claim 1, wherein the bit line is connected to the bit line contact plug by a bit line adhesion layer. (second conductive layer 112/110)
With regards to claim 5, Choi discloses the semiconductor structure of claim 1, wherein a top surface of the storage node plug is higher than a bottom surface of the bit line insulating layer; (see FIG. 2, showing the landing pad LP having an upper surface being higher)
wherein a bottom surface of the storage node plug is higher than a bottom surface of the bit line contact plug. (see FIG. 2, showing the landing pad LP having a bottom surface being higher)
With regards to claim 6, Choi discloses the semiconductor structure of claim 1, wherein an area of a top surface of the lower electrode is less than an area of the bottom surface of the lower electrode. (see FIG. 2, where the bottom surface of the electrode 30 has a greater area, as the bottom surface fractures into two portions which add up to a greater area)
With regards to claim 8, Choi discloses the semiconductor structure of claim 1, wherein a longitudinal cross section of each of the plurality of storage contact structures is T-shaped. (see FIG. 2, showing the “T” shape)
With regards to claim 9, Choi discloses the semiconductor structure of claim 1, wherein each of the plurality of capacitor structures is a columnar capacitor or a cup-shaped capacitor. (see FIG. 2, showing the columnar shape)
With regards to claim 10, Choi discloses the semiconductor structure of claim 1, wherein a contact area of the lower electrode and the top surface of the respective one of the plurality of storage contact structures is greater than a contact area of the lower electrode and the top surface of the respective one of the plurality of bit line stack structures. (see FIG. 2, showing the greater contact area of the LP and lower electrode 30 than the lower electrode 30 and the bit line 114/120)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHOI et al. (US 20200365537 A1, hereinafter Choi)
With regards to claim 7, Choi discloses the semiconductor structure of claim 1.
However, Choi does not explicitly teach wherein a cross section of a lower part of the lower electrode is gradually increased from top to bottom.
Choi generally teaches a change in the shape of the electrode from top to bottom, where it should be noted that the court held that the configuration of the claimed [device] was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed [device] was significant.). (See MPEP 2144.04 IV B. Changes in shape) In the instant case, the current device would not perform differently with the relative dimensions than the prior art device, and thus is not patentably distinct.
Therefore, it would have been obvious to one of ordinary skill in the art to modify the device of Choi to have the shape as recited in the above recited claim.
Response to Arguments
Applicant's arguments filed 11/21/2025 have been fully considered but they are not persuasive.
Examiner notes that interpreting the insulating layer 120, 152, and 164 as part of the bit line insulating structure meets all of the limitations of at least claim 1, and the claims are broad enough to support this interpretation. Therefore, Choi discloses or teaches all of the limitations of at least claims 1-10, and thus claims 1-10 are properly rejected under 35 USC 102/103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KIM et al (US 20220406791 A1) – landing pad LP with direct contact on bit line cap.
MOON et al. (US 20220173107 A1) – direct contact of the landing pad to the bit line cap
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812