DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s reply filed on 01/14/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-7 and 9-13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “wherein the semiconductor structure is a column structure and the gate layer is arranged around” is not clear because semiconductor structure means by entire device structure is column structure or intrinsic region only is column structure, is not defined. Instant application discloses “the intrinsic semiconductor layer 10 has a columnar structure and the gate layer 12 is arranged around the intrinsic semiconductor layer 10”, Para [ 0060]. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 3-7 and 9-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of ZHNAG et al (US 2015/020288 A1; hereafter ZHANG).
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Regarding claim 1. Holz discloses a semiconductor structure of a junction less transistor (Fig 1, transistor T2, Para [ 0055]), comprising:
a source doped region ( Fig 1, transistor T2, heavily n-doped source region S2, Para [ 0055]), a drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]), a lightly doped region (extension regions ES2, Para [ 0055]) and an intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) arranged adjacent to each other and located between the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) and the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]), wherein the lightly doped region (extension regions ES2, Para [ 0055]) is adjacent to the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]), and the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) is adjacent to the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]);
a gate layer (Fig 1, transistor T2, gate GD2, construed as gate layer, Para [ 0055]) at least covering an end adjacent to the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) of the lightly doped region (extension regions ES2, Para [ 0055]); and,
wherein a doping concentration of the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) and the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]) is greater than a doping concentration of the lightly doped region ( Para [0055] discloses “ Optionally, both at the source region S2 and at the drain region D2 it is possible to form extension regions ES2 and ED2, respectively, which have a lower dopant concentration than the source region S2 and than the drain region D2”); wherein the source doped region (Fig 1, transistor T2, heavily n-doped source region S2, Para [ 0055]), the drain doped region (Fig 1, heavily n-doped drain region D2, Para [ 0055]) and the lightly doped region have a same type ( n-type) of doped ions (extension regions ES2, Para [ 0055]); and the gate layer is arranged around (Fig 1, transistor T2, gate GD2, construed as gate layer, Para [ 0055]))
But, Holz does not disclose explicitly wherein the semiconductor structure is a column structure.
In a similar field of endeavor, ZHANG discloses wherein the semiconductor structure is a column structure (Fig 1, Para [ 0053] discloses “an N-type tunneling field effect transistor, the source region 10 may be a P-type dopant region and the drain region 20 may be an N-type dopant region. In other embodiments, if the tunneling field effect transistor is a P-type tunneling field effect transistor, the source region 10 may be an N-type dopant region and the drain region 20 may be a P-type dopant region. The channel region 30 may be an intrinsic region (e.g., including only the intrinsic material without any dopant). Alternatively, the channel region 30 may be a P-type or N-type dopant region (e.g., including an intrinsic material and dopant) that is more lightly doped than the source region 10 and the drain region 20”. This shape is column shape).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz in light of ZHANG teaching “wherein the semiconductor structure is a column structure (Fig 1, Para [ 0053] discloses “an N-type tunneling field effect transistor, the source region 10 may be a P-type dopant region and the drain region 20 may be an N-type dopant region. In other embodiments, if the tunneling field effect transistor is a P-type tunneling field effect transistor, the source region 10 may be an N-type dopant region and the drain region 20 may be a P-type dopant region. The channel region 30 may be an intrinsic region (e.g., including only the intrinsic material without any dopant). Alternatively, the channel region 30 may be a P-type or N-type dopant region (e.g., including an intrinsic material and dopant) that is more lightly doped than the source region 10 and the drain region 20”. This shape is column shape)” for further advantage such as minimizes or eliminates ambipolar such as the drain-side tunneling phenomenon, to obtain a low off-current.
Regarding claim 9. Holz and ZHANG discloses the semiconductor structure according to claim 1, Holz further discloses wherein the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) is completely covered by the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]), and an interface between the lightly doped region (extension regions ES2, Para [ 0055]) and the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) is flush with a sidewall adjacent to the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) of the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]).
Regarding claim 10. Holz and ZHANG discloses the semiconductor structure according to claim 1, Holz further discloses wherein the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]) further covers an end adjacent to the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) of the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region).
Regarding claim 11. Holz and ZHANG discloses the semiconductor structure according to claim 9, Holz further discloses wherein the gate layer (Fig 1, transistor T2, gate GD2, Para [ 0055]) further covers an end adjacent to the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) of the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of ZHNAG et al (US 2015/020288 A1; hereafter ZHANG) as applied claims above and further in view of Shrivastava et al (US 2014/0008733 A1; hereafter Shrivastava).
Regarding claim 3. Holz and ZHANG discloses the semiconductor structure according to claim 1, But, Holz and ZHANG does not disclose explicitly wherein a ratio of the doping concentration of the source doped region and the drain doped region to the doping concentration of the lightly doped region is in a range of 10 to 100.
In a similar field of endeavor, Shrivastava discloses wherein a ratio of the doping concentration of the source doped region and the drain doped region (Fig 2, Para [ 0021] discloses “A source region 212 and a drain region 214 are disposed in or adjacent to the upper fin portion 202b. The source region 212 and drain region 214 have a first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”) to the doping concentration of the lightly doped region is in a range of 10 to 100 ( Para [ 0023] discloses “ The source extension region 222 has the first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”, which are substantially same as source and drain region. Therefore, ratio fall in a range of 10 to 100).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Shrivastava teaching “wherein a ratio of the doping concentration of the source doped region and the drain doped region (Fig 2, Para [ 0021] discloses “A source region 212 and a drain region 214 are disposed in or adjacent to the upper fin portion 202b. The source region 212 and drain region 214 have a first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”) to the doping concentration of the lightly doped region is in a range of 10 to 100 ( Para [ 0023] discloses “ The source extension region 222 has the first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”, which are substantially same as source and drain region. Therefore, ratio fall in a range of 10 to 100)” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 4. Holz and ZHANG discloses the semiconductor structure according to claim 1, But, Holz and ZHANG does not disclose explicitly wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3.
In a similar field of endeavor, Shrivastava discloses wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3
(Fig 2, Para [ 0021-0023]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Shrivastava teaching “wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3 (Fig 2, Para [ 0021-0023])” for further advantage such as enhance carrier mobility and improve device performance.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of ZHNAG et al (US 2015/020288 A1; hereafter ZHANG) as applied claims above and further in view of SASAKI (US 2006/0214223 A1; hereafter SASAKI).
Regarding claim 5. Holz and ZHANG discloses the semiconductor structure according to claim 1, Holz further discloses weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and ZHANG does not disclose explicitly wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region.
In a similar field of endeavor, Shrivastava discloses wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region
(Fig 55, Para [ 0210]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Shrivastava teaching “wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region (Fig 55, Para [ 0210])” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 6. Holz and ZHANG in light of Shrivastava discloses the semiconductor structure according to claim 5, Shrivastava further discloses wherein the lightly doped region comprises a plurality of sub-doped regions ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) arranged along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]), wherein doping concentrations of the plurality of sub-doped regions are gradually decreased along the first direction ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Shrivastava teaching “wherein the lightly doped region comprises a plurality of sub-doped regions ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) arranged along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]), wherein doping concentrations of the plurality of sub-doped regions are gradually decreased along the first direction ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210])” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 7. Holz Holz and ZHANG in light Shrivastava discloses the semiconductor structure according to claim 5, Shrivastava further discloses wherein the doping concentration of the lightly doped region is gradually and continuously decreased (Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Shrivastava teaching “wherein the doping concentration of the lightly doped region is gradually and continuously decreased (Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206])” for further advantage such as enhance carrier mobility and improve device performance.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of ZHNAG et al (US 2015/020288 A1; hereafter ZHANG) as applied claims above and further in view of Yamazaki et al (US 5308,998 A1; hereafter Yamazaki).
Regarding claim 12. Holz and ZHANG discloses the semiconductor structure according to claim 10, Holz further discloses gate layer (Fig 1, transistor T2, gate G2/GD2, construed as gate layer, Para [ 0055]) covers entire channel region [30] and lightly doped region (ES2) and weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and ZHANG does not disclose explicitly wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6.
In a similar field of endeavor, Yamazaki discloses wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Yamazaki teaching “wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted)” for further advantage such as high switching speed and a low on-state resistance.
Regarding claim 13. Holz and ZHANG discloses the semiconductor structure according to claim 11, Holz further discloses gate layer (Fig 1, transistor T2, gate G2/GD2, construed as gate layer, Para [ 0055]) covers entire channel region [30] and lightly doped region (ES2) and weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and ZHANG does not disclose explicitly wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6.
In a similar field of endeavor, Yamazaki discloses wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and ZHANG in light of Yamazaki teaching “wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted)” for further advantage such as high switching speed and a low on-state resistance.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898