DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/17/2026 has been entered. An action on the RCE follows.
Response to Arguments
Applicant’s reply filed on 05/17/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 4727,044; hereafter Yamazaki) in view of Ueda (US 2002/0125535; hereafter Ueda).
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Regarding claim 1. Yamazaki discloses a semiconductor structure of a junction less transistor, comprising:
a source doped region (Fig 1, drain regions 5S, col 6, lines 25-35), a drain doped region (Fig 1, drain regions 5D, col 6, lines 25-35), a lightly doped region (a non-crystallized region 6C, col 6, lines 1-35) and
an intrinsic region (semiconductor layer 2 is constituted of an amorphous semiconductor, col 6, lines 5-20) arranged adjacent to each other and located between the source doped region (Fig 1, drain regions 5S) and the drain doped region (Fig 1, drain regions 5D), wherein the lightly doped region (a non-crystallized region 6C, col 6, lines 1-35 and col 7, lines 50-65) is adjacent to the source doped region (Fig 1, drain regions 5S), and the intrinsic region (semiconductor layer 2 is constituted of an amorphous semiconductor) is adjacent to the drain doped region (Fig 1, drain regions 5D);
a gate layer (gate 5G, col 6, lines 1-35) at least covering an end adjacent to the intrinsic region (semiconductor layer 2 is constituted of an amorphous semiconductor, col 6, lines 5-20) of the lightly doped region (a non-crystallized region 6C, 6C, col 6, lines 1-35 and col 7, lines 50-65); and,
wherein the intrinsic region is a column structure (semiconductor layer 2, col 6, lines 5-20) and the gate layer is arranged around (gate 5G, col 6, lines 1-35).
But Yamazaki does not disclose explicitly wherein a doping concentration of the source doped region and the drain doped region is greater than a doping concentration of the lightly doped region; wherein the source doped region, the drain doped region and the lightly doped region have a same type of doped ions.
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In a similar field of endeavor, Ueda discloses wherein a doping concentration of the source doped region ( Fig 8G, source region or first n-type heavily doped region, 28a, Para [ 0135]) and the drain doped region (drain region or second n-type heavily doped region 28b, Para [ 0135]) is greater than a doping concentration of the lightly doped region ( n-type lightly doped region 76a, Para [ 0135]); wherein the source doped region ( Fig 8G, source region or first n-type heavily doped region, 28a, Para [ 0135]), the drain doped region and the lightly doped region (drain region or second n-type heavily doped region 28b, Para [ 0135]) have a same type of doped ions ( n-type lightly doped region 76a, Para [ 0135]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Yamazaki in light of Ueda teaching “wherein a doping concentration of the source doped region ( Fig 8G, source region or first n-type heavily doped region, 28a, Para [ 0135]) and the drain doped region (drain region or second n-type heavily doped region 28b, Para [ 0135]) is greater than a doping concentration of the lightly doped region ( n-type lightly doped region 76a, Para [ 0135]); wherein the source doped region ( Fig 8G, source region or first n-type heavily doped region, 28a, Para [ 0135]), the drain doped region and the lightly doped region (drain region or second n-type heavily doped region 28b, Para [ 0135]) have a same type of doped ions ( n-type lightly doped region 76a, Para [ 0135])” for further advantage such as enhance carrier mobility in the channel region and improve device performance.
ALTERNATE REJECTION:
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of Marino et al (US 2017/0170276 A1; hereafter Marino).
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Regarding claim 1. Holz discloses a semiconductor structure of a junction less transistor (Fig 1, transistor T2, Para [ 0055]), comprising:
a source doped region ( Fig 1, transistor T2, heavily n-doped source region S2, Para [ 0055]), a drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]), a lightly doped region (extension regions ES2, Para [ 0055]) and an intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) arranged adjacent to each other and located between the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) and the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]), wherein the lightly doped region (extension regions ES2, Para [ 0055]) is adjacent to the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]), and the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) is adjacent to the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]);
a gate layer (Fig 1, transistor T2, gate GD2, construed as gate layer, Para [ 0055]) at least covering an end adjacent to the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region) of the lightly doped region (extension regions ES2, Para [ 0055]); and,
wherein a doping concentration of the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) and the drain doped region ( Fig 1, heavily n-doped drain region D2, Para [ 0055]) is greater than a doping concentration of the lightly doped region ( Para [0055] discloses “ Optionally, both at the source region S2 and at the drain region D2 it is possible to form extension regions ES2 and ED2, respectively, which have a lower dopant concentration than the source region S2 and than the drain region D2”); wherein the source doped region (Fig 1, transistor T2, heavily n-doped source region S2, Para [ 0055]), the drain doped region (Fig 1, heavily n-doped drain region D2, Para [ 0055]) and the lightly doped region have a same type ( n-type) of doped ions (extension regions ES2, Para [ 0055]); and the gate layer is arranged around (Fig 1, transistor T2, gate GD2, construed as gate layer, Para [ 0055]))
But, Holz does not disclose explicitly wherein the intrinsic region is a column structure.
In a similar field of endeavor, Marino discloses wherein the intrinsic region is a column structure (Fig [1-2], [13-16], Para [ 0032-0036], column shape intrinsic channel region 18).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz in light of Marino teaching “wherein the semiconductor structure is a column structure (Fig 1, Para [ 0053] discloses “an N-type tunneling field effect transistor, the source region 10 may be a P-type dopant region and the drain region 20 may be an N-type dopant region. In other embodiments, if the tunneling field effect transistor is a P-type tunneling field effect transistor, the source region 10 may be an N-type dopant region and the drain region 20 may be a P-type dopant region. The channel region 30 may be an intrinsic region (e.g., including only the intrinsic material without any dopant). Alternatively, the channel region 30 may be a P-type or N-type dopant region (e.g., including an intrinsic material and dopant) that is more lightly doped than the source region 10 and the drain region 20”. This shape is column shape)” for further advantage such as increase of the carrier mobility associated with the use of an intrinsic channel region.
Regarding claim 9. Holz and Marino discloses the semiconductor structure according to claim 1, Holz further discloses wherein the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) is completely covered by the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]), and an interface between the lightly doped region (extension regions ES2, Para [ 0055]) and the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) is flush with a sidewall adjacent to the source doped region ( Fig 1, heavily n-doped source region S2, Para [ 0055]) of the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]).
Regarding claim 10. Holz and Marino discloses the semiconductor structure according to claim 1, Holz further discloses wherein the gate layer (Fig 1, transistor T2, gate G2/GD2, Para [ 0055]) further covers an end adjacent to the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) of the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region).
Regarding claim 11. Holz and Marino discloses the semiconductor structure according to claim 9, Holz further discloses wherein the gate layer (Fig 1, transistor T2, gate GD2, Para [ 0055]) further covers an end adjacent to the lightly doped region (Fig 1, transistor T2, extension regions ES2, Para [ 0055]) of the intrinsic region (weakly p-doped channel forming region 30, construed as intrinsic region).
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of Marino et al (US 2017/0170276 A1; hereafter Marino) as applied claims above and further in view of Shrivastava et al (US 2014/0008733 A1; hereafter Shrivastava).
Regarding claim 3. Holz and Marino discloses the semiconductor structure according to claim 1, But, Holz and Marino does not disclose explicitly wherein a ratio of the doping concentration of the source doped region and the drain doped region to the doping concentration of the lightly doped region is in a range of 10 to 100.
In a similar field of endeavor, Shrivastava discloses wherein a ratio of the doping concentration of the source doped region and the drain doped region (Fig 2, Para [ 0021] discloses “A source region 212 and a drain region 214 are disposed in or adjacent to the upper fin portion 202b. The source region 212 and drain region 214 have a first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”) to the doping concentration of the lightly doped region is in a range of 10 to 100 ( Para [ 0023] discloses “ The source extension region 222 has the first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”, which are substantially same as source and drain region. Therefore, ratio fall in a range of 10 to 100).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Shrivastava teaching “wherein a ratio of the doping concentration of the source doped region and the drain doped region (Fig 2, Para [ 0021] discloses “A source region 212 and a drain region 214 are disposed in or adjacent to the upper fin portion 202b. The source region 212 and drain region 214 have a first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”) to the doping concentration of the lightly doped region is in a range of 10 to 100 ( Para [ 0023] discloses “ The source extension region 222 has the first conductivity type (e.g., n-type) at a first doping concentration (e.g., ranging from about 1e21 cm.sup.-3 to about 1e22 cm.sup.-3”, which are substantially same as source and drain region. Therefore, ratio fall in a range of 10 to 100)” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 4. Holz and Marino discloses the semiconductor structure according to claim 1, But, Holz and Marino does not disclose explicitly wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3.
In a similar field of endeavor, Shrivastava discloses wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3
(Fig 2, Para [ 0021-0023]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Shrivastava teaching “wherein the doping concentration of the source doped region and the drain doped region and the doping concentration of the lightly doped region are in a range of 1E19cm-3 to 1E21cm-3 (Fig 2, Para [ 0021-0023])” for further advantage such as enhance carrier mobility and improve device performance.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of Marino et al (US 2017/0170276 A1; hereafter Marino) as applied claims above and further in view of SASAKI (US 2006/0214223 A1; hereafter SASAKI).
Regarding claim 5. Holz and Marino discloses the semiconductor structure according to claim 1, Holz further discloses weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and Marino does not disclose explicitly wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region.
In a similar field of endeavor, Shrivastava discloses wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region
(Fig 55, Para [ 0210]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Shrivastava teaching “wherein the doping concentration of the lightly doped region close to the intrinsic region is less than the doping concentration of the lightly doped region away from the intrinsic region (Fig 55, Para [ 0210])” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 6. Holz and Marino in light of Shrivastava discloses the semiconductor structure according to claim 5, Shrivastava further discloses wherein the lightly doped region comprises a plurality of sub-doped regions ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) arranged along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]), wherein doping concentrations of the plurality of sub-doped regions are gradually decreased along the first direction ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Shrivastava teaching “wherein the lightly doped region comprises a plurality of sub-doped regions ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) arranged along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]), wherein doping concentrations of the plurality of sub-doped regions are gradually decreased along the first direction ( Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210])” for further advantage such as enhance carrier mobility and improve device performance.
Regarding claim 7. Holz Holz and Marino in light Shrivastava discloses the semiconductor structure according to claim 5, Shrivastava further discloses wherein the doping concentration of the lightly doped region is gradually and continuously decreased (Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Shrivastava teaching “wherein the doping concentration of the lightly doped region is gradually and continuously decreased (Fig 55, plurality sub-doped region 109-3, 109-2 and 109-1, Para [0210]) along a first direction that is a direction extending from the source doped region (Fig 55, heavily doped 111-1, Para [ 0204-0206]) toward the drain doped region (Fig 55, heavily doped 111-2, Para [ 0204-0206])” for further advantage such as enhance carrier mobility and improve device performance.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Holz et al (US 2009/0101975 A1; hereafter Holz) in view of Marino et al (US 2017/0170276 A1; hereafter Marino) as applied claims above and further in view of Yamazaki et al (US 5308,998 A1; hereafter Yamazaki).
Regarding claim 12. Holz and Marino discloses the semiconductor structure according to claim 10, Holz further discloses gate layer (Fig 1, transistor T2, gate G2/GD2, construed as gate layer, Para [ 0055]) covers entire channel region [30] and lightly doped region (ES2) and weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and Marino does not disclose explicitly wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6.
In a similar field of endeavor, Yamazaki discloses wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Yamazaki teaching “wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted)” for further advantage such as high switching speed and a low on-state resistance.
Regarding claim 13. Holz and Marino discloses the semiconductor structure according to claim 11, Holz further discloses gate layer (Fig 1, transistor T2, gate G2/GD2, construed as gate layer, Para [ 0055]) covers entire channel region [30] and lightly doped region (ES2) and weakly p-doped channel forming region 30, construed as intrinsic region.
But, Holz and Marino does not disclose explicitly wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6.
In a similar field of endeavor, Yamazaki discloses wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Holz and Marino in light of Yamazaki teaching “wherein a ratio of a length of a part covered by the gate layer of the lightly doped region to a length of a part covered by the gate layer of the intrinsic region is greater than 0.6 (Col 4, lines 5-68 discloses “the length L of the LDD regions can be arbitrarily and finely adjusted from 10 nm to 0.1 micrometer. The overlapping dimension between the gate electrode 105 the LDD regions 107 can be controlled at a similar accuracy as explained above. The channel length W can be reduced to 0.5 micrometer or less in this case. Conventionally, it had been very difficult to form a LDD region having 100 nm or less length and the error had been usually 20% or thereabout. It becomes, however, possible to form LDD regions having 10 to 100 nm lengths only with errors of about 10%”. Based on that, the overlapping ration can be grater than 0.6, since length of LDD regions can be arbitrarily and finely adjusted)” for further advantage such as high switching speed and a low on-state resistance.
Conclusion
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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