DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities: [0031] appears to contain a typo as in line 20 p. 5, the paragraph number contains a strike through “.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the product value" in lines 17, 20. Claim 13, of which claim 17 depends on, recites “ a first product value” and “a second product value” and thus the limitation renders the claim indefinite as it unclear which product value it is referring to in claim 13, or if it meant to refer to some other instance of “product value”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 10-12 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20220036165 A1 Kwon (hereinafter “Kwon”).
Regarding claim 1, Kwon discloses a processing unit (Fig. 7A [0134]) comprising a multiply-accumulate engine (Fig. 7A “710, 720, … other PEs” of top portion and unnumbered bottom portion [0137] containing MAC units) and a control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths), wherein: the multiply-accumulate engine comprises a plurality of dot product units (Fig. 7A multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]), switching circuitry (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), a plurality of adders (Fig. 7A adders
⊕
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]), and a plurality of accumulators (Fig. 7A “ACC” [0136]; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]);
the switching circuitry is coupled between the dot product units and the adders (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) and is configurable to selectively couple each of the adders to one of the plurality of dot product units (example in Fig. 7A MUX in “710” connected to adder
⊕
below it, and multiplier
⊗
above it; another example in Fig. 7A MUX in “720” connected to adder
⊕
of “720” and multiplier
⊗
of “710”; [0110] Note: descriptions of Figs. 1-6B are applicable see [0133]);
each of the adders is associated with a respective accumulator of the plurality of accumulators (Fig. 7A each adder
⊕
corresponds with an “ACC” [0136, 0139]; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]); and
in a processing cycle ([0136], [0139] each time; [0146], [0154] cycles), each of the dot product units is configured to output a product value (Fig. 7A outputs from multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]), the control unit ([0136], [0138]) is operable to configure the switching circuitry such that each of the adders is coupled to a selected dot product unit of the plurality of dot product units (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
and selects based on control signal of MODE (systolic or SIMD) [0134]; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), and each of the adders is configured to add the product value of the selected dot product unit to an accumulated value stored by the respective accumulator (Fig. 7A adders
⊕
receive multipliers
⊗
output and output of ACC; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]).
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Kwon discloses wherein:
the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to configure the switching circuitry (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) such that at least some of the adders (Fig. 7A adders
⊕
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) are coupled to different dot product units (Fig. 7A multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) in different processing cycles (Fig. 7A “710” adder
⊕
connected to multiplier
⊗
in “710”, Fig. 7A “720” adder
⊕
connected to multiplier
⊗
in “710” when mode signals multiplexer connection, and “720” adder
⊕
connected to multiplier
⊗
in “720” as one example [0137]; [0146], [0154] cycles).
Regarding claim 5, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Kwon discloses wherein:
each of the dot product units (Fig. 7A multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) is configured to output a product value (Fig. 7A outputs from multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) corresponding to a product of a value of an input feature map (Fig. 1A “111” [0079]; Fig. 1C “171, 172, 173, 174” [0086]) and a weight of a filter (Fig. 1A “121, 122, 123” [0079]; Fig. 1C “181, 182, 183, 184” [0086]), and the accumulated value of each of the accumulators (Fig. 7A adders
⊕
receive multipliers
⊗
output and output of ACC; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) corresponds to an element of an output feature map (Fig. 1A “115, 127, 128, 129, 130” [0079]; Fig. 1C “Output Feature Map” [0086-0087]).
Regarding claim 10, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Kwon discloses wherein:
the switching circuitry comprises a plurality of multiplexers (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), each of the multiplexers comprises a plurality of inputs and an output (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
with input connection ports to “0” and “1” and output connection port; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), each of the inputs is coupled to an output of one of the dot product units (Fig. 7A inputs of MUXs directly connected to multipliers
⊗
with input connection ports to “0” and “1”; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), and the output is coupled to an input of a respective adder of the plurality of adders (Fig. 7A output of MUXs directly connected to adders
⊕
with output connection port; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]).
Claims 11-12 are directed to a system that recites similar limitations to the apparatus of claims 1 and 10, respectively. The claims 1 and 10 analysis similarly applies, and claims 11-12 are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 6-9, 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon as applied to claim 1 above, and further in view of US 20180225116 A1 Henry et al. (hereinafter “Henry”).
Regarding claim 3, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Kwon discloses wherein:
in a first processing cycle, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to configure the switching circuitry (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) such that a first adder (Fig. 7A adder
⊕
in “710”) of the plurality of adders (Fig. 7A adders
⊕
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) is coupled to a first dot product unit (Fig. 7A multiplier
⊗
in “710”) of the plurality of dot product units (Fig. 7A multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]), and
in a second processing cycle, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to configure the switching circuitry (Fig. 7A MUXs directly connected to adders
⊕
and multipliers
⊗
; [0032], [0108], [0110], [0113], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) such that a second adder (Fig. 7A adder
⊕
in “720”) of the plurality of adders (Fig. 7A adders
⊕
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) is coupled to the first dot product unit (Fig. 7A multiplier
⊗
in “710”).
Although Kwon generally discloses processing cycles ([0136], [0139] each time; [0146], [0154] cycles), they appear to be silent to disclose explicitly a first and second processing cycle.
Henry discloses a first (Fig. 5 “clk 1” [0130]) and second processing cycle (Fig. 5 “clk 2” [0131]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kwon with Henry’s processing cycle feature because they are in the claimed invention’s same field of endeavor of multiplier accumulator circuitry ([abstract]). Although Kwon discloses cycles generally, it appears they are silent with disclosing a first and second processing cycle explicitly. Henry is in the claimed invention’s same field of endeavor of multiply-accumulate operations utilizing subcircuits for computing calculations (Fig. 2 “126-J” [0110]) and discloses the execution of the subcircuits with a cycle-by-cycle breakdown (Fig. 5 [0128]). Modifying Kwon’s circuitry to generate a timing diagram of the execution of the circuity would have been beneficial as doing so would provide better indication of how data flows throughout the circuitry ([0128]) and would provide information to designers on how to best optimize the design of the circuitry ([0136]). It would have been obvious to one of ordinary skill in the art to implement the first and second processing cycle features before the effective filing date to advantageously benefit from the information such timing diagram would provide and provide designers with better indication of where to optimize performance of the circuitry.
Regarding claim 4, the teachings addressed in the claim 3 analysis and rejection are incorporated, and Kwon discloses wherein:
in the first processing cycle, the first dot product unit (Fig. 7A multiplier
⊗
in “710”) is configured to output a first product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “1”) corresponding to a product of a first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) and a second value (Fig. 7A “B” in “710” connected to multiplexer control signal “1” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]); and
in the second processing cycle, the first dot product unit (Fig. 7A multiplier
⊗
in “710”) is configured to output a second product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “0”) corresponding to a product of the first value (Fig. 7A “A” in “710” [0137]) and a third value (Fig. 7A “B” in “710” connected to multiplexer control signal “0” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]).
Although Kwon generally discloses processing cycles ([0136], [0139] each time; [0146], [0154] cycles), they appear to be silent to disclose explicitly a first and second processing cycle.
Henry discloses a first (Fig. 5 “clk 1” [0130]) and second processing cycle (Fig. 5 “clk 2” [0131]).
The motivation to combine provided with respect to claim 3 similarly applies.
Regarding claim 6, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Kwon discloses wherein:
the processing unit (Fig. 7A [0134]) comprises a plurality of input registers, and a weight register;
each of the dot product units (Fig. 7A multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) comprises a first input (Fig. 7A multipliers
⊗
input connection to A [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) coupled to a respective input register of the plurality of input registers, and a second input (Fig. 7A multipliers
⊗
input connection to B [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) coupled to the weight register.
Although Kwon generally discloses input terminal ports for A and B ([0138]), Kwon appears to be silent to explicitly disclose them as a plurality of input registers and a weight register.
Henry discloses a plurality of input registers (Fig. 2 “208” [0111]; Fig. 3 “208” [0118]) and a weight register (Fig. 2 “205” [0111]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kwon with Henry’s plurality of registers feature because they are in the claimed invention’s same field of endeavor of multiplier accumulator circuitry ([abstract]). Although Kwon discloses input terminals generally, they appear to be silent with disclosing such terminals as registers explicitly. Henry is in the claimed invention’s same field of endeavor of multiply-accumulate operations utilizing subcircuits for computing calculations (Fig. 2 “126-J” [0110]) and discloses receiving inputs via registers (Fig. 2 “208, 205” [0111]). Modifying Kwon’s circuitry to receive inputs via registers would have been simple substitution of the input terminals to registers. Henry discloses registers are a known generic memory component in the art ([0118]) and are suitable for performing the functionalities of receiving, storing, and gathering data for processing purposes ([0111]). Further, making the modification would have yielded predictable results. It would have been obvious to try with predictable results to one of ordinary skill in the art to implement the register features as substitutes for the terminal ports before the effective filing date to achieve the predictable result of receiving, storing, and gathering data for processing.
Regarding claim 7, the teachings addressed in the claim 6 analysis and rejection are incorporated, and Kwon discloses wherein:
in a first processing cycle, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to load each of the input registers with a respective value (Fig. 7B “t1” of “740” [0138-0139] vector received through input terminal A), and to load the weight register with a first weight (Fig. 7B “t1” of “730” [0138-0139] matrix received through input terminal B); and
in a second processing cycle, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to load a subset of the input registers with a new respective value (Fig. 7B “t2” of “740” [0138-0139] vector received through input terminal A), and load the weight register with a second weight (Fig. 7B “t2” of “730” [0138-0139] matrix received through input terminal B).
Although Kwon generally discloses input terminal ports for A and B ([0138]), Kwon appears to be silent to explicitly disclose them each of the input registers, a subset of the input registers, the weight register, a first processing cycle, and a second processing cycle.
Henry discloses each of the input registers (Fig. 2 “208” [0111]; Fig. 3 “208” [0118]), a subset of the input registers (Fig. 3 “208” [0118] combination of “208”), the weight register (Fig. 2 “205” [0111]), a first processing cycle (Fig. 5 “clk 1” [0130]), and a second processing cycle (Fig. 5 “clk 2” [0131]).
The motivation to combine provided with respect to claims 3 and 6.
Regarding claim 8, the teachings addressed in the claim 6 analysis and rejection are incorporated, and Kwon discloses wherein:
the processing unit (Fig. 7A [0134]) is operable to perform a convolution operation ([0086]) over a plurality of processing cycles; and
in each processing cycle of the plurality of processing cycles, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to load the weight register with a weight of a filter (Fig. 1A “121, 122, 123” [0079]; Fig. 1C “181, 182, 183, 184” [0086]), and the weights employed in each pair of consecutive processing cycles are contiguous weights of the filter (Fig. 1A “121, 122, 123” [0079]; Fig. 1C “181, 182, 183, 184” [0086]).
Although Kwon generally discloses input terminal ports for A and B ([0138]), Kwon appears to be silent to explicitly disclose them as the weight register, in each processing cycle of the plurality of processing cycles, and in each pair of consecutive processing cycles.
Henry discloses the weight register (Fig. 2 “205” [0111]), in each processing cycle of the plurality of processing cycles (Fig. 5 clk [0128], [0133]), and in each pair of consecutive processing cycles (Fig. 5 “clk 1, clk 2” [0130-0131]).
The motivation to combine provided with respect to claims 3 and 6.
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Kwon discloses wherein:
in each processing cycle of the plurality of processing cycles, the control unit (Fig. 7A “712” & other multiplexers before A/B [0137]; [0135-0136] control circuit includes multiplexers and data paths) is operable to load (Fig. 7B “t2” of “740” [0138-0139] vector received through input terminal A) at least some of the input registers with values of an input feature map (Fig. 1A “111” [0079]; Fig. 1C “171, 172, 173, 174” [0086]).
Although Kwon generally discloses input terminal ports for A and B ([0138]), Kwon appears to be silent to explicitly disclose them at least some of the input registers and in each processing cycle of the plurality of processing cycles.
Henry discloses at least some of the input registers (Fig. 2 “208” [0111]; Fig. 3 “208” [0118]) and in each processing cycle of the plurality of processing cycles (Fig. 5 clk [0128], [0133]).
The motivation to combine provided with respect to claims 3 and 6.
Regarding claim 13, Kwon discloses a method of performing multiply-accumulate operations comprising:
in a first processing cycle, using a dot product unit (Fig. 7A multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) to output a first product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “1”), and adding (Fig. 7A adder
⊕
in “710” adding input from mux and fed back signal of “ACC” ; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) the first product value to a first accumulated value (Fig. 7A output of “ACC” of “710” that is fed back to adder
⊕
in “710” ) of a first accumulator (Fig. 7A “ACC” in “710” [0136]); and
in a second processing cycle, using the dot product unit (Fig. 7A multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) to output a second product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “0”), and adding (Fig. 7A adder
⊕
in “720” adding input from mux (fed back signal of “ACC”) and output of multiplier
⊗
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) the second product value to a second accumulated value (Fig. 7A output of “ACC” of “720” that is fed back to adder
⊕
via mux in “720” ) of a second accumulator (Fig. 7A “ACC” in “720” [0136]).
Although Kwon generally discloses processing cycles ([0136], [0139] each time; [0146], [0154] cycles), they appear to be silent to disclose explicitly a first and second processing cycle.
Henry discloses a first (Fig. 5 “clk 1” [0130]) and second processing cycle (Fig. 5 “clk 2” [0131]).
The motivation to combine provided with respect to claim 3 similarly applies.
Regarding claim 14, the teachings addressed in the claim 13 analysis and rejection are incorporated, and Kwon discloses wherein:
the first product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “1”) is a product of a first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) and a second value (Fig. 7A “B” in “710” connected to multiplexer control signal “1” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), and the second product value (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “0”) is a product of the first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) and a third value (Fig. 7A “B” in “710” connected to multiplexer control signal “0” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]).
Regarding claim 15, the teachings addressed in the claim 14 analysis and rejection are incorporated, and Kwon discloses wherein:
the first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) is a value of an input feature map (Fig. 1A “111” [0079]; Fig. 1C “171, 172, 173, 174” [0086]), the second value (Fig. 7A “B” in “710” connected to multiplexer control signal “1” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) is a first weight (Fig. 7B “t1” of “730” [0138-0139] matrix received through input terminal B) of a filter (Fig. 1A “121, 122, 123” [0079]; Fig. 1C “181, 182, 183, 184” [0086]), the third value (Fig. 7A “B” in “710” connected to multiplexer control signal “0” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]) is a second weight (Fig. 7B “t2” of “730” [0138-0139] matrix received through input terminal B) of the filter (Fig. 1A “121, 122, 123” [0079]; Fig. 1C “181, 182, 183, 184” [0086]), the first accumulated value (Fig. 7A output of “ACC” of “710” that is fed back to adder
⊕
in “710” ) corresponds to a first element (Fig. 1C “191” [0085-0086]) of an output feature map (Fig. 1A “115, 127, 128, 129, 130” [0079]; Fig. 1C “Output Feature Map” [0086-0087]), and the second accumulated value (Fig. 7A output of “ACC” of “720” that is fed back to adder
⊕
via mux in “720” ) corresponds to a second element (Fig. 1C “192” [0085-0086]) of the output feature map (Fig. 1A “115, 127, 128, 129, 130” [0079]; Fig. 1C “Output Feature Map” [0086-0087]).
Regarding claim 16, the teachings addressed in the claim 14 analysis and rejection are incorporated, and Kwon discloses wherein:
the dot product unit (Fig. 7A multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) comprises a first input (Fig. 7A multipliers
⊗
input connection to A [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) coupled to a first register and a second input (Fig. 7A multipliers
⊗
input connection to B [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) coupled to a second register, the dot product unit is configured to output a product value (Fig. 7A outputs from multipliers
⊗
[0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) corresponding to the product of values (Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “1”; Fig. 7A multiplier
⊗
in “710” output [0134], [0137] when control signal is “0”) in the first register and the second register, and the method comprises:
in the first processing cycle: loading (Fig. 7B “t1” of “740” [0138-0139] vector received through input terminal A) the first register with the first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), and loading (Fig. 7B “t1” of “730” [0138-0139] matrix received through input terminal B) the second register with the second value (Fig. 7A “B” in “710” connected to multiplexer control signal “1” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]); and
in the second processing cycle: leaving the first register loaded with the first value (Fig. 7A “A” in “710” [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]), and loading the second register with the third value (Fig. 7A “B” in “710” connected to multiplexer control signal “0” [0137], [0129] Note: descriptions of Figs. 1-6B are applicable see [0133]).
Although Kwon generally discloses input terminal ports for A and B ([0138]), Kwon appears to be silent to explicitly disclose them as leaving the first register loaded, loading the second register, the first processing cycle, and loading the second processing cycle.
Henry discloses leaving the first register (Fig. 2 “208” [0111]; Fig. 3 “208” [0118]) loaded (Fig. 6A “122” [0130-0135]), loading (Fig. 6A “124” [0130-0135]) the second register (Fig. 2 “205” [0111]), a first processing cycle (Fig. 5 “clk 1” [0130]), and a second processing cycle (Fig. 5 “clk 2” [0131]).
The motivation to combine provided with respect to claims 3 and 6.
Regarding claim 17, the teachings addressed in the claim 13 analysis and rejection are incorporated, and Kwon discloses wherein:
the dot product unit (Fig. 7A multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) comprises an output (Fig. 7A multiplier
⊗
in “710” output [0134], [0137]) coupled to a first input of a first multiplexer (Fig. 7A input port “0” of mux connected between multiplier ⊗ and adder
⊕
in “710” [0137]) and to a first input of a second multiplexer (Fig. 7A input port “0” of mux in “720” receiving signal from “710” [0137]);
the first multiplexer (Fig. 7A input port “0” of mux connected between multiplier ⊗ and adder
⊕
in “710” [0137]) comprises one or more further inputs coupled to outputs of one or more further dot product units, and an output (Fig. 7A multiplier ⊗ from “710” output [0137-0138]) coupled to a first adder (Fig. 7A adder
⊕
in “710” [0137-0138]) associated with the first accumulator (Fig. 7A “ACC” connected to adder
⊕
in “710” [0137-0138]);
the second multiplexer (Fig. 7A input port “0” of mux in “720” receiving signal from “710” [0137]) comprises one or more further inputs coupled to the outputs of the one or more further dot product units (Fig. 7A multiplier ⊗ from “710” output connected to mux in “720” at connection port 0 [0137-0138]), and an output (Fig. 7A multiplier ⊗ from “720” output [0137-0138]) coupled to a second adder (Fig. 7A adder
⊕
in “720” [0137-0138]) associated with the second accumulator (Fig. 7A “ACC” connected to adder
⊕
in “720” [0137-0138]);
and the method comprises:
in the first processing cycle, selecting the first input (Fig. 7A input port “0” of mux connected between multiplier ⊗ and adder
⊕
in “710” [0137]) of the first multiplexer (Fig. 7A input port “0” of mux connected between multiplier ⊗ and adder
⊕
in “710” [0137]) and selecting one of the further inputs of the second multiplexer (Fig. 7A input port “0” or “1” of mux in “720” receiving signal from “710” [0137]) such that the product value of the dot product unit (Fig. 7A output from multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) is added (Fig. 7A adder
⊕
in “710” adding input from mux and fed back signal of “ACC” ; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) to the first accumulated value (Fig. 7A output of “ACC” of “710” that is fed back to adder
⊕
in “710” ) by the first adder (Fig. 7A adder
⊕
in “710”); and
in the second processing cycle, selecting the first input of the second multiplexer (Fig. 7A input port “0” of mux in “720” receiving signal from “710” [0137]) and selecting one of the further inputs of the first multiplexer (Fig. 7A input port “0” or “1” of mux connected between multiplier ⊗ and adder
⊕
in “710” [0137]) such that the product value of the dot product unit (Fig. 7A output from multiplier
⊗
in “710” [0137]; [0080] Note: descriptions of Figs. 1-6B are applicable see [0133]) is added (Fig. 7A adder
⊕
in “720” adding input from mux (fed back signal of “ACC”) and output of multiplier
⊗
; [0108], [0110], [0113] Note: descriptions of Figs. 1-6B are applicable see [0133]) to the second accumulated value (Fig. 7A output of “ACC” of “720” that is fed back to adder
⊕
via mux in “720” ) by the second adder (Fig. 7A adder
⊕
in “720”).
Kwon appears to be silent to explicitly disclose the first processing cycle, the second processing cycle, and one or more further inputs coupled to outputs of one or more further dot product units.
Henry discloses the first processing cycle (Fig. 5 “clk 1” [0130]), the second processing cycle (Fig. 5 “clk 2” [0131]), and one or more further inputs coupled to outputs (Fig. 2 “211” [0111], [0118]) of one or more further dot product units.
The motivation to combine provided with claim 6 similarly applies. In addition, while Kwon discloses the input/output connections of the processing engines generally, it appears they are silent with disclosing the preliminary dot product engine’s multiplexer coupled to outputs of one or more further dot product units explicitly. Henry is in the claimed invention’s same field of endeavor of multiply-accumulate operations utilizing subcircuits for computing calculations (Fig. 2 “126-J” [0110]) and discloses the execution of the subcircuits with a cycle-by-cycle breakdown (Fig. 5 [0128]). Modifying Kwon’s circuitry to enable the multiplexer as receiving inputs from other dot product units would effectively enable the cores to operate as a word rotater, or circular shifter ([0111]). It would have been obvious to one of ordinary skill in the art to implement this feature before the effective filing date to advantageously benefit from effectively enabling the operation of word rotater (or a circular shifter) as such would allow more effective distribution of data to the necessary components ([0118]).
Conclusion
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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