DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note: It is possible to create an alloy of silver that can be used as a melting powder. For example, silver-tin alloy powder is used in soldering and brazing due to its low melting point and good solderability.
a transient liquid bonding material can indeed be a melting powder. In transient liquid phase (CP) Bonding, a low-melting-point material (often a metal powder) is used as an interlayer. This powder melts during the bonding process, forming a liquid phase that reacts with the surrounding materials, creating a bond.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, and 7-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda et al. (U.S. 2017/0207160) cited in the record in view of Nakano et al. (U.S. 2014/0193650), hereafter Nakano.
As to claim 1, Gowda discloses a method for manufacturing a circuit configuration (40) as shown in figures 2-10, the method comprising:
forming a substrate (100, para-0041);
providing a circuit board (42, para-0033) on the substrate (100) such that a cavity (51, figure 2 or 108, figure 9) is formed between the circuit board (42) and the substrate (100), and
a first gap (space in between the circuit board and substrate) is formed between the circuit board and the substrate; and closing the first gap via a first tolerance compensation element (92 or 98) by applying a sintered silver or metallic alloys (para-0039+) to at least one of the substrate or the circuit board.
Gowda does not specifically disclose the first tolerance compensation element, which is a power, and melting the powder.
Nakano teaches an electroconductive material (10) as shown in figures 1a-1c comprising a pair of electrodes (11a, 11b) having the first tolerance compensation (10 have elements 1 and 2) element, which is a power, and melting the powder.
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Nakano employed in the method of Gowda in order to provide high strength, excellent electrical insulation, and highly reliable connections.
As to claim 2, Gowda as modified by Nakano discloses the first tolerance compensation element is an additive manufacturing layer (84, figures 7-8).
As to claim 7, Gowda as modified by Nakano further comprising: positioning a semiconductor component (68, 70) in the cavity (108).
As to claim 8, Gowda as modified by Nakano discloses the forming the substrate includes forming a direct copper bonded substrate (100, para-0041).
As to claim 9, Gowda as modified by Nakano discloses the circuit board (42) has an undersize (where the element 92 or 98 formed on) such that the first gap is a defined distance.
As to claims 10-11, Gowda as modified by Nakano discloses the forming the substrate (DCB substrate 100) includes forming the substrate in a copper-aluminum-copper or a copper-ceramic- copper arrangement (the DCB consists of alumina or aluminum oxide).
As to claim 12, Gowda as modified by Nakano discloses the first tolerance compensation element (92 or 98) includes a material or alloy that is wettable for solder materials, para-0039+.
As to claim 13, Gowda as modified by Nakano discloses the undersize is configured such that a second gap (the gap where the element 64 formed on) is formed between the circuit board (42) and a semiconductor element (68 or 70) in the cavity (51 or 108).
As to claim 14, Gowda as modified by Nakano further comprising closing the second gap via a second tolerance compensation element (64, figure 5).
As to claim 15, Gowda as modified by Nakano further comprising: determining distance of the first gap for a pairing of the substrate (100) and the circuit board (42) via a closed control loop.
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gowda in view of Nakano, and further in view of Bruck et al. (U.S. 2015/0033561).
Regarding claims 5-6, Gowda as modified by Nakano discloses all of the limitations of claimed invention except for the melting the powder includes melting the powder in a punctiform manner or via a laser beam.
Bruck teaches a laser cladding particle injection process as shown in figure 3 comprising the melting the powder (68) on a surface (70) of the substrate (66) via a laser beam (60).
It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Bruck employed in the circuit configuration of Gowda and Nakano in order to create complex, high-precision metal parts layer by layer by selectively melting and fusing powdered materials. This process is used for a wide range of applications, including customized medical implants, turbine blades, and specialized automotive parts.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, and 5-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T DINH/ Primary Examiner, Art Unit 2848