DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Species I (claims 1-5, 8, 9, 10-12, 15, 17-19, and 21-26) in the reply filed on 04/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claims 4, 12 and 15 are objected to because of the following informalities:
Claim 4 recites the limitation "a plurality of the interconnect members" (emphasis added) in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a plurality of the interconnect members” (as recited in claim 4, lines 1-2) is:
"the plurality of the interconnect members" (emphasis added).
Claim 12 recites the limitation "a plurality of the interconnect members" (emphasis added) in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “a plurality of the interconnect members” (as recited in claim 12, lines 1-2) is:
"the plurality of the interconnect members" (emphasis added).
Claim 12 recites the limitation "the at least one interconnect member" (emphasis added) in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the at least one interconnect member” (as recited in claim 12, line 3) is:
" the at least one of interconnect members " (emphasis added).
Claim 12 also recites the limitation "the at least one interconnect member" (emphasis added) in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the at least one interconnect member” (as recited in claim 12, lines 4-5) is:
" the at least one of interconnect members " (emphasis added).
Claim 15 recites the limitation "the interconnect member" (emphasis added) in line 3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the Examiner assumes the above limitation of “the interconnect member” (as recited in claim 15, line 3) is:
"the interconnect members" (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 8-11, 15, 17, 19, 21-23, and 25-26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by EID et al. (U.S 2020/0235082 A1).
As to claim 1, EID et al. disclose in Fig. 4 an electrical package (“semico nductor package” 400) comprising: a substrate (401) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 4, para. [0070]-[0071]); one or more electrical components (“one or more dies” 405-409) mounted to the substrate (401) (Fig. 4, para. [0071]); and a plurality of electrically conductive interconnect members (“posts” 410a-410c) coupled to the second side (top side/surface) of the substrate (401), including at least one (“four L-shaped corner posts” 410b) of the interconnect members (“posts” 410a-410c) that is L-shaped (Fig. 4, para. [0047], [0071]).
As to claim 2, as applied to claim 1 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the L-shaped interconnect member (“four L-shaped corner posts” 410b) has a junction, a first arm that extends in a first direction (see a horizontal direction or x-direction portion of 410b, Fig. 4) from the junction, and a second arm that extends in a second direction (see a y-direction portion of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) from the junction (Fig. 4).
As to claim 3, as applied to claims 1 and 2 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein an angle between the first direction (see a horizontal direction or x-direction of 410b, Fig. 4) and the second direction (see a y-direction of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) is between about 80 degrees and about 100 degrees (an angle of 90 degrees, Fig. 4).
As to claim 5, as applied to claim 1 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the substrate (401) has a rectangular shape in plan view with four corners, with the L-shaped interconnect member (410b) positioned at or proximate one of the corners (Fig. 4).
As to claim 8, as applied to claim 1 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the interconnect members (“posts” 410a-410c) are arranged as a grid, with a group of the interconnect members (“posts” 410a-410c) each occupying a single grid cell, and the L-shaped interconnect member (410b) occupying at least three grid cells (Fig. 4).
As to claim 9, as applied to claim 1 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the package (400) is a dual-sided molded package (see Figs. 3A, & 4).
As to claim 10, EID et al. disclose in Fig. 4 an electrical package comprising: a substrate (401) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 4, para. [0070]-[0071]); one or more electrical components (“one or more dies” 405-409) mounted to the substrate (401) (Fig. 4, para. [0071]); and a plurality of electrically conductive interconnect members (“posts” 410a-410c) coupled to the second side (top side/surface) of the substrate (401), including at least one (“four L-shaped corner posts” 410b) of the interconnect members (“posts” 410a-410c) that has a first arm extending in a first direction (see a horizontal direction or x-direction portion of 410b, Fig. 4) and a second arm extending in a second direction (see a y-direction portion of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) that is substantially perpendicular to the first direction (a horizontal direction or x-direction portion of 410b, Fig. 4) (Fig. 4, para. [0047], [0071]).
As to claim 11, as applied to claim 10 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the first arm (see a horizontal direction or x-direction portion of 410b, Fig. 4) and the second arm (see a y-direction portion of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) are arranged so that the at least one of the interconnect members (410b) is L-shaped (Fig. 4).
As to claim 15, as applied to claim 10 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the interconnect members (“posts” 410a-410c) are arranged as a grid, with a group of the interconnect members (“posts” 410a-410c) each occupying a single grid cell, and the interconnect members (“posts” 410a-410c) with the first and second arms (a horizontal direction or x-direction portion of 410b and a y-direction portion of 410b which is perpendicular to a horizontal direction portion of 410b) occupying at least three grid cells (Fig. 4).
As to claim 17, EID et al. disclose in Fig. 4 an electrical package comprising: a substrate (401) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 4, para. [0070]-[0071]); one or more electrical components (“one or more dies” 405-409) mounted to the substrate (401) (Fig. 4, para. [0071]); and a plurality of electrically conductive interconnect members (“posts” 410a-410c) arranged as a two-dimensional array on the second side (top side/surface) of the substrate (401), including a plurality first interconnect members (410a) that each occupy one array location (see Figs. 3A -4), and at least one second interconnect member (comprising 410b & 410c) that occupies at least a first array location (Fig. 4), a second array location (Fig. 4), and a third array location (Fig. 4), the first, second, and third array locations arranged non-linearly (see the locations of 410b & 410c in Fig. 4).
As to claim 19, as applied to claim 17 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the second interconnect member (410b) that occupies at least the first, second, and third array locations is L-shaped (Fig. 4).
As to claim 21, as applied to claim 17 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the second interconnect member (comprising 410b & 410c) that occupies at least the first, second, and third array locations is a furthest interconnection member (410c) from a center of the package (Fig. 4).
As to claim 22, as applied to claim 17 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the second interconnect member (comprising 410b & 410c) includes: a first arm (see a horizontal direction or x-direction portion of 410b, Fig. 4) that extends from the first array location to the second array location along a first direction (a horizontal direction or x-direction) (Fig. 4); and a second arm (see a y-direction portion of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) that extends from the first array location to the third array location along a second direction (a y-direction which is perpendicular to the first direction or horizontal direction, Fig. 4) (Fig. 4).
As to claim 23, as applied to claims 17and 22 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein an angle between the first direction (see a horizontal direction or x-direction of 410b, Fig. 4) and the second direction (see a y-direction of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) is between about 80 degrees and about 100 degrees (an angle of 90 degrees, Fig. 4).
As to claim 25, as applied to claims 17and 22 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the second interconnect member (comprising 410b & 410c) has a junction with a shape of one of the first interconnect members (410a) (Fig. 4), the first arm (see a horizontal direction or x-direction portion of 410b, Fig. 4) has a shape of one of the first interconnect members (410a) coupled by a first bridge portion to the junction, and the second arm (see a y-direction portion of 410b which is perpendicular to the first direction or horizontal direction, Fig. 4) has a shape of one of the first interconnect members (410a) coupled by a second bridge portion to the junction (Fig. 4).
As to claim 26, as applied to claim 17 above, EID et al. disclose in Fig. 4 all claimed limitations including the limitation: wherein the package (400) is a dual-sided molded package (see Figs. 3A, & 4).
Claim(s) 4, 12, 18 and 24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Figure 6 (second embodiment) of EID et al. (U.S 2020/0235082 A1).
As to claim 4, EID et al. disclose in Fig. 6 an electrical package (“semiconductor package” 600) comprising: a substrate (601) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 6, para. [0070], [0076]); one or more electrical components (“dies” 605-607) mounted to the substrate (601) (Fig. 6, para. [0076]); and a plurality of electrically conductive interconnect members (comprising “posts” 610a & 610b) coupled to the second side (top side/surface) of the substrate (601), including at least one (610b) of the interconnect members (comprising “posts” 610a & 610b) that is L-shaped (see “L-shaped interconnect member” as annotated in Fig. 6 below, and para. [0076]);
wherein the L-shaped interconnect member (see “L-shaped interconnect member” as annotated in Fig. 6 below) has a junction, a first arm that extends in a first direction (see a horizontal direction or x-direction portion of 610b, annotated Fig. 6 below) from the junction, and a second arm that extends in a second direction (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction, annotated Fig. 6 below) from the junction (see annotated Fig. 6 below); and
wherein the plurality of the interconnect members (comprising “posts” 610a & 610b) have a circular shape (see member/post 610a having a circular shape) in plan view with a substantially uniform diameter (Fig. 6), the first arm (see a horizontal direction or x-direction portion of 610b) of the L-shaped interconnect member (see “L-shaped interconnect member” as annotated in Fig. 6 below) having a width that is substantially equal to the diameter of the circular interconnect members (610a), and the second arm (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction) of the L-shaped interconnect member (see “L-shaped interconnect member” as annotated in Fig. 6 below) having a width that is substantially equal to the diameter of the circular interconnect members (610a) (see annotated Fig. 6 below).
PNG
media_image1.png
526
1066
media_image1.png
Greyscale
As to claim 12, EID et al. disclose in Fig. 6 an electrical package (600) comprising: a substrate (601) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 6, para. [0070], [0076]); one or more electrical components (“dies” 605-607) mounted to the substrate (601) (Fig. 6, para. [0076]); and a plurality of electrically conductive interconnect members (comprising “posts” 610a & 610b) coupled to the second side (top side/surface) of the substrate (601), including at least one (610b) of the interconnect members (comprising “posts” 610a & 610b) that has a first arm extending in a first direction (see a horizontal direction or x-direction portion of 610b, annotated Fig. 6 below) and a second arm extending in a second direction (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction, annotated Fig. 6 below) that is substantially perpendicular to the first direction (a horizontal direction or x-direction portion of 610b, annotated Fig. 6) (see annotated Fig. 6, para. [0076]);
wherein a plurality of the interconnect members (comprising “posts” 610a & 610b) have a circular shape (see member/post 610a having a circular shape) in plan view with a substantially uniform diameter (Fig. 6), the first arm (see a horizontal direction or x-direction portion of 610b) of the at least one of interconnect members (comprising “posts” 610a & 610b) having a width that is substantially equal to the diameter of the circular interconnect members (610a) (Fig. 6), and the second arm (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction) of the at least one of interconnect members (comprising “posts” 610a & 610b) having a width that is substantially equal to the diameter of the circular interconnect members (610a) (see Fig. 6).
PNG
media_image1.png
526
1066
media_image1.png
Greyscale
As to claim 18, EID et al. disclose in Fig. 6 an electrical package (600) comprising: a substrate (601) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 6, para. [0070], [0076]); one or more electrical components (“dies” 605-607) mounted to the substrate (601) (Fig. 6, para. [0076]); and a plurality of electrically conductive interconnect members (comprising “posts” 610a & 610b) arranged as a two-dimensional array on the second side (top side/surface) of the substrate (601), including a plurality first interconnect members (610a) that each occupy one array location (see Figs. 3A & 6), and at least one second interconnect member (610b) that occupies at least a first array location (Fig. 6), a second array location (Fig. 6), and a third array location (Fig. 6), the first, second, and third array locations arranged non-linearly (see the locations of three portions/arms of 610b in Fig. 6);
wherein the first interconnect members (610a) that occupy one array location have a circular shape (see Fig. 6).
As to claim 24, EID et al. disclose in Fig. 6 an electrical package (600) comprising: a substrate (601) having a first side (bottom side/surface) and a second side (top side/surface) opposite the first side (bottom side/surface) (see Figs. 3A-3B & 6, para. [0070], [0076]); one or more electrical components (“dies” 605-607) mounted to the substrate (601) (Fig. 6, para. [0076]); and a plurality of electrically conductive interconnect members (comprising “posts” 610a & 610b) arranged as a two-dimensional array on the second side (top side/surface) of the substrate (601), including a plurality first interconnect members (610a) that each occupy one array location (see Figs. 3A & 6), and at least one second interconnect member (610b) that occupies at least a first array location (Fig. 6), a second array location (Fig. 6), and a third array location (Fig. 6), the first, second, and third array locations arranged non-linearly (see the locations of three portions/arms of 610b in Fig. 6);
wherein the second interconnect member (610b) includes: a first arm (see a horizontal direction or x-direction portion of 610b, annotated Fig. 6 below) that extends from the first array location to the second array location along a first direction (a horizontal direction or x-direction) (Fig. 6); and a second arm (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction, annotated Fig. 6 below) that extends from the first array location to the third array location along a second direction (a y-direction which is perpendicular to the first direction or horizontal direction, Fig. 6) (see annotated Fig. 6 below);
wherein the plurality of the interconnect members (comprising “posts” 610a & 610b) have a circular shape (see member/post 610a having a circular shape) in plan view with a substantially uniform diameter (Fig. 6), the first arm (see a horizontal direction or x-direction portion of 610b) of the second interconnect member (610b) having a width that is substantially equal to the diameter of the circular interconnect members (610a) (see annotated Fig. 6 below), and the second arm (see a y-direction portion of 610b which is perpendicular to the first direction or horizontal direction) of the second interconnect member (610b) having a width that is substantially equal to the diameter of the circular interconnect members (610a) (see annotated Fig. 6 below).
PNG
media_image1.png
526
1066
media_image1.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: EID et al. (U.S 2020/0312782 A1) and YOO (U.S 2012/0119370 A1).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Thanh Y. Tran/Primary Examiner, Art Unit 2817
June 25, 2026
Prosecution Insights