Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to Applicant’s Response to Election/Restriction Requirement received on January 19, 2026, regarding the application filed February 14, 2023.
Election/Restrictions
Applicant's election with traverse of Group I, corresponding to claims 1-13, in the reply filed on January 19, 2026 is acknowledged. The traversal is on the ground(s) that the search and examination of all the claims may be made without serious burden. This is not found persuasive because, as stated in the Requirement for Restriction filed January 5, 2026:
A serious search burden can be evidenced by separate classification, status, or field of search. See MPEP § 808.02. The inventions require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries). Group I would require a search in at least CPC H10D 30/701, along with a unique text search. Group II would not be searched as above, and would instead require a search in at least CPC G06N 3/063, along with a unique text search. The separate classification of Group I and Group II shows that each invention has attained recognition in the art as a separate subject for inventive effort, and therefore requires a separate field of search.
Applicant argues on pages 9-10 that the first claim of Group II (claim 14) includes a ferroelectric field effect transistor including all the limitations of the first claim of Group I (claim 1). However, this argument is not persuasive because Group II includes claims to a neural network apparatus which are absent from the claims of Group I and Group I includes claims which are absent from the claims of Group II. As explained above, each of Group I and Group II are classified separately and each of Group I and Group II requires a different field of search. A serious search burden on the examiner may be prima facie shown by appropriate explanation of separate classification, or separate status in the art, or a different field of search. Applicant has not provided sufficient showings or evidence to rebut this prima facie showing of serious search and/or examination burden. See MPEP 803. The requirement is still deemed proper and is therefore made FINAL.
Claims 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on January 19, 2026.
Claims 1-20 are pending, with claims 14-20 currently withdrawn from consideration.
Priority
Acknowledgment is made of Applicant's claim for foreign priority based on Korean Patent Application No. 10-2022-0021735, filed on Feb. 18, 2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 11, 2025 and December 11, 2025 have been placed in the application file and is being considered by the examiner.
Drawings
The drawings filed with the application on February 14, 2023 are accepted.
Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites “wherein a value obtained by dividing a greater work function, between the first work function of the first gate layer and the second work function of the second gate layer, by the other work function of the first gate layer or the second gate layer, is between 5 % to 100 %”. However, when dividing a greater number by a smaller number, the resulting value is greater than 100%, and therefore cannot be between 5% to 100%. it is unclear how the value obtained by dividing a greater number by a smaller number can be between 5% to 100%, as recited in claim 13.
Applicant’s specification appears to describe the value recited in claim 13 as “the work function difference between the first gate layer 142 a and the second gate layer 142 b may be about 5% to about 100% of a smaller work function between the work function of the first gate layer 142 a and the work function of the second gate layer 142 b,” [0070]. Note that difference is understood to refer to a value obtained by subtraction.
For examination purposes, claim 13 has been interpreted as “wherein a first value obtained by subtracting a lesser work function, between the first work function of the first gate layer and the second work function of the second gate layer, from the other work function of the first gate layer or the second gate layer, and dividing the first value by the lesser work function yields a resulting value between 5% to 100%.” This interpretation is supported by, for example, Applicant’s specification at paragraph 0070. This objection may be overcome by amending claim 13 to further clarify Applicant’s intended meaning, consistent with the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., US 2021/0217847 A1 (hereinafter Chang) in view of Bao et al., US 2020/0118888 A1 (hereinafter Bao).
Regarding claim 1, Chang discloses: A ferroelectric field effect transistor comprising: a source (Chang, FIGs. 1B, 1C, second epitaxial feature EP1*, connected to ground, [0032]); a drain (Chang, FIGs. 1B, 1C, first epitaxial feature EP1, connected to bit line “the epitaxial features may include SiP, SiGe, or other suitable source/drain material,” [0032]); a first channel connected to and between the source and the drain (Chang, FIG. 1C shows first semiconductor nanosheet 11A-X [the first channel] connected to and between second epitaxial feature EP1* [the source] and first epitaxial feature EP1 [the drain], [0021-0024]); a second channel connected to and between the source and the drain and spaced apart from the first channel (Chang, FIG. 1C shows second semiconductor nanosheet 11B-X [the second channel] connected to and between fourth epitaxial feature EP2* [the source] and third epitaxial feature EP2 [the drain] and spaced apart from first semiconductor nanosheet 11A-X [the first channel] along the secondary direction (SD), [0021-0024]; “the epitaxial features connected to the first end of the semiconductor nanosheets are connected, and each of the epitaxial features connected to the second end of the semiconductor nanosheets are connected,” [0033]); a ferroelectric layer at least partially covering the first channel and the second channel (Chang, FIGs. 1B, 1C, ferroelectric layer 12, “the semiconductor nanosheets [i.e., the first channel and the second channel] are surrounded by a ferroelectric layer 12,” [0026]); a first gate layer on the ferroelectric layer (Chang, FIGs. 1B, 1C, metal gate layer 13, [0027]; the first gate layer is shown as the portion of metal gate layer 13 surrounding first semiconductor nanosheet 11A-X [the first channel]), the first gate layer at least partially covering the first channel (Chang, see FIG. 1B, [0027]); a second gate layer on the ferroelectric layer, the second gate layer at least partially covering the second channel (Chang, FIGs. 1B, 1C, the second gate layer is shown as the portion of metal gate layer 13 surrounding second semiconductor nanosheet 11B-X [the second channel], [0027]); and a gate wiring electrically connected to the first gate layer and the second gate layer (Chang, see FIG. 1B, “the top surface of the metal gate layer 13 surrounding the first semiconductor nanosheet 11A-X [the first gate layer], the top surface of the metal gate layer 13 surrounding the second semiconductor nanosheet 11B-X [the second gate layer], and the top surface of the metal gate layer 13 surrounding the fourth semiconductor nanosheet 11C-X are continuously connected,” [0028]),
Chang is silent regarding: wherein the first gate layer includes a first metallic material having a first work function, the second gate layer includes a second metallic material having a second work function, and the second work function is different from the first work function.
However, Bao, in the same field of endeavor, teaches a gate formation scheme configured and arranged to provide separately tunable threshold voltages: wherein the first gate layer (Bao, FIG. 14 shows the first gate layer as the work function metal 604 on fin 222, above NVt1 220, [0051]) includes a first metallic material having a first work function (Bao, work function metal layer 604, [0051-0052]), the second gate layer (Bao, FIG. 14 shows the second gate layer as the work function metal 304A on fin 232, above NVt2 230, [0051]) includes a second metallic material having a second work function (Bao, work function metal layer 304A; Vt optimized by use of different work function metals, [0051-0052]), and the second work function is different from the first work function (Bao, “the use of different work function metals to form NVt1 220, NVt2 230 … is part of optimizing the Vt,” i.e., the second work function is different from the first work function, [0051]; Bao, claim 5). Bao teaches that “in non-planar, fully depleted channel architectures (e.g., FinFETs, gate-all-around (GAA) nanosheet transistors, and the like), providing multiple work function metals in the gate stacks is indispensable to achieving CMOS technology with multiple threshold voltages,” (Bao, [0034]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the ferroelectric field effect transistor as taught by Chang with the multiple work function metals in the gate stack, as taught by Bao, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Bao, to provide for multiple threshold voltages within the gate stack, thereby improving device performance and reliability.
Regarding claim 2, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1, wherein the first channel (Chang, FIG. 1C, first semiconductor nanosheet 11A-X) and the second channel (Chang, FIG. 1C second semiconductor nanosheet 11B-X) are electrically connected in parallel (Chang, see FIG. 1C, “Each of the epitaxial features connected to the first end of the semiconductor nanosheets are connected, and each of the epitaxial features connected to the second end of the semiconductor nanosheets are connected,” [0033]).
Regarding claim 3, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1, wherein at least one of the first metallic material or the second metallic material includes at least one of TiN, TiAlN, TaN, Co, WN, NbN, W, Mo, or Pt. (Chang, “the metal gate layer 13 includes conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or the like,” [0044]; Bao, suitable work function metals include platinum, cobalt, nickel, titanium, tantalum, aluminum, and combinations thereof, [0051]).
When a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298, 92 USPQ2d 1163, 1171 (Fed. Cir. 2009). The alternative elements taught by Chang in view of Bao include one or more of Applicant’s claimed alternative elements, for example: titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), cobalt (Co), platinum (Pt).
Regarding claim 4, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1, wherein the ferroelectric layer includes an oxide and a dopant, wherein the oxide includes at least one of Si, Al, Hf, or Zr (Chang, “ferroelectric layer 12 may include ferroelectric materials, such as hafnium oxide-based material,” [0026]), and the dopant is at least one of Si, Al, Y, La, Gd, Mg, Ca, Sr, Ba, Ti, Zr, Hf, N, MgZnO, AlScN, BaTiO3, Pb(Zr,Ti)O3, SrBiTaO7, or polyvinylidene fluoride (PVDF). (Chang, “the hafnium oxide-based material [the oxide] is doped with zirconium or silicon,” [0026]).
Regarding claim 5, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1 further comprising: a substrate (Chang, FIG. 1B, substrate 1, [0021]), wherein the source (Chang, FIGs. 1B, 1C, second epitaxial feature EP1*), the drain (Chang, FIGs. 1B, 1C, first epitaxial feature EP1), the first channel (Chang, FIG. 1C, first semiconductor nanosheet 11A-X), and the second channel (Chang, FIG. 1C, second semiconductor nanosheet 11B-X) are protruded from an upper surface of the substrate in a first direction (Chang, FIGs. 1B, 1C, show second epitaxial feature EP1* [the source], first epitaxial feature EP1 [the drain], first semiconductor nanosheet 11A-X [the first channel], and second semiconductor nanosheet 11B-X [the second channel] protruded from, i.e., extending from, upper surface of substrate 1 [the substrate] in the tertiary direction (TD) [the first direction], [0022]; Bao, FIG. 1 shows an analogous structure, the first direction shown as the Y-axis).
Regarding claim 6, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 5, wherein the first channel and the second channel extend in a second direction perpendicular to the first direction (Chang, FIGs. 1B, 1C show first semiconductor nanosheet 11A-X [the first channel] and second semiconductor nanosheet 11B-X [the second channel] extend along the primary direction (PD) [the second direction] perpendicular to the tertiary direction (TD) [the first direction], [0022]).
Regarding claim 7, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 6, wherein the first channel and the second channel are spaced apart from each other in a third direction perpendicular to the first direction and the second direction (Chang, FIGs. 1B, 1C show first semiconductor nanosheet 11A-X [the first channel] and second semiconductor nanosheet 11B-X [the second channel] spaced apart from each other along the secondary direction (SD) [the third direction] perpendicular to the tertiary direction (TD) [the first direction] and the primary direction (PD) [the second direction], [0022]).
Regarding claim 8, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1, further comprising: a substrate (Chang, FIG. 1B, substrate 1, [0021]), wherein the source (Chang, FIGs. 1B, 1C, second epitaxial feature EP1*) and the drain (Chang, FIGs. 1B, 1C, first epitaxial feature EP1) protrude from an upper surface of the substrate in a first direction (Chang, FIGs. 1B, 1C, show second epitaxial feature EP1* [the source] and the first epitaxial feature EP1 [the drain] protruded from, i.e., extending from, upper surface of substrate 1 [the substrate] in the tertiary direction (TD) [the first direction], [0022]), and the first channel and the second channel are spaced apart from the upper surface of the substrate in the first direction (Chang, FIG. 1B shows first semiconductor nanosheet 11A-X [the first channel] and second semiconductor nanosheet 11B-X [the second channel] spaced apart from the upper surface of substrate 1 in the tertiary direction (TD) [the first direction].
Regarding claim 9, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 8, wherein the first channel and the second channel extend in a second direction perpendicular to the first direction (Chang, FIGs. 1B, 1C show first semiconductor nanosheet 11A-X [the first channel] and second semiconductor nanosheet 11B-X [the second channel] extend along the primary direction (PD) [the second direction] perpendicular to the tertiary direction (TD) [the first direction], [0022]), and the first channel and the second channel are spaced apart from each other in at least one of the first direction or in a third direction perpendicular to the first direction and the second direction (Chang, FIGs. 1B, 1C show first semiconductor nanosheet 11A-X [the first channel] and second semiconductor nanosheet 11B-X [the second channel] spaced apart from each other along the secondary direction (SD) [the third direction] perpendicular to the tertiary direction (TD) [the first direction] and the primary direction (PD) [the second direction], [0022]).
Applicant is advised that should claim 9 be found allowable, claim 7 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Regarding claim 10, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 8, wherein the ferroelectric layer (Chang, FIG. 1B, ferroelectric layer 12) includes a first ferroelectric layer surrounding the first channel (Chang, FIG. 1B shows the first ferroelectric layer as the portion of ferroelectric layer 12 surrounding first semiconductor nanosheet 11A-X [the first channel], [0026]) and a second ferroelectric layer surrounding the second channel (Chang, FIG. 1B shows the second ferroelectric layer as the portion of ferroelectric layer 12 surrounding second semiconductor nanosheet 11B-X [the second channel], [0026]).
Regarding claim 11, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 10, wherein the first gate layer surrounds the first ferroelectric layer (Chang, FIGs. 1B, 1C, the first gate layer is shown as the portion of metal gate layer 13 surrounding first semiconductor nanosheet 11A-X [the first channel]), and the second gate layer surrounds the second ferroelectric layer (Chang, FIGs. 1B, 1C, the second gate layer is shown as the portion of metal gate layer 13 surrounding second semiconductor nanosheet 11B-X [the second channel]; “each of the ferroelectric layer 12 surrounding the first semiconductor nanosheet 11A-X [i.e., the first ferroelectric layer surrounding the first channel], the second semiconductor nanosheet 11B-X [i.e., the second ferroelectric layer surrounding the second channel] … is surrounded by a metal gate layer 13,” [0027]).
Regarding claim 12, Chang in view of Bao teaches: The ferroelectric field effect transistor of claim 1, further comprising: a third channel (Chang, FIGs. 1B, 1C, fourth semiconductor nanosheet 11C-X [the third channel], [0021-0024] spaced apart from the first channel and the second channel (Chang, see FIGs. 1B, 1C, [0021-0024]); and a third gate layer on the ferroelectric layer, the third gate layer at least partially covering the third channel (Chang, FIGs. 1B, 1C, the third gate layer is shown as the portion of metal gate layer 13 surrounding ferroelectric layer 12 [the ferroelectric layer] on fourth semiconductor nanosheet 11C-X [the third channel], [0027]; Bao, FIG. 14 shows the third gate layer as the work function metal 602A on fin 252, above PVt 1 250, [0051]) and including a third metallic material having a third work function (Bao, work function metal layer 602A, [0051-0052]), the third work function different from the first work function and the second work function (Bao, “the first, second, third and fourth work function metal stacks each comprises a different threshold voltage,” claim 15), wherein the gate wiring electrically connects the first gate layer, the second gate layer, and the third gate layer to each other (Chang, see FIG. 1B, “the top surface of the metal gate layer 13 surrounding the first semiconductor nanosheet 11A-X [the first gate layer], the top surface of the metal gate layer 13 surrounding the second semiconductor nanosheet 11B-X [the second gate layer], and the top surface of the metal gate layer 13 surrounding the fourth semiconductor nanosheet 11C-X [the third gate layer] are continuously connected,” [0028]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Bao, and further in view of Pesic et al, US 2021/0350219 A1 (hereinafter Pesic).
Regarding claim 13, insofar as the claim can be understood in view of the claim objections above, Chang in view of Bao teaches nearly every element of claim 13 but is silent regarding: wherein a first value obtained by subtracting a lesser work function, between the first work function of the first gate layer and the second work function of the second gate layer, from the other work function of the first gate layer or the second gate layer, and dividing the first value by the lesser work function yields a resulting value between 5% to 100%.
However, Pesic, in the same field of endeavor, teaches the use of different materials such that there is a work function differential that can be used for tuning the read-voltage and ON/OFF ratio of the device; Pesic provides examples of the different work functions as 4.6 eV and 5.6 eV (Pesic, [0078]). When these numbers are used in Applicant’s claim 13, as interpreted above, the resulting value is within Applicant’s claimed range:
5.6
-
4.6
4.6
=
21.7
%
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Chang in view of Bao with the teachings of Pesic, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Pesic, for tuning the read-voltage and ON/OFF ratio of the device, thereby improving device performance and reliability.
Conclusion
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/D.L.N./Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899