DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/10/2026 has been entered.
Allowable Subject Matter
Claim 15 allowed. Accordingly dependent claim 16-20 are allowable because of dependency from claim 15.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGpub: 2021/0358694 A1), herein after Lee, in view of HOU et al. (US PGpub: 2018/0151755 A1 A1), herein after HOU.
Regarding claim 1, Lee teaches a semiconductor device comprising:
a semiconductor substrate (FIG. 3, 400) including a dopant having a polarity (Paragraph [0078]);
a channel layer (CR) on the semiconductor substrate and including majority carriers having a polarity opposite a polarity of the semiconductor substrate (Paragraph [0078]-[0079]);
a ferroelectric layer (100) on the channel layer; and
a gate (330 and 200 constitutes gate structure with gate electrode & gate dielectric) on the ferroelectric layer (100).
the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn (Claim 20).
Lee does not explicitly teach wherein a doping concentration of the semiconductor substrate is less than a concentration of the majority carriers of the channel layer.
However, it is actually adjustable based on control voltage. HOU teaches a doping concentration of the semiconductor substrate is less than a concentration of the majority carriers of the channel layer (FIG. 21 and FIG. 22 description. explain how charge trapping works. Concentration of the carriers can be controlled using charge trapping) .
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Lee’s semiconductor device with other teaching from HOU so that high electron mobility (μ.sub.e) value, which is within a range of about 50-1000 cm.sup.2/V-sec or even higher. It is understood that the bulk silicon, when cut to a low thickness (e.g., about 2 nm) comparable with a typical thickness of a 2D material film, can have its mobility degraded drastically.
Additional rejection (claim1):
Claim 1-14 are rejected under 35 U.S.C. 103 as being anticipated by MATSUURA et al. (Foreign Patent: JP2002-151599 A),in view of HOU et al. (US PGpub: 2018/0151755 A1 A1), herein after HOU (or, in view of Lee).
a semiconductor device (Paragraph [0001]) comprising:
a semiconductor substrate including a dopant having a polarity (A semiconductor substrate (1) having P-type impurities in Paragraph [0076] and FIGS. 1, 2, and 22);
a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite a polarity of the semiconductor substrate (A channel layer (5N), which is formed on the semiconductor substrate (1) and includes N-type impurities in Paragraph [0076] and FIGS. 1, 2, 19, and 22);
a ferroelectric layer on the channel layer (A gate insulating film (3), which is a ferroelectric film formed on the channel layer (5N) in Paragraph [0075] and FIGS. 1, 2, and 22); and
a gate on the ferroelectric layer (A gate electrode (4), which is formed on the gate insulating film (3) that is a ferroelectric film and is a metal film in Paragraph [0075] and FIGS. 1, 2, and 22);
wherein a doping concentration of the semiconductor substrate is less than a concentration of the majority carriers of the channel layer (the impurity concentration of the N-type channel layer (5N) is equal to or higher than the impurity concentration of the semiconductor substrate (1) (i.e., the impurity concentration of the P-type well layer PWL) in Paragraph [0076] and FIGS. 1, 2, and 22) .
MATSUURA does not explicitly teach the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn
Lee teaches the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn (Claim 20). HOU also teaches in Paragraph [0036]-[0042]), wherein the channel layer has a thickness of about 5 nm or less and charge trapping layer is an oxide of Ga.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use MATSUURA’s semiconductor device with other teaching from Lee so that the device its mobility can be improved
Regarding claim 2, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the doping concentration of the semiconductor substrate is about 1016 to about 1019 cm-3. (HOU Paragraph [0034]-[0036]. Also, this range can be manipulated to fit the device requirements)
Regarding claim 3, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the concentration of the majority carriers of the channel layer is about 1018 to about 1021 cm-3 (HOU Paragraph [0034]-[0036]. Also, this range can be manipulated to fit the device requirements).
Regarding claim 4, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the channel layer has a thickness of about 5 nm or less (HOU Paragraph [0036]-[0037]).
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PGpub: 2021/0358694 A1), herein after Lee, in view of HOU et al. (US PGpub: 2018/0151755 A1), herein after HOU.
Regarding claim 5, Lee teaches (in view of HOU) the semiconductor device of claim 1,
the gate (330 and 200 constitutes gate structure with gate electrode & gate dielectric) directly contacts the ferroelectric layer (100), the ferroelectric layer is between the gate and the channel layer (CR),
the semiconductor substrate includes a group IV semiconductor material (Paragraph [0052] on HOU et al).
Alternatively, Van Houdt et al (US: 20190198638 ) teaches gate (104) directly contacts ferroelectric layer (102).
Regarding claim 6, Lee teaches the semiconductor device of claim 1, wherein the channel layer includes an oxide semiconductor or a two-dimensional (2D) semiconductor material (HOU Paragraph [0036]).
Regarding claim 7, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the dopant in the semiconductor substrate is a p-type dopant (HOU Paragraph [0035]).
Regarding claim 8, Lee teaches the semiconductor device of claim 1, wherein the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn (Claim 20). This well known in the industry as taught in Pillarisetty et al. (US 20200020805 A1) in Paragraph [0027]-[0031].
Regarding claim 9, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the channel layer includes graphene or transition metal dichalcogenide (TMD) (HOU Paragraph [0036]).
Regarding claim 10, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the dopant in the semiconductor substrate is an n-type dopant (Paragraph [0034-[0036], [0052], [0078]).
Regarding claim 11, Lee teaches (in view of HOU and known arts) the semiconductor device of claim 1, wherein the channel layer includes an oxide of at least one of Sn and Ni . (HOU Paragraph [0036]). This well known in the industry as taught in Pillarisetty et al. (US 20200020805 A1) in Paragraph [0027]-[0031] and also in Huang et al. (Paragraph [0048)
Regarding claim 12, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the channel layer includes black phosphorous (HOU Paragraph [0036]). This well known in the industry as taught in Pillarisetty et al. (US 20200020805 A1) in Paragraph [0027]-[0031] and also in Huang et al .(Paragraph [0048)
Regarding claim 13, Lee teaches (in view of HOU) the semiconductor device of claim 1, wherein the ferroelectric layer includes at least one of hafnium oxide, zirconium oxide, and hafnium-zirconium oxide (Paragraph [0056]).
Regarding claim 14, Lee (in view of HOU) teaches the semiconductor device of claim 1, wherein the channel layer, the ferroelectric layer, and the gate sequentially surround the semiconductor substrate (FIG. 3).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over MATSUURA, in view of HOU et al. (US PGpub: 2018/0151755 A1 A1), herein after HOU (or, in view of Lee).
Regarding claim 21, MATSUURA teaches a semiconductor device comprising:
a semiconductor substrate including a dopant having a polarity (A semiconductor substrate (1) having P-type impurities in Paragraph [0076] and FIGS. 1, 2, and 22);
a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite a polarity of the semiconductor substrate (A channel layer (5N), which is formed on the semiconductor substrate (1) and includes N-type impurities in Paragraph [0076] and FIGS. 1, 2, 19, and 22);
a ferroelectric layer on the channel layer (A gate insulating film (3), which is a ferroelectric film formed on the channel layer (5N) in Paragraph [0075] and FIGS. 1, 2, and 22); and
a gate on the ferroelectric layer (A gate electrode (4), which is formed on the gate insulating film (3) that is a ferroelectric film and is a metal film in Paragraph [0075] and FIGS. 1, 2, and 22);
wherein a doping concentration of the semiconductor substrate is less than a concentration of the majority carriers of the channel layer (the impurity concentration of the N-type channel layer (5N) is equal to or higher than the impurity concentration of the semiconductor substrate (1) (i.e., the impurity concentration of the P-type well layer PWL) in Paragraph [0076] and FIGS. 1, 2, and 22) .
wherein the channel layer has a thickness of about 5 nm or less, the semiconductor substrate includes a group IV semiconductor material, the dopant in the semiconductor substrate is a p-type dopant (Paragraph [0076] and FIGS. 1, 2, and 22),
MATSUURA does not explicitly teach the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn
Lee teaches the channel layer includes an oxide of at least one of In, Ga, Zn, and Sn (Claim 20). HOU also teaches in Paragraph [0036]-[0037]), wherein the channel layer has a thickness of about 5 nm or less.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use MATSUURA’s semiconductor device with other teaching from Lee so that the device its mobility can be improved
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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