Office Action Predictor
Last updated: April 17, 2026
Application No. 18/169,290

SEMICONDUCTOR STORAGE DEVICE, PRINTING APPARATUS, AND WRITE CONTROL METHOD OF SEMICONDUCTOR STORAGE DEVICE

Non-Final OA §102§103
Filed
Feb 15, 2023
Examiner
KEBEDE, BROOK
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
canon Kabushiki Kaisha
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
93%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
887 granted / 1000 resolved
+20.7% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
1028
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
33.9%
-6.1% vs TC avg
§102
31.0%
-9.0% vs TC avg
§112
11.6%
-28.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1000 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Species I, i.e., Claims 1-8, in the reply filed on November 24, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 9-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 24, 2025. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 3 -5 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Tran et al. (US 6,434,048). Re Claim 1, Tran et al. disclose a semiconductor storage device configured to control writing in a memory unit including an anti-fuse element, (abstract – memory cell, figure 3a shows the control device 355 that controls the writing, col 5 lines 22-35) the device comprising: a comparison unit (figure 3a comparator 330) configured to compare, with a reference voltage (Vref), a voltage generated across a resistor element connected in series with a power supply line used to energize the anti-fuse element (310 is the power supply unit to the anti-fuse memory cell 210 [col 4 lines 10-14], wherein the power supply unit 310 is connected in series with the resistor R1, col 4 lines 41-55); and a control unit configured to, in writing in the memory unit, control writing in the anti-fuse element of the memory unit based on an output of the comparison unit (control device 355, depending on the voltage output of the comparator in a write operation, the pulse train is discontinued to the anti-fuse elements - col 4 lines 51-55 and col 5 lines 27-33). Re Claim 3, as applied to claim 1 above, Tran et al. disclose all the claimed limitations including a power supply control unit configured to, in writing in the memory unit (Col 2, lines 63 – Col 3, line 9), apply a write voltage to the power supply line used to energize the anti-fuse element (Fig. 3B and Col 5, lines 44-27). Re Claim 4, as applied to claim 1 above, Tran et al. disclose all the claimed limitations including wherein in writing in the memory unit (Col 2, lines 63 – Col 3, line 9), the control unit performs writing in the anti-fuse element by applying a pulse signal to the anti-fuse element (Fig. 3B and Col 5, lines 44-27). Re Claim 5, as applied to claim 4 above, Tran et al. disclose all the claimed limitations including wherein when the output of the comparison unit indicates that writing in the anti-fuse element of the memory unit is complete, the control unit terminates writing in the anti-fuse element (control device 355, depending on the voltage output of the comparator in a write operation, the pulse train is discontinued to the anti-fuse elements - col 4 lines 51-55 and col 5 lines 27-33) after further applying the pulse signal to the anti-fuse element for a predetermined time (see Fig. 3B and Abstract). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US 6,434,048) in view of PARK et al. (US 2012/0014156). Re Claim 6, as applied to claim 1 above, Tran et al. disclose all the claimed limitations except wherein a current supply side of the power supply line is grounded via an ESD protection element. PARK et al. disclose a current supply side of the power supply line is grounded via an ESD protection element (see Page 3, Paragraph [0057] i.e., to reduce high voltage components and/or high current components). Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to provide Tran et al. reference with ESD as taught by PARK et al. in order to reduce high voltage components and/or high current components. Allowable Subject Matter Claims 2, 7 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Perner et al. (US 6,501,697), Allen et al. (US 2008/0158933) and Taigor et al. (2016/0179113) also disclose similar inventive subject matter. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BROOK KEBEDE/ Primary Examiner, Art Unit 2894 /BK/ January 28, 2026
Read full office action

Prosecution Timeline

Feb 15, 2023
Application Filed
Jan 29, 2026
Non-Final Rejection — §102, §103
Apr 07, 2026
Response Filed

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
93%
With Interview (+4.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1000 resolved cases by this examiner. Grant probability derived from career allow rate.

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