DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “wherein a plurality of the photoelectric conversion parts is provided”. The language is confusing in regards to the antecedent. It is unclear whether the limitation may be satisfied by a plurality of light detectors or whether other elements of the light detector must remain singular while only the photoelectric conversion parts are in plural form.
Claim 5 further recites “the plurality of photoelectric conversion parts is located above one of the voids”. The language is further confusing. It is unclear how many voids are required or allowed and how many photoelectric conversion parts must or may be above what number of voids. Due to this combination of confusing elements, the Examiner finds the scope of the claim to be indefinite, rather than merely broad.
The Examiner suggests language in the independent claim such as “one or more”, followed by dependent claim language specifying that “one or more” is a plurality along with any additional clarification that may be appropriate. Claim 5 will not be examined as is for prior art.
Claim 18 recites the limitation " the avalanche photodiode” according to claim 17. There is insufficient antecedent basis for this limitation in the claim. Claim 17 does not require an avalanche photodiode since it may be satisfied by a p-i-n diode not being an avalanche diode.
For the purposes of examination, the claim will be interpreted for the case where claim 17 is satisfied by an avalanche photodiode.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 6, 11, 14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang).
Regarding claim 1, Wang discloses a light detector (in particular example, Figs 84A,84B,85; ¶ [0517-531]; entire document), comprising:
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a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD {microstructure-enhanced photodetector/avalanche microstructured photodiode}; ¶ [0038-39, 0517]),
the photoelectric conversion part including
a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) of a first conductivity type, and
a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]) of a second conductivity type,
the substrate including
a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer, and
a trench (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]) surrounding the photoelectric conversion part, a lower end of the trench being positioned in the second semiconductor layer,
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Regarding claim 2, Wang discloses the detector according to claim 1, wherein the void (8490; Fig 84B) extends through the insulating layer (BOX 8408; ¶ [0517]).
Regarding claim 6, Wang discloses the detector according to claim 1, wherein
the second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B) further includes:
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (connecting well 8006, which is N {plus} type; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) positioned above the third semiconductor region, the fourth semiconductor region being of the second conductivity type and being electrically connected with the third semiconductor region (¶ [0505]),
the trench (8462; Fig 84B) is positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region is positioned below the trench (as shown in Fig 84B), and
the third semiconductor region electrically connects the fourth semiconductor region and the photoelectric conversion part (as shown in Figs 80,84B; ¶ [0505])).
Regarding claim 11, the Examiner interprets that MSPD/MSAPD 9810 of Fig 98 (¶ [0582-583]) may be any number of MSPD/MSAPD photodetectors described throughout the disclosure, Wang having indicated no limitation and disclosing only that 9810 may be formed with or without superstrates (¶ [0582]). That is, 9810 is interpreted to be a genus which includes the species photodetectors cited with reference to Fig 84B. The Examiner therefore is citing the necessary details from Fig 84B in combination with Fig 98 which lacks those details in regards to photodetectors 9810.
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Wang discloses a light detector (in particular example, Figs 84A,84B,85,89; ¶ [0517-531, 0582-583]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the substrate including
a light-receiving region (the region vertically above 9860 in Fig. 98, comprising 9810) including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]), the photoelectric conversion part including a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) and a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]), the first semiconductor region being of a first conductivity type, the second semiconductor region being of a second conductivity type, a first trench (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]) being provided in the light-receiving region, and
a transistor region (the region including 9860 and vertically below in Fig. 98, comprising CMOS/BiCMOS ASICs) arranged with the light-receiving region in a direction perpendicular to a first direction (into the page, Fig 98; vertical direction, Fig 84B), the first direction being from the first semiconductor layer toward the second semiconductor layer, the transistor region including a transistor (CMOS/BiCMOS ASICs include a transistor),
the transistor region including a second trench (9860; Fig 98; ¶ [0582]) located between the light-receiving region and at least a portion of the transistor,
in the light-receiving region, the second semiconductor layer further including
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (connecting well 8006, which is N {plus} type; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) positioned above the third semiconductor region and electrically connected with the third semiconductor region (¶ [0505]), the fourth semiconductor region being of the second conductivity type,
the first trench (8462) being positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region (8424) being positioned below the first trench, the third semiconductor region electrically connecting the photoelectric conversion part and the fourth semiconductor region (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Regarding claim 14, Wang discloses the light detector of claim 11, wherein the substrate includes a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned between the photoelectric conversion part and a portion of the first semiconductor layer.
Regarding claim 17, Wang discloses the light detector of claim 1, wherein the photoelectric conversion part is a p-i-n diode or an avalanche photodiode (for example, avalanche photodiode {MSAPD}, as applied to claim 1).
Regarding claim 18, Wang discloses the light detector of claim 17, wherein the avalanche photodiode operates in a Geiger mode (the MSAPD can be operated in Geiger-counter mode; ¶ [0602]).
Regarding claim 19, Wang discloses a light detection system (LIDAR chip; ¶ [0534,0256]), comprising: the detector according to claim 1; and a distance measuring circuit calculating a time-of-flight of light based on an output signal of the detector (¶ [0256]).
Regarding claim 20, Wang discloses a lidar device (see Fig 8; ¶ [0205]), comprising: a light source irradiating light on an object (vertical cavity emitting laser {VCSEL}; ¶ [0256]) and the light detection system according to claim 19, the light detection system detecting light reflected by the object (¶ [0256]).
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang) Second Interpretation
Regarding claim 1 (Second Interpretation), Wang discloses a light detector (in particular example, Figs 84A,84B,85; ¶ [0517-531]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the photoelectric conversion part including
a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) of a first conductivity type, and
a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]) of a second conductivity type,
the substrate including
a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer, and
a trench (connecting well 8006 {0505,0510}; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) surrounding the photoelectric conversion part, a lower end of the trench being positioned in the second semiconductor layer,
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8006 {unlabeled; see Fig 80}; Fig 84B).
Regarding claim 10, Wang discloses the detector according to claim 1 (Second Interpretation), further comprising:
a conductive part located inside the trench (as applied to claim 1),
the second semiconductor layer further including a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) of the second conductivity type positioned above the insulating layer,
a portion of the third semiconductor region being positioned under a lower end of the conductive part and electrically connecting the conductive part and the photoelectric conversion part (as shown in Figs 80,84B; ¶ [0505]) .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 9, 12, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang).
Regarding claim 7, Wang discloses the detector according to claim 6, but does not disclose in the same embodiment wherein a plurality of the photoelectric conversion parts is provided, the plurality of photoelectric conversion parts includes mutually-adjacent photoelectric conversion parts, and the fourth semiconductor region surrounds the mutually-adjacent photoelectric conversion parts.
However, in another embodiment, Wang discloses a detector chip 9800 comprising an array of light detectors 9810 arranged in an grid pattern (two rows by four columns, for example; ¶ [0582]). It would have been obvious to a person having ordinary skill in the art to have combined the embodiment of claim 1 with the embodiment of detector chip 9800 such that the light detector of claim 1 (Figs 84B,85) is used in place of each 9810. In this configuration, each of the plurality of photoelectric conversion parts is surrounded by a fourth semiconductor region (connecting well 8006; Figs 80,84B {unlabeled in 84B, beneath Cat}; as applied to claim 6). When arranged in a grid pattern, the plurality of light detectors comprises mutually-adjacent photoelectric conversion parts, which are each interior to the outermost portions of the (plurality of) fourth semiconductor region(s); the fourth semiconductor region thereby surrounding the mutually adjacent-photoelectric conversion parts (interpreting “surrounds” in view of page 34, lines 10-21 of the disclosure). One would have been motivated to combine the embodiments in order to take advantage of the low reverse bias avalanche voltage and high quantum efficiency (QE; ¶ [0527]) of the claim 1 light detector with the integrated ASIC functionality (¶ [0582]) of detector chip 9800. One would have had a reasonable expectation of success because of Wang disclose an MSAPD type device in both embodiments.
Regarding claim 9, the Wang discloses the light detected for claim 6, but does not disclose wherein the fourth semiconductor region is surrounded with a trench.
However, elsewhere in the disclosure Wang discloses that isolation trenches can surround an entire light detector (Fig 63C; ¶ [0441]). It would have been obvious to a person having ordinary skill in the art that an isolation trench may surround the light detector of claim 6, thereby surrounding the fourth semiconductor region comprised therein. One may have been motivated to do this when monolithically integrating the light detector with other circuits (TIA/ASIC’s; Fig 63C; ¶ [0441]) in order to fully isolate the light detector from the other circuits. One would have been motivated to do this because of Wang’s disclosure and because such isolation is well-known in the art.
Regarding claim 12, Wang discloses the light detector of claim 11, but does not disclose wherein a lower end of the second trench reaches the insulating layer. However, this would have been obvious to a person having ordinary skill in the art to prevent a leakage path beneath the second trench between the light-receiving region and the transistor region, and thereby provide electrical isolation therebetween (Wang; ¶ [0582]). One would have been motivated to do this, with a reasonable expectation of success, because requirements for a trench to provide electrical isolation is well-known in the art, and because Wang discloses this configuration in other embodiments (for example, in regards to trench 4462; Fig 46; ¶ [0332,0341]).
Regarding claim 15, Wang discloses the light detector of claim 11, but does not disclose wherein the substrate includes a void positioned between the transistor and a portion of the first semiconductor layer. However, Wang discloses elsewhere in the disclosure that all MSPD,MSAPD, monolithic integration with CMOS, BiCMOS mentioned in the application can be fabricated on a SOH (silicon on holes) wafer (Fig 6E; ¶ [0198]) wherein CMOS, BiCMOS layers can be fabricated on the holes (voids). Accordingly, it would have been obvious to a person having ordinary skill in the art to have used a hole containing layer such as that of Fig 6E of Wang as the first semiconductor layer of claim 11, wherein the transistor is above a void of the hole containing layer, having a portion of the first semiconductor layer below the void. One would have been motivated to do this at least as an alternate layer, and would have had a reasonable expectation of success because Wang discloses the SOH wafer as an alternate of SOI and bulk wafers applicable to detectors of the disclosure (¶ [0198]).
Regarding claim 16, Wang discloses the light detector of claim 11, but does not disclose further comprising: a conductive layer, the first semiconductor layer being located between the conductive layer and the insulating layer.
However, elsewhere in the disclosure (¶ [0463]) Wang discloses that a through silicon via (TSV) may be used to connect front side electrodes (anode, cathode {¶ [0458]) to the bottom substrate for a solder bump connection at the backside. Accordingly, it would have been obvious to a person having ordinary skill in the art that the TSV would need to connect to a conductive layer (comprising solder bump pads, for example) on the backside and to form a conductive layer on the light detector of claim 11 satisfying claim 16 in this manner. One would have been motivated to do this in order to satisfy particular packaging connection requirements for a particular application, and would have had a reasonable expectation of success because it is well-known in the art.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang). (Second Interpretation)
Regarding claim 11 (Second Interpretation), the Examiner interprets that MSPD/MSAPD 9810 of Fig 98 (¶ [0582-583]) may be any number of MSPD/MSAPD photodetectors described throughout the disclosure, Wang having indicated no limitation and disclosing only that 9810 may be formed with or without superstrates (¶ [0582]). That is, 9810 is interpreted to be a genus which includes the species photodetectors cited with reference to Fig 84B. The Examiner therefore is citing the necessary details from Fig 84B in combination with Fig 98 which lacks those details in regards to photodetectors 9810.
Wang discloses a light detector (in particular example, Figs 84A,84B,85,89; ¶ [0517-531, 0582-583]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the substrate including
a light-receiving region (the region vertically above 9860 in Fig. 98, comprising 9810) including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]), the photoelectric conversion part including a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) and a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]), the first semiconductor region being of a first conductivity type, the second semiconductor region being of a second conductivity type, a connecting well (8006; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) being provided in the light-receiving region, and
a transistor region (the region including 9860 and vertically below in Fig. 98, comprising CMOS/BiCMOS ASICs) arranged with the light-receiving region in a direction perpendicular to a first direction (into the page, Fig 98; vertical direction, Fig 84B), the first direction being from the first semiconductor layer toward the second semiconductor layer, the transistor region including a transistor (CMOS/BiCMOS ASICs include a transistor),
the transistor region including a second trench (9860; Fig 98; ¶ [0582]) located between the light-receiving region and at least a portion of the transistor,
in the light-receiving region, the second semiconductor layer further including
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (8426, which is N {minus} type, outside the photoelectric conversion part {on a side opposite the connecting well from the photoelectric conversion part}; Fig 84B; ¶ [0525]) positioned above the third semiconductor region and electrically connected with the third semiconductor region, the fourth semiconductor region being of the second conductivity type,
the connecting well being positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region (8424) being positioned below the connecting well, the third semiconductor region electrically connecting the photoelectric conversion part and the fourth semiconductor region (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Wang does not disclose, in regards to Fig 84B, that the connecting well is a trench. However, he discloses elsewhere in the disclosure that a connecting well may be a trench with oxide on its sidewalls and a conductive material at its center (¶ [0550] with reference to Fig 89.) Accordingly, it would have been obvious to a person having ordinary skill in the art to have used a trench such as that of Fig 89 and associated description for the connecting well (the first trench) of claim 11. One may have been motivated to do this a number of reasons known in the art including the higher conductivity provided by using a metal for the conductive material rather than a semiconductor (Wang; ¶ [0550]). One would have had a reasonable expectable of success because Wang has disclosed this as an alternate to a highly doped connecting well (¶ [0550]).
Regarding claim 13, Wang discloses the light detector of claim 11 (Second Interpretation), wherein a conductive part is located inside at least a portion of the first or second trench (the conductive material of the first trench, as applied to claim 11).
Allowable Subject Matter
Claims 3,4, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein a portion of the insulating layer is located between the first semiconductor layer and the photoelectric conversion part, and the void is located between the photoelectric conversion part and the portion of the insulating layer.”
Regarding claim 4, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the void is positioned between the first semiconductor layer and the photoelectric conversion part, and a portion of the insulating layer is located between the void and the photoelectric conversion part.”
Regarding claim 8, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the fourth semiconductor region does not surround the photoelectric conversion part.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakanishi Kentaro et al. (JP-2020/102498-A)
Moussy; Norbert et al. (US 2021/0159257)
Moussy; Norbert (US 2019/0198701)
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817