DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed April 14, 2026 has been entered. Applicant' s amendment to claim 5 has been considered, and the 35 U.S.C. 112(b) rejection is hereby withdrawn. The 35 U.S.C. 112(b) rejection of claim 18 from the prior office action remains; the rejection has been updated with an exemplary remedy that may be considered.
Claims 1-13, 15-20 and newly added claims 21-22 are pending in the application.
Response to Arguments
Applicant' s arguments, see pages 11-13, filed April 14, 2026, with respect to the rejections of claims 1-2, 6, 10-11, 14, and 17-20 under 35 U.S.C 102(a)(1) and to the rejections of claims 7, 9, 12-13, and 15-16 under 35 U.S.C 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of additional embodiments from the same prior art.
In addition, although claim 4 was indicated in the prior office action as including allowable subject matter, the claim has been reconsidered in view of the additional embodiments and rejected under 35 U.S.C 103.
Please see the claim rejections below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation " the avalanche photodiode” according to claim 17. There is insufficient antecedent basis for this limitation in the claim. Claim 17 does not require an avalanche photodiode since it may be satisfied by a p-i-n diode not being an avalanche diode. The claim may be re-written in another form to overcome this rejection; for example: “The detector according to claim 1, wherein the photoelectric conversion part is an avalanche photodiode, wherein the avalanche photodiode operates in a Geiger mode.”
For the purposes of examination, the claim will be interpreted for the case where claim 17 is satisfied by an avalanche photodiode.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-7, 9, 12 and 15-22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang).
Regarding claim 1, Wang discloses a light detector (in particular example, Figs 84A,84B,85; ¶ [0517-531]; entire document), comprising:
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a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD {microstructure-enhanced photodetector/avalanche microstructured photodiode}; ¶ [0038-39, 0517]),
the photoelectric conversion part including
a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) of a first conductivity type, and
a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]) of a second conductivity type,
the substrate including
a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer, and
a trench (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]) surrounding the photoelectric conversion part, a lower end of the trench being positioned in the second semiconductor layer,
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Wang does not disclose, in the embodiment of Figs 84B,85, the substrate having no hole extending from an upper surface of the substrate to the void, because holes 8460 (Fig 84B; ¶ [0517,0525]) extends from an upper surface of a substrate to the void, the holes having enabled the formation of the void. However, Wang discloses another method of removing oxide from the BOX layer to enable forming a higher reflection semiconductor-air interface (which is provided in Fig 84B by the semiconductor-air interface of the void 8490; ¶ [0518]). Wang discloses the method of forming the interface by forming holes (1914; Figs 19A-19D; ¶ [0242-244]; {see also 532; Figs 5,6A-6D; ¶ [0196-8]}; see the included figures below) in a BOX layer, including bonding a second substrate (1906; Figs 19C-19D; ¶ [0242]) onto a first substrate (1902; Figs 19A-19D; ¶ [0242]) which has had a void (holes/voids 1914; Figs 19B-19D; ¶ [0242]) patterned into its surface (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the BOX/void structure 1904 of Figs 19C-D for the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of providing the more highly reflecting interface by including the lower refractive index air (hole), since each of the structures is disclosed as being capable of serving the same purpose (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
Regarding claim 2, Wang discloses the detector according to claim 1, wherein the void extends through the insulating layer (analogous to 1914 of Figs 19A-B extending through BOX 1904, as applied to claim 1 in place of 8490 through BOX 8408 of Fig 84B.)
Regarding claim 4, Wang discloses a light detector (in particular example, Figs 84A,84B,85; ¶ [0517-531]; entire document), comprising:
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a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD {microstructure-enhanced photodetector/avalanche microstructured photodiode}; ¶ [0038-39, 0517]),
the photoelectric conversion part including
a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) of a first conductivity type, and
a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]) of a second conductivity type,
the substrate including
a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer, and
a trench (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]) surrounding the photoelectric conversion part, a lower end of the trench being positioned in the second semiconductor layer,
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Wang does not disclose wherein the void is positioned between the first semiconductor layer and the photoelectric conversion part, and a portion of the insulating layer is located between the void, and the photoelectric conversion part.
However, Wang discloses another method of providing a void, wherein the void is positioned between the first semiconductor layer and the photoelectric conversion part, and a portion of the insulating layer is located between the void and the photoelectric conversion part. In Fig 84B, the void 8490 is formed by removing oxide from BOX layer 8408 through holes 8460 (¶ [0517,0525]). Wang discloses another method of forming a void (holes/voids 1914; Figs 19A-19D; ¶ [0242-244]; {see also 532; Figs 5,6A-6D; ¶ [0196-8]}; see the included figures below) in a BOX layer, including bonding a second substrate (1906; Figs 19C-19D; ¶ [0242]) onto a first substrate (1902; Figs 19A-19D; ¶ [0242]) which has had a void (1914; Figs 19B-19D; ¶ [0242]) patterned into its surface (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the BOX/void structure 1904 of Figs 19C-D for the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of providing a more highly reflecting interface by including lower refractive index air in the layer, since each of the structures is disclosed as being capable of serving the same purpose of enabling a reflective interface (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
As shown in Figs 19C-D, a portion of insulating layer 1904 is located between the void 1914 and the overlying structure, which as described above comprises the photoelectric conversion part.
Regarding claim 5, Wang discloses the detector according to claim 1, but does not disclose wherein the second semiconductor layer further includes another photoelectric conversion part, the another photoelectric conversion part includes another first semiconductor region of the first conductivity type and another second semiconductor region of the second conductivity type, and the photoelectric conversion part and the another photoelectric conversion part are positioned above the void.
However, in another embodiment, Wang discloses a detector chip 9800 comprising an array of light detectors 9810 arranged in an grid pattern (one row by four columns, for example; Fig 98; ¶ [0582]). It would have been obvious to a person having ordinary skill in the art to have combined the embodiment of claim 1 with the embodiment of detector chip 9800 such that the light detector of claim 1 (Figs 84B,85) is used in place of each 9810, which would satisfy the limitations of claim 5, since the BOX/void structure 1904 is continuous across the bonded wafers on either side of it. One would have been motivated to combine the embodiments in order to take advantage of the low reverse bias avalanche voltage and high quantum efficiency (QE; ¶ [0527]) of the claim 1 light detector with the integrated ASIC functionality (¶ [0582]) of detector chip 9800. One would have had a reasonable expectation of success because of Wang disclose an MSAPD type device in each embodiments.
Regarding claim 6, Wang discloses the detector according to claim 1, wherein
the second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B) further includes:
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (connecting well 8006, which is N {plus} type; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) positioned above the third semiconductor region, the fourth semiconductor region being of the second conductivity type and being electrically connected with the third semiconductor region (¶ [0505]),
the trench (8462; Fig 84B) is positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region is positioned below the trench (as shown in Fig 84B), and
the third semiconductor region electrically connects the fourth semiconductor region and the photoelectric conversion part (as shown in Figs 80,84B; ¶ [0505])).
Regarding claim 7, Wang discloses the detector according to claim 6, but does not disclose in the same embodiment wherein a plurality of the photoelectric conversion parts is provided, the plurality of photoelectric conversion parts includes mutually-adjacent photoelectric conversion parts, and the fourth semiconductor region surrounds the mutually-adjacent photoelectric conversion parts.
However, in another embodiment, Wang discloses a detector chip 9800 comprising an array of light detectors 9810 arranged in an grid pattern (two rows by four columns, for example; ¶ [0582]). It would have been obvious to a person having ordinary skill in the art to have combined the embodiment of claim 1 with the embodiment of detector chip 9800 such that the light detector of claim 1 (Figs 84B,85) is used in place of each 9810. In this configuration, each of the plurality of photoelectric conversion parts is surrounded by a fourth semiconductor region (connecting well 8006; Figs 80,84B {unlabeled in 84B, beneath Cat}; as applied to claim 6). When arranged in a grid pattern, the plurality of light detectors comprises mutually-adjacent photoelectric conversion parts, which are each interior to the outermost portions of the (plurality of) fourth semiconductor region(s); the fourth semiconductor region thereby surrounding the mutually adjacent-photoelectric conversion parts (interpreting “surrounds” in view of page 34, lines 10-21 of the disclosure). One would have been motivated to combine the embodiments in order to take advantage of the low reverse bias avalanche voltage and high quantum efficiency (QE; ¶ [0527]) of the claim 1 light detector with the integrated ASIC functionality (¶ [0582]) of detector chip 9800. One would have had a reasonable expectation of success because of Wang disclose an MSAPD type device in both embodiments.
Regarding claim 9, the Wang discloses the light detected for claim 6, but does not disclose wherein the fourth semiconductor region is surrounded with a trench.
However, elsewhere in the disclosure Wang discloses that isolation trenches can surround an entire light detector (Fig 63C; ¶ [0441]). It would have been obvious to a person having ordinary skill in the art that an isolation trench may surround the light detector of claim 6, thereby surrounding the fourth semiconductor region comprised therein. One may have been motivated to do this when monolithically integrating the light detector with other circuits (TIA/ASIC’s; Fig 63C; ¶ [0441]) in order to fully isolate the light detector from the other circuits. One would have been motivated to do this because of Wang’s disclosure and because such isolation is well-known in the art.
Regarding claim 11, the Examiner interprets that MSPD/MSAPD 9810 of Fig 98 (¶ [0582-583]) may be any number of MSPD/MSAPD photodetectors described throughout the disclosure, Wang having indicated no limitation and disclosing only that 9810 may be formed with or without superstrates (¶ [0582]). That is, 9810 is interpreted to be a genus which includes the species photodetectors cited with reference to Fig 84B. The Examiner therefore is citing the necessary details from Fig 84B in combination with Fig 98 which lacks those details in regards to photodetectors 9810.
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Wang discloses a light detector (in particular example, Figs 84A,84B,85,89; ¶ [0517-531, 0582-583]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the substrate including
a light-receiving region (the region vertically above 9860 in Fig. 98, comprising 9810) including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]), the photoelectric conversion part including a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) and a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]), the first semiconductor region being of a first conductivity type, the second semiconductor region being of a second conductivity type, a first trench (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]) being provided in the light-receiving region, and
a transistor region (the region including 9860 and vertically below in Fig. 98, comprising CMOS/BiCMOS ASICs) arranged with the light-receiving region in a direction perpendicular to a first direction (into the page, Fig 98; vertical direction, Fig 84B), the first direction being from the first semiconductor layer toward the second semiconductor layer, the transistor region including a transistor (CMOS/BiCMOS ASICs include a transistor),
the transistor region including a second trench (9860; Fig 98; ¶ [0582]) located between the light-receiving region and at least a portion of the transistor,
in the light-receiving region, the second semiconductor layer further including
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (connecting well 8006, which is N {plus} type; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) positioned above the third semiconductor region and electrically connected with the third semiconductor region (¶ [0505]), the fourth semiconductor region being of the second conductivity type,
the first trench (8462) being positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region (8424) being positioned below the first trench, the third semiconductor region electrically connecting the photoelectric conversion part and the fourth semiconductor region (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B), wherein
the substrate includes a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned between the photoelectric conversion part and a portion of the first semiconductor layer.
Wang does not disclose, in the embodiment of Fig 84B, a portion of the insulating layer overlaps the void in the first direction.
However, Wang discloses another method of providing a void positioned between the photoelectric conversion part and a portion of the first semiconductor layer, wherein a portion of the insulating layer overlaps the void in the first direction. In Fig 84B, the void 8490 is formed by removing oxide from BOX layer 8408 through holes 8460 (¶ [0517,0525]). Wang discloses another method of forming a void (holes/voids 1914; Figs 19A-19D; ¶ [0242-244]; {see also 532; Figs 5,6A-6D; ¶ [0196-8]}; see the included figures below) in a BOX layer, including bonding a second substrate (1906; Figs 19C-19D; ¶ [0242]) onto a first substrate (1902; Figs 19A-19D; ¶ [0242]) which has had a void (1914; Figs 19B-19D; ¶ [0242]) patterned into its surface (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the BOX/void structure 1904 of Figs 19C-D for the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of providing a more highly reflecting interface by including lower refractive index air in the layer, since each of the structures is disclosed as being capable of serving the same purpose of enabling a reflective interface (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
As shown in Figs 19C-D, a portion of insulating layer 1904 overlaps the void 1914 in the first direction.
Regarding claim 12, Wang discloses the light detector of claim 11, but does not disclose wherein a lower end of the second trench reaches the insulating layer. However, this would have been obvious to a person having ordinary skill in the art to prevent a leakage path beneath the second trench between the light-receiving region and the transistor region, and thereby provide electrical isolation therebetween (Wang; ¶ [0582]). One would have been motivated to do this, with a reasonable expectation of success, because requirements for a trench to provide electrical isolation is well-known in the art, and because Wang discloses this configuration in other embodiments (for example, in regards to trench 4462; Fig 46; ¶ [0332,0341]).
Regarding claim 15, Wang discloses the light detector of claim 11, wherein the substrate includes a void positioned between the transistor and a portion of the first semiconductor layer. (Because the BOX/void structure 1904 of Figs 19C-D is provided as a hole containing layer between two bonded wafers, the transistor is positioned above the void and therefore between the void and a portion of the first semiconductor layer which is below the hole containing layer.)
Regarding claim 16, Wang discloses the light detector of claim 11, but does not disclose further comprising: a conductive layer, the first semiconductor layer being located between the conductive layer and the insulating layer.
However, elsewhere in the disclosure (¶ [0463]) Wang discloses that a through silicon via (TSV) may be used to connect front side electrodes (anode, cathode {¶ [0458]) to the bottom substrate for a solder bump connection at the backside. Accordingly, it would have been obvious to a person having ordinary skill in the art that the TSV would need to connect to a conductive layer (comprising solder bump pads, for example) on the backside and to form a conductive layer on the light detector of claim 11 satisfying claim 16 in this manner. One would have been motivated to do this in order to satisfy particular packaging connection requirements for a particular application, and would have had a reasonable expectation of success because it is well-known in the art.
Regarding claim 17, Wang discloses the light detector of claim 1, wherein the photoelectric conversion part is a p-i-n diode or an avalanche photodiode (for example, avalanche photodiode {MSAPD}, as applied to claim 1).
Regarding claim 18, Wang discloses the light detector of claim 17, wherein the avalanche photodiode operates in a Geiger mode (the MSAPD can be operated in Geiger-counter mode; ¶ [0602]).
Regarding claim 19, Wang discloses a light detection system (LIDAR chip; ¶ [0534,0256]), comprising: the detector according to claim 1; and a distance measuring circuit calculating a time-of-flight of light based on an output signal of the detector (¶ [0256]).
Regarding claim 20, Wang discloses a lidar device (see Fig 8; ¶ [0205]), comprising: a light source irradiating light on an object (vertical cavity emitting laser {VCSEL}; ¶ [0256]) and the light detection system according to claim 19, the light detection system detecting light reflected by the object (¶ [0256]).
Regarding claim 21, Wang discloses a method for manufacturing a light detector, the method comprising:
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preparing a substrate including a first semiconductor layer (8400, for example, a silicon {Si} substrate; Fig 84B) an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer, and a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) located between the first semiconductor layer and the second semiconductor layer;
forming, in the substrate, a trench having a lower end positioned in the second semiconductor layer (8462 {ring/perimeter trench}; Figs 84B,85; ¶ [0518]); and
forming, in the second semiconductor layer, a photoelectric conversion part (MSPD/MSAPD {microstructure-enhanced photodetector/avalanche microstructured photodiode}; ¶ [0038-39, 0517]) including a first semiconductor region of a first conductivity type (8428, which is P type; Fig 84B; ¶ [0525]) and a second semiconductor region of a second conductivity type (8426, which is N {minus} type; Fig 84B; ¶ [0525]), the photoelectric conversion part being positioned above the void, surrounded with the trench (as shown in Fig 84B),
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B).
Wang does not disclose the void is already formed, when the trench is formed, being silent in regards to the sequence of formation of the void and the trench. The Examiner does not believe it is obvious which of the void or trench is or should be formed before the other, and there are a finite number of possibilities, but a disclosed alternate void formation method renders the question moot:
Wang discloses another method of preparing a substrate, the substrate including a first semiconductor layer (1906; Figs 19C-19D; ¶ [0242]), an insulating layer (1904; Figs 19B-19D; ¶ [0242]) located on the first semiconductor layer, a second semiconductor layer (1902; Figs 19A-19D; ¶ [0242]) located on the insulating layer, and a void (1914; Figs 19C-19D; ¶ [0242-244]), located between the first semiconductor layer and the second semiconductor layer (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the preparing a substrate comprising the BOX/void structure 1904 of Figs 19C-D for the preparing the substrate comprising the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of preparing a substrate having a highly reflecting interface, since the structure of each substrate preparation method is disclosed as being capable of serving the same purpose of enabling a reflective interface (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
Regarding claim 22, Wang discloses the method according to claim 21, wherein the void is formed, in a manufacturing process of the substrate, by processing at least one of the insulating layer and the first semiconductor layer and bonding a support substrate including the first semiconductor layer to the second semiconductor layer (as applied to claim 21; Figs 19A-19D; ¶ [0242-244]).
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang). Second Interpretation
Regarding claim 1 (Second Interpretation), Wang discloses a light detector (in particular example, Figs 84A,84B,85; ¶ [0517-531]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the photoelectric conversion part including
a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) of a first conductivity type, and
a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]) of a second conductivity type,
the substrate including
a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned below the photoelectric conversion part and between the first semiconductor layer and the second semiconductor layer, and
a trench (connecting well 8006 {0505,0510}; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) surrounding the photoelectric conversion part, a lower end of the trench being positioned in the second semiconductor layer,
the photoelectric conversion part being electrically connected with an upper surface side of the substrate via a portion below the trench (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8006 {unlabeled; see Fig 80}; Fig 84B).
Wang does not disclose, in the embodiment of Figs 84B,85, the substrate having no hole extending from an upper surface of the substrate to the void, because holes 8460 (Fig 84B; ¶ [0517,0525]) extend from an upper surface of a substrate to the void, the holes having enabled the formation of the void. However, Wang discloses another method of removing oxide from the BOX layer to enable forming a higher reflection semiconductor-air interface (which is provided in Fig 84B by the semiconductor-air interface of the void 8490; ¶ [0518]). Wang discloses the method of forming the interface by forming a void (holes/voids 1914; Figs 19A-19D; ¶ [0242-244]; {see also 532; Figs 5,6A-6D; ¶ [0196-8]}; see the included figures below) in a BOX layer, including bonding a second substrate (1906; Figs 19C-19D; ¶ [0242]) onto a first substrate (1902; Figs 19A-19D; ¶ [0242]) which has had a void (1914; Figs 19B-19D; ¶ [0242]) patterned into its surface (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the BOX/void structure 1904 of Figs 19C-D for the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of providing the more highly reflecting interface by including the lower refractive index air (hole), since each of the structures is disclosed as being capable of serving the same purpose (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
Regarding claim 10, Wang discloses the detector according to claim 1 (Second Interpretation), further comprising:
a conductive part located inside the trench (as applied to claim 1),
the second semiconductor layer further including a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) of the second conductivity type positioned above the insulating layer,
a portion of the third semiconductor region being positioned under a lower end of the conductive part and electrically connecting the conductive part and the photoelectric conversion part (as shown in Figs 80,84B; ¶ [0505]) .
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Wang; Shih-Yuan et al. (US 2019/0288132; hereinafter Wang). (Second Interpretation)
Regarding claim 11 (Second Interpretation), the Examiner interprets that MSPD/MSAPD 9810 of Fig 98 (¶ [0582-583]) may be any number of MSPD/MSAPD photodetectors described throughout the disclosure, Wang having indicated no limitation and disclosing only that 9810 may be formed with or without superstrates (¶ [0582]). That is, 9810 is interpreted to be a genus which includes the species photodetectors cited with reference to Fig 84B. The Examiner therefore is citing the necessary details from Fig 84B in combination with Fig 98 which lacks those details in regards to photodetectors 9810.
Wang discloses a light detector (in particular example, Figs 84A,84B,85,89; ¶ [0517-531, 0582-583]; entire document), comprising:
a substrate including
a first semiconductor layer (the layer below BOX 8408, for example, a silicon {Si} substrate; Fig 84B; {silicon on holes} SOH, {silicon on insulator} SOI, or bulk wafer; ¶ [0198]),
an insulating layer ({buried oxide} BOX 8408; Fig 84B; ¶ [0517]) located on the first semiconductor layer, and
a second semiconductor layer (layers above BOX 8408, including 8424,8426,8428,8402; Fig 84B; ¶ [0525]) located on the insulating layer,
the second semiconductor layer including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]),
the substrate including
a light-receiving region (the region vertically above 9860 in Fig. 98, comprising 9810) including a photoelectric conversion part (MSPD/MSAPD; ¶ [0038-39, 0517]), the photoelectric conversion part including a first semiconductor region (8428, which is P type; Fig 84B; ¶ [0525]) and a second semiconductor region (8426, which is N {minus} type; Fig 84B; ¶ [0525]), the first semiconductor region being of a first conductivity type, the second semiconductor region being of a second conductivity type, a connecting well (8006; Figs 80,84B {unlabeled in 84B, beneath Cat}; ¶ [0505,0525]) being provided in the light-receiving region, and
a transistor region (the region including 9860 and vertically below in Fig. 98, comprising CMOS/BiCMOS ASICs) arranged with the light-receiving region in a direction perpendicular to a first direction (into the page, Fig 98; vertical direction, Fig 84B), the first direction being from the first semiconductor layer toward the second semiconductor layer, the transistor region including a transistor (CMOS/BiCMOS ASICs include a transistor),
the transistor region including a second trench (9860; Fig 98; ¶ [0582]) located between the light-receiving region and at least a portion of the transistor,
in the light-receiving region, the second semiconductor layer further including
a third semiconductor region (8424, which is N {plus} type; Fig 84B; ¶ [0525]) positioned above the insulating layer, the third semiconductor region being of the second conductivity type; and
a fourth semiconductor region (8426, which is N {minus} type, outside the photoelectric conversion part {on a side opposite the connecting well from the photoelectric conversion part}; Fig 84B; ¶ [0525]) positioned above the third semiconductor region and electrically connected with the third semiconductor region, the fourth semiconductor region being of the second conductivity type,
the connecting well being positioned between the fourth semiconductor region and the photoelectric conversion part (as shown in Fig 84B),
a portion of the third semiconductor region (8424) being positioned below the connecting well, the third semiconductor region electrically connecting the photoelectric conversion part and the fourth semiconductor region (top surface Cat {cathode} is electrically connected with the MSAPD through layer 8424 below trench 8462 and the connecting well {unlabeled; see 8006, Fig 80; ¶ [0505]}; Fig 84B), wherein the substrate includes a void (8490 {where BOX 8408 is etched away}; Fig 84B; ¶ [0517]) positioned between the photoelectric conversion part and a portion of the first semiconductor layer.
Wang does not disclose, in the embodiment of Fig 84B:
(1) a portion of the insulating layer overlaps the void in the first direction; and
(2) that the connecting well is a trench.
Regarding (1) Wang discloses another method of providing a void positioned between the photoelectric conversion part and a portion of the first semiconductor layer, wherein a portion of the insulating layer overlaps the void in the first direction. In Fig 84B, the void 8490 is formed by removing oxide from BOX layer 8408 through holes 8460 (¶ [0517,0525]). Wang discloses another method of forming a void (holes/voids 1914; Figs 19A-19D; ¶ [0242-244]; {see also 532; Figs 5,6A-6D; ¶ [0196-8]}; see the included figures below) in a BOX layer, including bonding a second substrate (1906; Figs 19C-19D; ¶ [0242]) onto a first substrate (1902; Figs 19A-19D; ¶ [0242]) which has had a void (1914; Figs 19B-19D; ¶ [0242]) patterned into its surface (a SOH (silicon on holes) wafer; ¶ [0198]).
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Accordingly, it would have been obvious to a person having ordinary skill in the art to substitute the BOX/void structure 1904 of Figs 19C-D for the BOX having a void formed in accordance with Fig 84B. One would have been motivated to do this as alternate method of providing a more highly reflecting interface by including lower refractive index air in the layer, since each of the structures is disclosed as being capable of serving the same purpose of enabling a reflective interface (Fig 84B; ¶ [0518] and 1904 {532}; ¶ [0196-7,0242]), and the various figures being exemplary combinations. One would have had a reasonable expectation of success because Wang discloses that all the MSPD,MSAPD mentioned in the application can be fabricated on a SOH (silicon on holes) wafer, in addition to SOI and bulk wafers (¶ [0198]).
As shown in Figs 19C-D, a portion of insulating layer 1904 overlaps the void 1914 in the first direction.
Regarding (2), Wang discloses elsewhere in the disclosure that a connecting well may be a trench with oxide on its sidewalls and a conductive material at its center (¶ [0550] with reference to Fig 89.) Accordingly, it would have been obvious to a person having ordinary skill in the art to have used a trench such as that of Fig 89 and associated description for the connecting well (the first trench) of claim 11. One may have been motivated to do this a number of reasons known in the art including the higher conductivity provided by using a metal for the conductive material rather than a semiconductor (Wang; ¶ [0550]). One would have had a reasonable expectable of success because Wang has disclosed this as an alternate to a highly doped connecting well (¶ [0550]).
Regarding claim 13, Wang discloses the light detector of claim 11 (Second Interpretation), wherein a conductive part is located inside at least a portion of the first or second trench (the conductive material of the first trench, as applied to claim 11).
Allowable Subject Matter
Claims 3 and 8 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein a portion of the insulating layer is located between the first semiconductor layer and the photoelectric conversion part, and the void is located between the photoelectric conversion part and the portion of the insulating layer.”
Regarding claim 8, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the fourth semiconductor region does not surround the photoelectric conversion part.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/B.A.K./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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