DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/12/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-6, 9-10, and 13-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeyama (US 20140346878) in view of Yasuda (US 20120075910).
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With respect to claim 1, figures 1-5 of Umeyama (US 20140346878) discloses a circuit, comprising: a control circuit (120) configured to: receive a selection signal (SD) transitioning within a first voltage domain (VM – GND); and generate, based on the selection signal (SD), a first control signal (SC from B22) transitioning within a second voltage domain (VB-GND) different from the first voltage domain; and a switch circuit (130) operatively coupled to the control circuit (120) and comprising: a first header transistor (M3b1) coupled to a first voltage supply (220) transitioning within the second voltage domain (VB – GND), and gated by the first control signal (Sc); and a second header transistor (M3m1) coupled to a second voltage supply (210) transitioning within the first voltage domain (VM – GND), and gated by a second control signal (SC from B21) that is logically inverse to the first control signal (SC from B22); a third header transistor (M3b2) coupled to the first header transistor in series, , wherein a drain of the first header transistor is connected to a source of the third header transistor (connected through the transistor M3b1), and a drain of the third header transistor is connected to an output node (vout); and a fourth header transistor (M3m2) coupled to the second header transistor in series wherein the fourth header transistor is gated by a fourth control signal that is logically inverse to the third control signal. wherein the first header transistor (M3b1) and the second header transistor (M3m1) are complementarily turned on so as to provide an output voltage (Vout) equal to either the first voltage supply (220) or the second voltage supply (210) wherein the second and fourth header transistors each have its VSG equal to or less than 0 volts (V) when providing the output voltage equal to the first voltage supply (Note: To supply the first voltage supply to the output when second and fourth header transistors VSG are less than or equal to zero because the transistors are NMOS the transistors would be off, in the event the 1st and 3rd transistors are on, the first voltage would be seen at the output) , but fails to disclose the third control signal being different from the first control signal.
Yasuda teaches the substitution of transmission gates for transistors in switches. “A transmission gate formed of the p-channel type MOS transistor and the n-channel type MOS transistor may substitute for the transistor as a switch.” [0070] It would be obvious at the time the invention was made to a person having ordinary skill in the art to use transmission gates in the structure of figure 3 for the transistors as they are recognized as art equivalents in switches. The resulting circuit would cure the deficiencies of Umeyama by having one transistor in series having the control signal at the gate and another transistor in series having an inverse control signal at the gate. Thus the gates would receive a control signal and an inverted control signal different from the control signal. In such a configuration one header gate would receive the “control signal” and the other header gate would receive a different inverted “control signal”. Thus the deficiency of Umeyama would be cured by the teaching of Yasuda.
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With respect to claim 2, the circuit above produces the circuit of claim 1, wherein the control circuit (120) comprises a level shifter (1104) powered by the first voltage supply (220) (VM) , and configured to receive the selection signal (SD) and shift the selection signal (SD) from the first voltage domain (VM – GND) to the second voltage domain (VB-GND).
With respect to claim 4, the circuit above produces the circuit of claim 1, wherein the first and second control signals are generated based on the shifted selection signal (SD) .
With respect to claim 5, the circuit above produces the circuit of claim 1, wherein each of the first to fourth header transistors includes a p- type metal-oxide-semiconductor (PMOS) transistor (paragraphs [0113-0114]).
With respect to claim 6, the circuit above produces the circuit of claim 5, the first (M3b1) and third (M3b2) header transistors each have its VsG equal to or less than 0 V when providing the output voltage equal to the second voltage supply (210) .
With respect to claim 9, the circuit above produces the circuit of claim 1, further comprising: a maximum voltage selection circuit (1101) configured to select a greater one of the first voltage supply (220) or second voltage supply (210) ; wherein the control circuit (120) comprises a level shifter (1104) powered by the greater one of the first voltage supply (220) or second voltage supply (210) , and configured to receive the selection signal (SD) and shift the selection signal (SD) from the first voltage domain (VM – GND ) to the second voltage domain.
With respect to claim 10, the circuit above produces the circuit of claim 9, wherein the first and second control signals are generated based on the shifted selection signal (SD) .
With respect to claim 13, figures 1-5, 10-11 and 14 of Umeyama disclose circuit, comprising: a control circuit (120) configured to: receive a selection signal (SD) transitioning within a first voltage domain; and generate, based on the selection signal (SD) , a first control signal (SC from B22) and a second control signal (SC from B21) transitioning within a second voltage domain (VB-GND) different than the first voltage domain, wherein the first control signal and the second control single are logically inverse to each other; and a switch circuit (130) operatively coupled to the control circuit (120) and comprising: a first header transistor (M3b1) coupled to a first voltage supply (220) transitioning within the second voltage domain, and gated by the first control signal; and a second header transistor (M3m1) coupled to a second voltage supply (210) transitioning within the first voltage domain, and gated by the second control signal; a third header transistor (M3m2) coupled to the first header transistor in series, wherein the third header transistor is gated by a third control signal transitioning within the second voltage domain; and a fourth header transistor (M3m2) coupled to the second header transistor in series wherein the fourth header transistor is gated by a fourth control signal that is logically inverse tot the third control signal; wherein the first header transistor (M3b1) and the second header transistor (M3m1) are complementarily turned on so as to couple either the first voltage supply (220) or the second voltage supply (210) to an output node wherein the second and fourth header transistors each have its VSG equal to or less than 0 volts (V) when providing the output voltage equal to the first voltage supply (Note: To supply the first voltage supply to the output when second and fourth header transistors VSG are less than or equal to zero because the transistors are NMOS the transistors would be off, in the event the 1st and 3rd transistors are on, the first voltage would be seen at the output) , but fails to disclose the third control signal being different from the first control signal.
Yasuda teaches the substitution of transmission gates for transistors in switches. “A transmission gate formed of the p-channel type MOS transistor and the n-channel type MOS transistor may substitute for the transistor as a switch.” [0070] It would be obvious at the time the invention was made to a person having ordinary skill in the art to use transmission gates in the structure of figure 3 for the transistors as they are recognized as art equivalents in switches. The resulting circuit would cure the deficiencies of Umeyama by having one transistor in series having the control signal at the gate and another transistor in series having an inverse control signal at the gate.
With respect to claim 15, the circuit above produces the circuit of claim 13, wherein each of the first to fourth header transistors is a p-type metal-oxide-semiconductor (PMOS) transistor (see paragraphs [0113]-[0114]),, and wherein the output node is directly connected to a drain of the second header transistor (M3m2) and a drain of the third header transistor (M3b2).
With respect to claim 16, the circuit above produces the circuit of claim 13, wherein the control circuit (120) comprises: an even number of first inverters configured to receive the selection signal (SD) in the first voltage domain (VM – GND) and generate the first and second control signals; a level shifter configured to shift the selection signal (SD) to the second voltage domain; and an even number of second inverters configured to receive the shifted selection signal (SD) and generate the third and fourth control signals (Here, the inverters inside the level shifter are included).
With respect to claim 17, the circuit above produces the circuit of claim 13, wherein each of the first and second header transistors is a p- type metal-oxide-semiconductor (PMOS) transistor (see paragraphs [0113]-[0114]), and wherein the output node is directly connected to a drain of the first header transistor (M3b) and a drain of the second header transistor.
With respect to claim 18, the circuit above produces the circuit of claim 17, wherein the control circuit (120 ) comprises: a level shifter (1104) configured to shift the selection signal (SD) transitioning in the first voltage domain (VM – GND) to the second voltage domain (VB-GND) and output the shifted selection signal (SD) as the first control signal; and an odd number of inverters configured to invert the shifted selection signal (SD) as the second control signal (even being 2 and odd being 3 including B33 inside level shifter shown in fig. 11).
With respect to claim 19, the circuit above produces a method for selecting a voltage supply, comprising: receiving a selection signal (SD) transitioning in a first voltage domain (VM – GND ); generating, based on the selection signal (SD) , a first control signal (SC from B21) transitioning within the first voltage domain and a second control signal (SC from B22) transitioning within a second voltage domain (VB-GND) different from the first voltage domain; coupling a first voltage supply (220) to an output node (at Vout) through a first header transistor (M3b1 (within the transmission gate)) that is gated by the first control signal (SC from B22), and a second header transistor (M3m1 (within the transmission gate)) that is gated by the second control signal , wherein the first voltage supply (220) transitions within the first voltage domain; and decoupling a second voltage supply (210) from the output node through a third header transistor (M3m2 (within the transmission gate)) that is gated by the third control signal (SC from B22) and a fourth header transistor (M3b2 (within the transmission gate)) that is gated by a fourth control signal logically inverse to the second control signal wherein the second voltage supply (210) transitions within the second voltage domain wherein the second and fourth header transistors each have its VSG equal to or less than 0 volts (V) when providing the output voltage equal to the first voltage supply (Note: To supply the first voltage supply to the output when second and fourth header transistors VSG are less than or equal to zero because the transistors are NMOS the transistors would be off, in the event the 1st and 3rd transistors are on, the first voltage would be seen at the output) .
With respect to claim 20, the circuit above produces the method of claim 19, wherein each of the first to fourth header transistors is a p- type metal-oxide-semiconductor (PMOS) transistor (the transmission gates would have both p-type and n-type transistors available).
With respect to claim 21, the circuit above produces the method of claim 19, wherein the first header transistor and the second header transistor are connected to each other in series, and the third header transistor and the fourth header transistor are connected to each other in series.
With respect to claim 22, the circuit above produces the method of claim 19, wherein the first control signal is different from the second control signal. (Here, the second control signal would be inverse of the first control signal).
Claim(s) 8 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeyama (US 20140346878) in view of Yasuda (US 20120075910) in further view of Zhou (US 10862463).
With respect to claim 8, the combination above discloses the circuit of claim 1, but fails to disclose further comprising: a first NAND-type SR latch; one or more first delay circuits coupled to the first NAND-type SR latch; a second NAND-type SR latch; and one or more second delay circuits coupled to the second NAND-type SR latch; wherein, during transition between the first voltage supply (220) and the second voltage supply (210) , the first to fourth header transistors are each configured to be turned off through the first NAND-type SR latch, the one or more first delay circuits, the second NAND-type SR latch, and the one or more second delay circuits
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Figure 1 of Zhou teaches the use of a high speed level shifter that has self correction features that ensure normal operation. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the level shifter of Zhou in the circuit of Umeyama for the purpose of producing a normal signal during switching operations.
The resulting circuit would produce a first NAND-type SR latch (Nand 3 and 4); one or more first delay circuits coupled to the first NAND-type SR latch (delay chain 1; wherein, during transition between the first voltage supply (220) and the second voltage supply (210) , the first to fourth header transistors are each configured to be turned off through the first NAND-type SR latch, the one or more first delay circuits, , and the one or more second delay circuits ); but fails to teach a second NAND-type SR latch; and one or more second delay circuits coupled to the second NAND-type SR latch.
It is well known in the art to use multiple level shifters to drive different domains of load components. It would be obvious at the time the invention was made to use multiple level shifters instead of the single ls in level shifter of Umeyama for the purpose of driving the different domains. The resulting circuit would use the level shifter of Zhou as the multiple level shifters to replace the single level shifter of Umeyama to drive the different domain components.
With respect to claim 12, the combination above produces the circuit of claim 9, further comprising: a NAND-type SR latch (fig 1) and one or more delay circuits coupled to the NAND-type SR latch (delay chain 1 and delay chain 2); wherein, during transition between the first voltage supply (220) and the second voltage supply (210) , the first to second header transistors are each configured to be turned off through the NAND-type SR latch and the one or more delay circuits.
Claim(s) 7 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Umeyama (US 20140346878) in view of Yasuda (US 20120075910) in further view of Zhou (US 10862463).
With respect to claim 7, the combination above produces the claim according to claim 3 but fails to disclose furhter comprising: a first NOR-type SR latch; one or more first delay circuits coupled to the first NOR-type SR latch; a second NOR-type SR latch; and one or more second delay circuits coupled to the second NOR-type SR latch; wherein, during transition between the first voltage supply (220) and the second voltage supply (210) , the first to fourth header transistors are each configured to be turned on through the first NOR-type SR latch, the one or more first delay circuits, the second NOR-type SR latch, and the one or more second delay circuits.
It is well known in the art to substitute NAND sR flip-flops for NOR SR flip flops. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace NAND SR flip-flops with nor SR-Flip flops for the purpose of using readily available components.
With respect to claim 11, the combination above produces the circuit of claim 9, but fails to disclose further comprising: a NOR-type SR latch; one or more delay circuits coupled to the NOR-type SR latch; wherein, during transition between the first voltage supply (220) and the second voltage supply (210), the first to second header transistors are each configured to be turned on through the NOR-type SR latch and the one or more delay circuits.
It is well known in the art to substitute NAND sR flip-flops for NOR SR flip flops. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace NAND SR flip-flops with nor SR-Flip flops for the purpose of using readily available components.
Response to Arguments
Applicant's arguments filed 12/17/2025 have been fully considered but they are not persuasive.
With respect to applicant’s argument, that the way the Examiner combined the references Umeyama in view of Yasuda fails to teach or suggest all the features in claims 1, 13 and 19 the Examiner disagrees.
With respect to applicant’s argument that Umeyama would not teach the second header and fourth header transistors have a VSG equal to or less than 0 volts when providing an output voltage equal to a first supply voltage, the Examiner disagrees. For the output to be equal to the first power supply, the second and fourth header transistors would be off, thus providing VSG equal to or less than 0 such that the power from 220 is seen at the output. As such, the amended claims still read on the invention as stated.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849