Prosecution Insights
Last updated: July 17, 2026
Application No. 18/169,662

Electromagnetic Interference Shield with Thermal Conductivity

Final Rejection §103
Filed
Feb 15, 2023
Priority
Aug 24, 2022 — provisional 63/400,651
Examiner
CULLEN, PATRICK LAWRENCE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
13 granted / 16 resolved
+13.3% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
35 currently pending
Career history
72
Total Applications
across all art units

Statute-Specific Performance

§103
97.4%
+57.4% vs TC avg
§102
1.7%
-38.3% vs TC avg
§112
0.9%
-39.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 16 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The amendment filed 12/23/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: “For example, the array 84 and/or the EMI mesh 63 may have a width and/or length greater than 10 millimeters (mm), greater than 15 mm, greater than 20 mm, greater than 25 mm, 30 mm or less, or greater than 30 mm.” Applicant is required to cancel the new matter in the reply to this Office Action. Claim Rejections - 35 USC § 103 Claim(s) 1-2, 4-7, 21-24, and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Fay (PGPub No. 20220068837) in further view of Ranganathan (PGPub No. 20220206061). Regarding claim 1, Fay teaches an electronic device, comprising: a semiconductor die (Fig. 2 points to a semiconductor device (electronic device) comprising a semiconductor die 102.); a thermal interface material (TIM) thermally coupled to a surface of the semiconductor die (Id. points to a thermal interface material 215.); and a thermal electromagnetic interference (EMI) shield thermally coupled to the semiconductor die along the surface of the semiconductor die (Id. points to an EMI shield 106.). Fay fails to teach wherein the thermal EMI shield comprises one or more windows, and at least a portion of the TIM is disposed within the one or more windows. Ranganathan teaches wherein the thermal EMI shield comprises one or more windows (Fig. 3 and [0070] point to an active thermal interposer device 300 comprising an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (one or more windows).), and at least a portion of the TIM is disposed within the one or more windows (Fig. 3, [0070], and [0072] point to a top thermal layer 340 (TIM) positioned directly above the EMI shield layer 320, which may comprise a grid of conductive elements (one or more windows). In light of this, it is considered obvious that at least a portion of the thermal layer 340 would form within the gaps created by the grid of conductive elements comprising the EMI shield layer 320.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Fay and Ranganathan, such that the EMI shield comprises one more windows with the thermal layer/TIM at least partially disposed within in order to improve heat dissipation while still providing some level of electromagnetic interference. Regarding claim 2, Ranganathan teaches wherein the one or more windows is an array of windows along width and length of the thermal EMI shield (Fig. 3 and [0070] point to an active thermal interposer device 300 comprising an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (one or more windows).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fay and Ranganathan, such that the thermal EMI is not a single piece but rather a grid/array of windows in order to attenuate desired wavelength(s) of electromagnetic interference. Regarding claim 4, Fay teaches wherein the thermal EMI shield is physically coupled to the surface of the semiconductor die (Fig. 2 points to the EMI shield 106 coupled to the semiconductor die 102 via the TIM 215.). Regarding claim 5, Fay teaches a spreader physically coupled to the TIM (Fig. 2 and [0018] point to the TIM 215 coupled to a second dielectric material 108 (spreader) via the EMI shield 106.). Regarding claim 6, Fay teaches wherein the thermal EMI shield comprises a conductive material ([0013] points to the EMI shield 106 including one or more other materials, such as one or more other thermally conductive materials.). Regarding claim 7, Fay teaches wherein the TIM comprises a phase change material, a thermal paste, a thermal adhesive, or any combination thereof ([0017] points to the TIM 215 including a ferrous material, copper, copper alloy, cobalt, and/or one or more other thermally conductive materials (phase change material).). Regarding claim 21, Fay teaches an electronic device, comprising: a semiconductor die (Fig. 2 points to a semiconductor device (electronic device) comprising a semiconductor die 102.); and a thermal interface material (TIM) thermally coupled to a surface of the semiconductor die (Id. points to a thermal interface material 215.); and a thermal electromagnetic interference (EMI) shield thermally coupled to the semiconductor die along the surface of the semiconductor die (Id. points to an EMI shield 106.). Fay alone fails to teach a thermal electromagnetic interference (EMI) shield comprising a conductive material forming a plurality of windows, wherein the thermal EMI shield is thermally coupled to the semiconductor die via at least a portion of the TIM that is disposed within the plurality of windows, wherein the TIM and thermal EMI shield are physically coupled to a top surface of the semiconductor die. Fay in combination with Ranganathan teaches a thermal electromagnetic interference (EMI) shield comprising a conductive material forming a plurality of windows (Fig. 3 and [0070] of Ranganathan point to an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (plurality of windows).), wherein the thermal EMI shield is thermally coupled to the semiconductor die (Fig. 2 of Fay points to the EMI shield 106 being coupled to the semiconductor die 102 via the TIM 215.) via at least a portion of the TIM that is disposed within the plurality of windows (Fig. 3, [0070], and [0072] of Ranganathan point to a top thermal layer 340 (TIM) positioned directly above the EMI shield layer 320, which may comprise a grid of conductive elements (plurality of windows). In light of this, it is considered obvious that at least a portion of the thermal layer 340 would form within the gaps created by the grid of conductive elements comprising the EMI shield layer 320.), wherein the TIM and thermal EMI shield are physically coupled to a top surface of the semiconductor die (Fig. 2 points to the EMI shield 106 coupled to the semiconductor die 102 via the TIM 215.).Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fay and Ranganathan, such that the electronic device further comprises an EMI shield made up of a grid/array of windows which allow said shield to be thermally coupled to a die via the TIM in order to provide electromagnetic interference while still maintaining heat dissipation. Regarding claim 22, Ranganathan teaches wherein a length, a width, or both, of the plurality of the windows are substantially the same (Fig. 3 and [0070] point to an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (plurality of windows). The use of the term “grid” is interpreted to imply a sense of uniformity in the sense that the length(s) and/or width(s) of each conductive element (window) are substantially the same.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fay and Ranganathan, such that each conductive element/window comprises substantially the same length and/or width in order to create a uniform surface across the grid/plurality and by extension provide uniform shielding to the underlying region(s). Regarding claim 23, Fay teaches wherein a thickness of the EMI shield is 1 millimeter or less ([0018] points to the EMI shield 106 having a thickness in the range of 30 µm to 2 mm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Regarding claim 24, Fay teaches wherein the thermal electromagnetic interference (EMI) shield comprises a dimension that is 30 millimeters or less ([0018] points to the EMI shield 106 having a thickness in the range of 30 µm to 2 mm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Regarding claim 26, Fay teaches wherein the TIM and the thermal EMI shield are physically coupled to the surface of the semiconductor die (Fig. 2 points to the EMI shield 106 coupled to the semiconductor die 102 via the TIM 215.). Regarding claim 27, Fay teaches wherein the TIM is physically coupled to the surface of the semiconductor die (Fig. 2 points to the TIM 215 and the semiconductor die 102.). Regarding claim 28, Ranganathan teaches wherein a width, a length, or both of a window of the plurality of windows is 5 millimeters or less (Fig. 3, [0070], and [0072] point to a top thermal layer 340 (TIM) positioned directly above the EMI shield layer 320, which may comprise a grid of conductive elements (plurality of windows) which may be resized. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the size of the grid (and by extension the size of each conductive element (window)) to be a result effective variable affecting the attenuation of desired wavelength(s) of electromagnetic interference. Thus, it would have been obvious to modify the device of Ranganathan to have the width and/or length of a window within the claimed range in order to better control the level of electromagnetic interference, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.). Regarding claim 29, Ranganathan teaches wherein the one or more windows are configured to permit the TIM to traverse through the one or more windows based on an applied force (Fig. 3, [0070], and [0072] point to a top thermal layer 340 (TIM) positioned directly above the EMI shield layer 320, which may comprise a grid of conductive elements (one or more windows) sized to attenuate desired wavelength(s) of electromagnetic interference. It is considered obvious that the grid/windows of the EMI shield layer 320 may be arranged and sized such that gaps are formed between each of the conductive elements, which would allow the thermal layer 340 (TIM) to traverse through. This embodiment alone fails to teach the use of an applied force by which said traversal would be based on. However, Fig. 4 and [0078] further point to an alternative embodiment comprising pogo pins 460 which push the EMI shield layer 320′ and top thermal layer 340′ (TIM). In light of this, it is further considered obvious that the pogo pins 460 could be applied to the grid/windows previously mentioned, resulting in an application of force that would permit the traversal of the top thermal layer 340/340′ (TIM) through the EMI shield layer 320/320′.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fay and Ranganathan, such that the TIM is permitted to traverse through the one or more windows based on an applied force in order to improve heat dissipation while still providing some level of electromagnetic interference. Claim(s) 8, 10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ranganathan (PGPub No. 20220206061) in further view of Fay (PGPub No. 20220068837). Regarding claim 8, Ranganathan teaches a thermal electromagnetic interference (EMI) shield, comprising: an EMI mesh comprising a conductive material forming a plurality of windows (Fig. 3 and [0070] point to an EMI shield layer 320, which in some embodiments comprises a grid (EMI mesh) of conductive elements (plurality of windows).). Ranganathan fails to teach a thermal interface material (TIM) coupled to the conductive material, wherein at least a portion of the TIM is disposed within the windows, and the TIM and the EMI mesh are configured to physically couple to a die. Ranganathan in combination with Fay teaches a thermal interface material (TIM) coupled to the conductive material (Fig. 2 of Fay points to a TIM 215 coupled to an EMI shield 106.), wherein at least a portion of the TIM is disposed within the windows (Fig. 3, [0070], and [0072] of Ranganathan point to a top thermal layer 340 (TIM) positioned directly above the EMI shield layer 320, which may comprise a grid of conductive elements (windows). In light of this, it is considered obvious that at least a portion of the thermal layer 340 would form within the gaps created by the grid of conductive elements comprising the EMI shield layer 320.), and the TIM and the EMI mesh are configured to physically couple to a die (Fig. 2 of Fay points to the EMI shield 106 coupled to the semiconductor die 102 via the TIM 215.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ranganathan and Fay, such that a TIM is coupled to the EMI shield in order to better dissipate heat away from the underlying region(s) and towards the EMI shield. Regarding claim 10, Ranganathan teaches wherein a length or width of each window of the plurality of windows is 1 millimeter or less (Fig. 3 and [0070] point to an active thermal interposer device 300 comprising an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (plurality of windows) that may be sized to attenuate desired wavelength(s) of electromagnetic interference. The disclosure does not appear to lend any criticality or significance to the length or width of each individual window and, as such, is deemed a matter of choice that a person of ordinary skill in the art would have found obvious. Absent persuasive evidence that a particular configuration is significant, said configuration is deemed a matter of choice which a person of ordinary skill in the art would have found obvious. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966); see also MPEP 2144.04(IV)(B).). Regarding claim 12, Ranganathan teaches wherein the EMI mesh comprises a surface, and wherein the surface comprises the conductive material forming plurality of windows arranged in columns or rows (Fig. 3 and [0070] point to an active thermal interposer device 300 comprising an EMI shield layer 320, which in some embodiments comprises a grid of conductive elements (plurality of windows arranged in columns or rows).). Regarding claim 13, Fay teaches wherein the EMI mesh comprises a dimension that is 30 millimeters or less ([0018] points to the EMI shield 106 (EMI mesh) having a thickness in the range of 30 µm to 2 mm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Ranganathan and Fay, such that the EMI mesh comprises a thickness less than 30 mm in order to increase heat transfer away from the underlying region(s). Response to Arguments Applicant’s arguments, see Remarks, filed 12/23/2025, with respect to the objection to the drawings have been fully considered and are persuasive. Said objection has been withdrawn. Applicant’s arguments, see Remarks, filed 12/23/2025, with respect to the objection of claim 11 has been fully considered and are persuasive. Said objection has been withdrawn. Applicant's arguments filed 12/23/2025 with respect to the rejections of claims 13 and 24 under 35 U.S.C. §112(a) have been fully considered and are persuasive. Said rejections have been withdrawn. Applicant’s arguments, see Remarks, filed 12/23/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. §102(a)(1)/102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Fay (PGPub No. 20220068837) in further view of Ranganathan (PGPub No. 20220206061) under 35 U.S.C. §103. Applicant's arguments filed 12/23/2025 with respect to amended claims 8 and 21 have been fully considered but they are not persuasive. Specifically, Applicant argues that Ranganathan and/or Fay fail to teach 1) that at least a portion of the TIM is disposed within one or more of the windows and 2) the “coupling” that occurs between components, both thermally and/or physically. Regarding the first argument(s), Examiner argues that Applicant has made a conclusory statement with no supporting evidence. In both sections for claims 8 and 21 (see pgs. 6 and 8 of Remarks respectively), Applicant points to the same argument made in the section for claim 1 (see pgs. 4-5), which states that “Ranganathan in silent” with respect to the top thermal layer 340 (TIM) being at least partially disposed within the EMI shield layer 320. While Examiner agrees that Ranganathan does not specifically disclose this structure, it does present the EMI shield layer 320 as a grid of conductive elements and the top thermal layer 340 as being positioned directly on said grid, such that one of ordinary skill in the art prior to the filing date would obviously conclude that a portion of the top thermal layer 340 would fall into the grid below it; Applicant’s argument of silence does nothing to address this obviousness. Thus, Applicant’s arguments fail to place the claims in a state of allowance, and the previous rejections of said claims are upheld. Regarding the second argument(s), Examiner argues that Applicant has applied a definition of the term “couple” or “coupled” that is narrower than what is actually supported by the claims. Under the broadest reasonable interpretation, coupled is defined as two or more items joined, linked, or paired together, whether thermally or physically as in the case of the present invention. In the case of Fay, the structure of Fig. 2 comprising the EMI shield 106 disposed on the TIM 215 which in turn is disposed on the semiconductor die 106 would qualify as showing coupling between the components, despite the arguments presented Applicant; physical coupling is shown by way of each component being in physical contact with one another, whether directly or indirectly, and thermal coupling is shown by the path of heat dissipation shown in Fig. 2 and further explained in [0018] of Fay, which points to the TIM 215 transferring heat away from the semiconductor die 102 and out of the overall device 200, which would by extension include going through the surrounding EMI shield 106. Thus, Applicant’s arguments fail to place the claims in a state of allowance, and the previous rejections of said claims are upheld. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Show 1 earlier event
Jun 07, 2024
Response after Non-Final Action
Jul 24, 2025
Applicant Interview (Telephonic)
Jul 24, 2025
Examiner Interview Summary
Sep 24, 2025
Non-Final Rejection mailed — §103
Dec 23, 2025
Response Filed
Apr 16, 2026
Final Rejection mailed — §103
Jun 09, 2026
Applicant Interview (Telephonic)
Jun 09, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+33.3%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 16 resolved cases by this examiner. Grant probability derived from career allowance rate.

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