DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-7, 9, 10, 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ookuma et al (U.S. 2021/0134828), Boyle et al (U.S. 3,858,232), and Fukuzumi et al (U.S. 2013/0075918).
Regarding claim 1. Ookuma et al discloses a three-dimensional integrated charge-coupled device (CCD) memory (FIG. 1 and 3, [0037]) comprising:
a gate stack (FIG. 3, item 44) comprising
a plurality of gate layers (FIG. 3, item 62) and spacer layers (FIG. 3, item 46) alternatingly arranged one on the other ([0050]) along a first direction (FIG. 3, item V),
a plurality of semiconductor-based channels (FIG. 1, item 54) extending in the gate stack (FIG. 3, item 44), and a plurality of dielectric layers (FIG. 1, item 50), each dielectric layer (FIG. 1, item 50) being arranged between ([0066]) one of the semiconductor-based channels (FIG. 1, item 54) and at least one of the gate layers (FIG. 3, item 62); and
a readout layer (FIG. 3, item 90), wherein the gate stack (FIG. 3, item 44) is arranged ([0059]) on the readout layer (FIG. 3, item 90),
wherein each ([0066]) semiconductor-based channel (FIG. 1, item 54) forms ([0066]), in combination ([0066]) with the gate layers (FIG. 1, item 62) and at least one ([0066]) of the dielectric layers (FIG. 1, item 50), a string of charge storage capacitors ([0037]-[0038]) arranged along the first direction (FIG. 3, item V)
wherein each string of charge storage capacitors ([0037]-[0038],
wherein the readout layer (FIG. 3, item 90) comprises a plurality of readout stages (FIG. 3, item 58)
Ookuma et al fails to explicitly disclose wherein each string of charge storage capacitors is operable as a CCD register, and
wherein the readout layer comprises a plurality of readout stages configured to individually readout stored charge from each of the CCD registers, wherein the readout stage of the respective CCD register is disposed under the respective string of charge storage capacitors arranged along the first direction..
However, Boyle et al teaches wherein each string of charge storage capacitors (Col 1, lines 46-55) is operable as a CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13; i.e. shift register), and
wherein the readout layer comprises a plurality of readout stages (FIG. 10) configured to individually readout stored charge (Col 12, lines 43-59) from each of the CCD registers (FIG. 2).
Since Ookuma et al, and Boyle et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the three-dimensional integrated charge-coupled device (CCD) memory as disclosed to modify Ookuma et al and Boyle et al with the teachings of wherein each string of charge storage capacitors is operable as a CCD register as disclosed by Boyle et al. The use of shift registers in Boyle et al provides for a storage medium with sufficient carrier mobility for charge carrier transfer especially important for high speed operation (Boyle et al, [Col 2, lines 15-17]).
Ookuma et al and Boyle et al fails to explicitly disclose wherein the readout stage of the respective CCD register is disposed under the respective string of charge storage capacitors arranged along the first direction .
However, Fukuzumi et al teaches
wherein the readout stage (FIG. 8, items 202; [0074]) of the respective CCD register (FIG. 8, item 111) is disposed under ([0072]-[0075]) the respective string of charge storage capacitors ([0080]) arranged along the first direction (FIG. 8, item Z).
Since Ookuma et al, Boyle et al and Fukuzumi et al teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the three-dimensional integrated charge-coupled device (CCD) memory as disclosed to modify Ookuma et al and Boyle et al with the teachings of wherein the readout layer comprises a plurality of readout stages configured to individually readout stored charge from each of the CCD registers wherein the readout stage of the respective CCD register is disposed under the respective string of charge storage capacitors arranged along the first direction as disclosed by Fukuzumi et al. The use data is read, the electrons in the channel layer are transferred downward by the shift operation described in the first embodiment, and the electrons are transferred to the diffusion layer and read as data (Fukuzumi et al, [0074]).
Regarding claim 4. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein at least one semiconductor-based channel is made of a silicon-based semiconductor material ([0042]-[0043]) or III-V semiconductor material.
Regarding claim 5. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Boyle et al further discloses wherein each CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13; i.e. shift register) is connected to one of the readout stages (FIG. 2, items 28-32; Col 5 lines 11-39), which is configured to readout stored charge (Col 7, lines 33-37) from the connected CCD register (FIG. 2; Col 3, lines 59 to Col 4).
Regarding claim 6. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Boyle et al further discloses wherein each CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13) is connected to a write stage (FIG. 2; item 25) configured to push charge (Col 6, lines 53-61) into the CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13).
Regarding claim 7. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 6 above.
Boyle et al further discloses wherein the readout stage (FIG. 2, items 28-32; Col 5 lines 11-39) and the write stage (FIG. 2; item 25) of the CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13) are connected to different ends (Col 16, lines 1-23) of the semiconductor-based channel (FIG.2, item 20) that is associated with the CCD register (FIG. 2; Col 3, lines 59 to Col 4 lines 13).
Regarding claim 9. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein at least a part of each semiconductor-based channel (FIG. 1, item 54) extends along the first direction (FIG. 1, item V) and/or extends perpendicular to parallel surfaces of the gate layers (FIG. 1, item 62).
Regarding claim 10. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein at least one semiconductor-based channel (FIG. 3, item 54) is straight in the stack (FIG. 3, item 62).
Regarding claim 14. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein each gate layer (FIG. 1, item 62) surrounds ([0066]) one or more of the semiconductor-based channels (FIG. 1, item 54).
Regarding claim 15. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein the gate stack further comprises an input transfer-gate layer (FIG. 1, item 36) and an output transfer-gate layer (FIG. 1, item 38), which sandwich the gate layers (FIG. 1, item 62) and the spacer layers (FIG. 1, item 46) of the gate stack (FIG. 1, item 36) in the first direction (FIG. 1, item V);
wherein the input transfer-gate layer (FIG. 1, item 36) and the output transfer-gate layer (FIG. 1, item 38) respectively comprise a plurality of transfer-gates ([0024])
wherein the output transfer-gate layer (FIG. 1, item 38) of the gate stack (FIG. 1, item 44) is formed ([0045]) on the readout layer (FIG. 1, item 90); and
wherein the transfer-gates ([0024]) of the output transfer-gate layer (FIG. 1, item 38) are connected to the readout stages (FIG. 3, item 58) of the readout layer (FIG. 3, item 90).
Boyle et al discloses wherein the input transfer-gate layer (Col 6, line 62 through Col 7, line 12) and the output transfer-gate layer (Col 8, lines 5-42) respectively comprise a plurality of transfer-gates (Col 6, line 62 through Col 7, line 12; Col 8, lines 5-42) configured to access the CCD registers (FIG. 2; Col 3, lines 59 to Col 4 lines 13; i.e. shift register);
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Ookuma et al (U.S. 2021/0134828), Boyle et al (U.S. 3,858,232), and Fukuzumi et al (U.S. 2013/0075918) as applied to claim 1 above, and further in view of Sharma et al (U.S. 2019/0198675)
Regarding claim 2. Ookuma et al, Boyle et al, and Fukuzumi et al discloses all the limitations of the CCD memory according to claim 1 above.
Ookuma et al further discloses wherein at least one semiconductor-based channel is made of a semiconductor material ([0042]-[0043]).
Ookuma et al, Boyle et al, and Fukuzumi et al fail to explicitly disclose wherein at least one semiconductor-based channel is made of a semiconductor oxide material
However, Sharma et al teaches wherein at least one semiconductor-based channel is made of a semiconductor oxide material ([0040]).
Since Ookuma et al, Boyle et al, Fukuzumi et al, and Sharma et al teach transistors, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the three-dimensional integrated charge-coupled device (CCD) memory as disclosed to modify Ookuma et al, Boyle et al, and Fukuzumi et al with the teachings of wherein at least one semiconductor-based channel is made of a semiconductor oxide material as disclosed by Sharma et al. The use of thin channel transistor materials such as IGZO, ITO, IZO in Sharma et al provides for improved lateral area to performance ratio as compared to an integrated circuit based on a planar gate thin film transistor (Sharma et al, [0036]).
Regarding claim 3. Ookuma et al, Boyle et al, Fukuzumi et al, and Sharma et al discloses all the limitations of the CCD memory according to claim 2 above.
Sharma et al further discloses wherein the semiconductor oxide material ([0040]) comprises at least one of: indium gallium zinc oxide (IGZO), indium tin oxide (ITO), and indium zinc oxide (IZO) ([0040]).
Response to Arguments
Applicant's arguments filed October 14, 2025 have been fully considered but they are not persuasive.
On pages 5-8 of applicants remarks, applicant appears to argue that Boyle et al Fig. 10 does not teach applicant’s amended claim 1 limitations.
Examiner respectfully points out that Fukuzumi et al Figure 8 teaches applicant’s amended claim limitation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./ Examiner, Art Unit 2815