Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Chinese Patent Application No. 202210603709.5, filed May 30, 2022.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed November 19, 2025. Claims 1-2, 4, 11, 15, and 20 are amended. Claims 3, 9-10, and 18-19 are cancelled. The Examiner notes that claims 1-2, 4-8, 11-17, and 20 are examined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-8, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yuzawa (US 2005/0127522 A1).
With respect to claim 1, Yuzawa teaches in Fig. 17 and embodiments of Figs. 18-19, Figs. 20-21, and/or Figs. 22-23:
A semiconductor structure (electronic device 2), comprising:
a first semiconductor layer (first substrate 50) and a second semiconductor layer (second substrate 70) bonded to each other,
wherein the first semiconductor layer (50) comprises a plurality of first redistribution lines (first wires 64) and a first metal pad (first lands 62) connected to each of the first redistribution lines (para. 95 “first wires 64 that are respectively drawn out from the first lands 62”),
and each of the first redistribution lines (64) has a first projection length on a bonding surface (surface where 62 and 82 meet) of the first semiconductor layer and the second semiconductor layer,
wherein the second semiconductor layer (70) comprises a plurality of second redistribution lines (second wires 84) and a second metal pad (second land 82) connected to each of the second redistribution lines (84),
each of the second redistribution lines (84) has a second projection length on the bonding surface,
and the first projection length is different from the second projection length (see Fig. 19, 21, and/or 23, each first wire 64 and its corresponding second wire 84 have different lengths),
and wherein each of the plurality of first redistribution lines is electrically connected to a respective one of the plurality of second redistribution lines through the first metal pad and the second metal pad (para. 97 “the first land 62 and the second land 82 are placed opposite to each other so that they may overlap lengthwise and whereby electrically connected.”),
and a sum of projection lengths of each of the plurality of first redistribution lines and a respective one of the plurality of second redistribution lines on the bonding surface has a same value (see Fig. 19, combined length of bonded wires are the same),
and each of a plurality of first metal pads (62) is bonded with a respective one of a plurality of second metal pads (82) to form a respective one of a plurality of bonding pads (para. 97),
and the plurality of bonding pads (82 and 62 bonded together) are distributed in a ladder shape on the bonding surface (see Fig. 19, 21, and/or 23).
With respect to claim 2, Yuzawa further teaches:
Wherein projection lengths of any two adjacent first redistribution lines (64) on the bonding surface are different, or projection lengths of any two adjacent second redistribution lines (84) on the bonding surface are different (see Fig. 20),
With respect to claim 4, Yuzawa further teaches:
wherein the plurality of first redistribution lines are cyclically arranged in a present arrangement manner (see Fig. 22, the pattern of lines repeats), and
wherein the preset arrangement manner comprises: first projection lengths of the plurality of first redistribution lines being sequentially increased (see Fig. 22, from left to right the lengths of 64 first increases), the first projection lengths being sequentially decreased (after increasing the lengths decrease), the projection lengths being firstly increased and then decreased (starting on the right side moving left the line lengths increases and then decreases), and the first projection lengths being firstly decreased and then increased (increases and decreases are cyclical so starting at a spot where length is maximum and moving right or left results in decreased and then increased)
With respect to claim 5, Yuzawa further teaches:
wherein as the first projection lengths of the plurality of first redistribution lines on the bonding surface are sequentially decreased, second projection lengths of the plurality of second redistribution lines corresponding to the plurality of first redistribution lines on the bonding surface are sequentially increased. (the total length is the same, so when the length of 64 increases, 84 decreases and vice versa)
With respect to claim 6, Yuzawa further teaches:
wherein as the first projection lengths of the plurality of first redistribution lines on the bonding surface are sequentially increased, second projection lengths of the plurality of second redistribution lines corresponding to the plurality of first redistribution lines on the bonding surface are sequentially decreased. (the total length is the same, so when the length of 64 increases, 84 decreases and vice versa)
With respect to claim 7, Yuzawa further teaches:
wherein as the first projection lengths of the plurality of first redistribution lines on the bonding surface are firstly increased and then decreased, second projection lengths of the plurality of second redistribution lines corresponding to the plurality of first redistribution lines on the bonding surface are firstly decreased and then increased. (the total length is the same, so when the length of 64 increases, 84 decreases and vice versa)
With respect to claim 8, Yuzawa further teaches:
wherein as the first projection lengths of the plurality of first redistribution lines on the bonding surface are firstly decreased and then increased, second projection lengths of the plurality of second redistribution lines corresponding to the plurality of first redistribution lines on the bonding surface are firstly increased and then decreased. (the total length is the same, so when the length of 64 increases, 84 decreases and vice versa)
With respect to claim 15, Yuzawa teaches in Fig. 17 and embodiments of Figs. 18-19, Figs. 20-21, and/or Figs. 22-23:
A method for forming a semiconductor structure (electronic device 2), comprising:
providing a first semiconductor layer (first substrate 50) and a second semiconductor layer (second substrate 70),
forming a plurality of first redistribution lines (first wires 64) in the first semiconductor layer (50),
wherein each of the first redistribution lines (64) has a first projection length on a bonding surface (surface where 62 and 82 meet) of the first semiconductor layer and the second semiconductor layer,
forming a plurality of second redistribution lines (second wires 84) in the second semiconductor layer (70),
wherein each of the second redistribution lines (84) has a second projection length on the bonding surface,
and the first projection length is different from the second projection length (see Fig. 19, 21, and/or 23, each first wire 64 and its corresponding second wire 84 have different lengths),
a sum of projection lengths of each of the plurality of first redistribution lines (64) and a respective second one of the plurality of second redistribution lines (84) on the bonding surface has a same value (see Fig. 19, 21, and/or 23, the combined length is the same for each pair of wires)
and wherein each of the plurality of first redistribution lines is electrically connected to a respective one of the plurality of second redistribution lines through the first metal pad and the second metal pad (para. 97 “the first land 62 and the second land 82 are placed opposite to each other so that they may overlap lengthwise and whereby electrically connected.”),
and a sum of projection lengths of each of the plurality of first redistribution lines and a respective one of the plurality of second redistribution lines on the bonding surface has a same value (see Fig. 19, combined length of bonded wires are the same),
forming a first metal pad (lands 62) connected to each of the first redistribution lines (64);
forming a second metal pad (lands 82) connected to each of the second redistribution lines (84);
bonding the first semiconductor layer (50) with the second semiconductor layer (70) to electrically connect the plurality of first redistribution lines (64) to the plurality of second redistribution lines (84) through the first metallic pad (62) and the second metallic pad (82), wherein each of a plurality of first metal pads (62) is bonded with a respective one of a plurality of second metal pads (82) to form a respective one of a plurality of bonding pads (combination of one of 62 and a respective 82 bonded to it) (para. 97 “the first land 62 and the second land 82 are placed opposite to each other so that they may overlap lengthwise and whereby electrically connected.”), and the plurality of bonding pads are distributed in a ladder shape on the bonding surface (see Fig. 19, 21, and/or 23)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yuzawa (US 2005/0127522 A1) in view of Rabkin (US 2022/0068966 A1).
With respect to claim 11, Yuzawa teaches all limitations of claim 1 upon which claim 11 depends. Yuzawa teaches that the interconnect structure may be used in a memory device, but does not teach details of the memory structure and therefore fails to teach:
wherein the first semiconductor layer comprises a memory array,
and the memory array comprises a plurality of wordlines and a plurality of bitlines,
and wherein each of the plurality of wordlines is electrically connected to a respective one of the plurality of first redistribution lines,
and each of the plurality of bitlines is electrically connected to a respective one of the plurality of first redistribution lines.
Rabkin teaches:
wherein the first semiconductor layer (memory die 900) comprises a memory array,
and the memory array comprises a plurality of wordlines and a plurality of bitlines (para. 45 “Each alternating stack can laterally extend along a first horizontal direction (e.g., word line direction) hd1”),
and wherein each of the plurality of wordlines is electrically connected to a respective one of the plurality of first redistribution lines (memory-side metal interconnect structures 980 connected through the word line connection metal lines 96),
and each of the plurality of bitlines is electrically connected to a respective one of the plurality of first redistribution lines (para. 46 “Connection between the bit line and overlying metal interconnect structures can be formed in memory-side bit-line hookup regions 111”)
Yuzawa discloses the claimed invention except for the connection to a memory structure, bitlines, and wordlines. Rabkin teaches that it is known to connect the redistribution lines to bitlines and wordlines as set forth in para. 46 and 51. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect the redistribution lines of Yuzawa to bitlines and wordlines, as taught by Rabkin in order to connect a memory array to a peripheral circuit in order to control and read the array. See MPEP 2144.
With respect to claim 12, Rabkin further teaches:
wherein the second semiconductor layer comprises a peripheral circuit (logic die 700), and the plurality of second redistribution lines (lower logic-side metal interconnect structures) are electrically connected to the peripheral circuit (peripheral circuit 720).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Yuzawa in view of Rabkin as explained above.
With respect to claim 13, Rabkin further teaches:
wherein each of the plurality of wordlines is electrically connected to the peripheral circuit through a respective one of the plurality of first redistribution lines and a respective one of the plurality of second redistribution lines,
and each of the plurality of bitlines is electrically connected to the peripheral circuit through a respective one of the plurality of first redistribution lines and a respective one of the plurality of second redistribution lines. (para. 47 “The logic die 700 includes logic (i.e., driver/peripheral) circuits that can be employed to control operation of the three-dimensional array of memory elements within the memory die 900. Each plane (Q0-Q3) can include logic-side word-line hookup regions 722 and logic-side bit-line hookup regions 711. The logic-side word-line hookup regions 722 includes word line driver circuits and logic-side bonding pads electrically connected to the word line driver circuits. The logic-side bit-line hookup regions 711 includes sense amplifiers and bit line bias circuits (i.e., bit line drivers) and logic-side bonding pads electrically connected to the sense amplifiers and the bit line bias circuits”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Yuzawa in view of Rabkin as explained above.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yuzawa (US 2005/0127522 A1) in view of Rabkin (US 2022/0068966 A1) as applied to claim 13 above and further in view of Lu (US 2015/0130082 A1).
With respect to claim 14, Yuzawa/Rabkin teaches all limitations of claim 13 upon which claim 14 depends. Rabkin further teaches:
wherein the first semiconductor layer comprises a first dielectric layer (upper level dielectric layers 460), and the plurality of first redistribution lines (upper level interconnect structures 460) are located within the first dielectric layer,
wherein the second semiconductor layer comprises a second dielectric layer (lower level dielectric material layers 360), and the plurality of second redistribution lines (metal interconnect structures 380) are located within the second dielectric layer,
Yuzawa/Rabkin fails to teach:
wherein the semiconductor structure further comprises a barrier layer,
and wherein the barrier layer is located between the plurality of first redistribution lines and the first dielectric layer,
between the plurality of second redistribution lines and the second dielectric layer,
between the plurality of bonding pads and the first dielectric layer,
and between the plurality of bonding pads and the second dielectric layer.
Lu teaches in para. 26 about making redistribution lines with a diffusion barrier:
“The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material.”
Modifying Yuzawa/Rabkin with the teachings of Lu such that the conductive parts of the redistribution layer include a diffusion barrier layer teaches:
wherein the semiconductor structure further comprises a barrier layer,
and wherein the barrier layer is located between the plurality of first redistribution lines and the first dielectric layer, between the plurality of second redistribution lines and the second dielectric layer,
between the plurality of bonding pads and the first dielectric layer,
and between the plurality of bonding pads and the second dielectric layer.
Yuzawa modified by Rabkin discloses the claimed invention except for the barrier layer between the conductive parts of the RDL and the dielectric layer. Lu teaches that it is known to fill recesses in a dielectric layer with a diffusion barrier before filling with the conductive features. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yuzawa/Rabkin to include diffusion barrier layers as taught by Lu in order to prevent diffusion of the conductive materials into the dielectric layer. See MPEP 2144.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Yuzawa (US 2005/0127522 A1) as applied to claim 15 above and in view of Lu (US 2015/0130082 A1).
With respect to claim 16, Yuzawa further teaches in Fig. 3B:
wherein the first redistribution line is formed by:
forming a first dielectric layer (reinforcement 21, which may be resin) on a surface of a substrate (substrate 10) of the first semiconductor layer (50);
Yuzawa fails to teach:
etching the first dielectric layer to form a first etching trench;
and filling the first etching trench with metal material to form the first redistribution line.
Lu teaches in para. 26:
etching the dielectric layer to form an etching trench;
and filling the etching trench with metal material to form the redistribution line. (“an etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the dielectric layer corresponding to the exposed portions of the dielectric layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material.”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the undescribed method of forming a redistribution line of Yuzawa for the method that involves filling an etching trench with conductive materials of Lu because they are known equivalents and it would have yielded the predictable result of creating a metallization pattern. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
With respect to claim 17, Yuzawa further teaches:
wherein the second redistribution line is formed by:
forming a second dielectric layer (reinforcement 21 which may be resin) on a surface of a substrate (substrate 10) of the first semiconductor layer (70);
Yuzawa fails to teach:
etching the second dielectric layer to form a second etching trench;
and filling the second etching trench with metal material to form the second redistribution line.
Lu teaches in para. 26:
etching the dielectric layer to form an etching trench;
and filling the etching trench with metal material to form the redistribution line. (“an etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the dielectric layer corresponding to the exposed portions of the dielectric layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material.”)
It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the undescribed method of forming a redistribution line of Yuzawa for the method that involves filling an etching trench with conductive materials of Lu because they are known equivalents and it would have yielded the predictable result of creating a metallization pattern. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yuzawa (US 2005/0127522 A1) as applied to claim 15 above and in view of Chen (US 2015/0171050 A1).
With respect to claim 20, Yuzawa teaches all limitations of claim 15 upon which claim 20 depends. Yuzawa fails to teach:
wherein bonding the first semiconductor layer with the second semiconductor layer to electrically connect the first redistribution line to the second redistribution line comprises:
performing surface activation treatment on a first surface of the first semiconductor layer exposing the first metal pad and a second surface of the second semiconductor layer exposing the second metal pad;
attaching the first surface to the second surface with the first metal pad being aligned to the second metal pad face to face;
and annealing the first semiconductor layer and the second semiconductor layer.
Chen teaches in Fig. 11A:
wherein bonding the first semiconductor layer (first device die 100) with the second semiconductor layer (second device die 200) to electrically connect the first redistribution line (metallization layers 105) to the second redistribution line (metallization layers 205) comprises:
performing surface activation treatment on a first surface of the first semiconductor layer exposing the first metal pad (para. 38 “surface activation module 306 may be a wet cleaning module that performs a wet clean to activate the surface of oxide layer 110”) and a second surface of the second semiconductor layer exposing the second metal pad (para. 39 “A similar surface activation treatment may be applied to a surface of oxide layer 210 as the treatment applied to oxide layer 110”);
attaching the first surface to the second surface (bottom surface of 100 as shown in Fig. 11A) with the first metal pad (conductive pad 118) being aligned to the second metal pad (conductive pad 218) face to face;
and annealing the first semiconductor layer and the second semiconductor layer (para. 41 “a thermal annealing process may be utilized to strengthen the bond between oxide layers 110 and 210 and to additionally bond conductive pads 118 and 218 as illustrated by FIG. 9.”)
Yuzawa discloses the claimed invention except for the surface activation treatment and annealing associated with bonding. Chen teaches that it is known to activate surfaces before bonding and annealing to form the bond. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform a surface activation treatment and annealing, as taught by Chen in order to clean the surfaces and facilitate bonding between the surfaces. See MPEP 2144.
Response to Arguments
Applicant’s arguments, see page 7, filed November 19, 2025, with respect to 112(b) rejections have been fully considered and are persuasive. The 112(b) rejections of claims 4-8 have been withdrawn in view of amendments.
Applicant’s arguments with respect to claims 1 and 15 and their dependents have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakamura (US 2003/0025122 A1) teaches a similar arrangement of data lines to reduce parasitic capacitance, see Figs. 5-6.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897