DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 01/29/2026 has been entered. Applicant's arguments have overcome
the objections to the Claims previously set forth in the Non-Final Office Action dated on 11/06/2025.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Non-Final Reject" filed on 01/29/2026, have been fully considered, the arguments related to the Applicant’s amendment of claim 1: “the power rail structure comprising a rail conductor that is electrically conductive and wherein a lower end of the lower portion is closer than an upper surface of the rail conductor to a lower surface of the power rail structure” are not persuasives and some of them are moot because do not apply to new ground of rejections with a new reference, US 20230154783 A1 to Xie, being used in the current rejection. The Applicant’s arguments related to reference US 20220157957 A1 (Jin) and claim 11: “element 200 in FIG. 4 of Jin does not have a curved shape "toward" elements 120 and 125 in FIG. 4 of Jin”. However, the Applicant’s arguments are not persuasive because the terms “curved” and “toward” have a broad meaning, wherein the lower portion of structure 200 (Jin) has a curved preferential direction toward the power rail structure 120-125 (Jin), see detail below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis
for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 11 is rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Jin et al. (US 20220157957 A1, hereinafter Jin, of the record).
Re: Independent Claim 11, Jin teaches an integrated circuit device comprising:
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Jin’s Figure 4-Annotated.
a power rail structure (120-125 a power rail line including an insulation layer 125 in [0026, 0044], Figs. 3,4); and
a transistor (140-130 source/drain 130 as part of gate 130 in [0026], Figs. 3,4) and a power contact structure (200 a power rail contact plug in [0026], Figs. 3,4) on the power rail structure (120-125),
wherein the transistor (140-130) comprises a source/drain region (140, Fig. 3,4), the power contact structure (200) electrically connects the power rail structure (120-125) to the source/drain region (140), and
an interface (interface, Fig. 4-Annotated) between the power contact structure (200) and the power rail structure (120-125) is curved (the end of the 200 is curved toward 120-125, Fig. 4-Annotated) toward the power rail structure (120-125).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jin in view of Smith et al. (US 20240047342 A1, hereinafter Smith, of the record).
Re: Claim 12, Jin discloses the integrated circuit device of Claim 11, wherein the power contact structure comprises a contact conductor (200 made of conductive materials in [0064], Jin)
Jin does not expressly disclose a contact barrier layer on an outer surface of the contact conductor, and the interface between the power contact structure and the power rail structure is devoid of the contact barrier layer.
However, in the same semiconductor device field of endeavor, Smith discloses a contact barrier layer (215b barrier film made of titanium nitride in [0031,0039], Fig. 2) on an outer surface of the contact conductor (211 via structure in [0045], Fig. 2), and the interface between the power contact structure (215b-211) and the power rail structure (210 power rail in [0045]) is devoid of the contact barrier layer (the barrier film 215b can cover or not cover the interface between the via structure 211 and the embedded power rail 210 in [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Smith’s feature of a contact barrier layer on an outer surface of the contact conductor, and the interface between the power contact structure and the power rail structure is devoid of the contact barrier layer to Jin’s device to include a selectivity of the deposition process of the barrier layer ([0045], Smith).
Re: Claim 13, Jin modified by Smith discloses the integrated circuit device of Claim 12, wherein the contact barrier layer (215b, Smith) comprises a metal nitride layer (215b barrier film made of titanium nitride in [0031], Fig. 2, Smith).
Claim(s) 14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jin in view of Xie et al. (US 20230207553 A1, hereinafter Xie-7553, of the record).
Re: Claim 14, Jin discloses the integrated circuit device of Claim 11,
Jin does not expressly disclose further comprising a back- end-of-line (BEOL) structure including a conductive wire on the transistor, wherein the transistor is between the BEOL structure and the power rail structure.
However, in the same semiconductor device field of endeavor, Xie-7553 discloses
a back- end-of-line (BEOL) structure (170 BEOL interconnect structure in [0047], Fig. 1A) including a conductive wire (170 having multilevel of wirings in [0047]) on the transistor (120-1,-2,-3,-4 plurality of nanosheet FET devices 120-1, 120-2, 120-3, and 120-4 in [0044], Fig. 1A), wherein the transistor (120-1,-2,-3,-4) is between the BEOL structure (170) and the power rail structure (190 backside power delivery structure in [0049], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Xie-7553’s feature of further comprising a back- end-of-line (BEOL) structure including a conductive wire on the transistor, wherein the transistor is between the BEOL structure and the power rail structure to Jin’s device for using via structures which connect the wiring between different wiring levels ([0047], Xie).
Claim(s) 1,5-9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jin et al. (US 20220157957 A1, hereinafter Jin, of the record) in view of Xie et al. (US 20230154783 A1, hereinafter Xie).
Re: Independent Claim 1, Jin discloses an integrated circuit device comprising:
a lower insulating structure (115 an isolation structure in [0031], Fig. 4);
a transistor (140-130 source/drain 130 as part of gate 130 in [0026], Figs. 3,4) on the lower insulating structure (115), the transistor comprising a source/drain region (140, Fig. 3,4);
a power rail structure (120-125 a power rail line including an insulation layer 125 in [0026, 0044], Figs. 3,4) in (Fig. 4) the lower insulating structure (115), the power rail structure (120-125) comprising a rail conductor (120) that is electrically conductive ([0036]); and
a power contact structure (200 a power rail contact plug in [0026], Figs. 3,4) that is on the power rail structure (120-125) and electrically connects the source/drain region (140) to the power rail structure (120-125),
wherein the power contact structure (200) comprises a lower portion (200-L a lower portion of 200 in [0026], Fig. 4-Annotated) that is in the power rail structure (120-125).
Jin does not expressly disclose wherein a lower end of the lower portion is closer than an upper surface of the rail conductor to a lower surface of the power rail structure.
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Jin’s Figure 12-Annotated.
However, in the same semiconductor device field of endeavor, Xie discloses a lower end (Fig.12-Annotated) of the lower portion (lower-142a a lower portion of contact 142a in [0037], Fig.12-Annotated) is closer than an upper surface (upper-158 Fig.12-Annotated) of the rail conductor (158 a BPR in [0041], Fig.12) to a lower surface (Fig.12-Annotated) of the power rail structure (158-166 a BPR 158 and metal adhesion liner in [0041], Fig.12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the Jin’s power rail structure to have a lower end of the lower portion is closer than an upper surface of the rail conductor to a lower surface of the power rail structure as disclosed by Xie’s device to provide significantly lower resistance through the power rail without driving any negative impact to either via resistance or capacitance in the BEOL ([0003], Xie).
Re: Claim 5, Jin modified by Xie discloses the integrated circuit device of Claim 1, wherein the lower portion (200-L, Jin) of the power contact structure (200, Jin) has a convex surface (Fig. 4-Annotated, Jin).
Re: Claim 6, Jin modified by Xie discloses the integrated circuit device of Claim 1, further comprising a first active region (110-1 a channel structure in [0026], Fig. 4-Annotated, Jin) and a second active region (110-2 a channel structure in [0026], Fig. 4-Annotated, Jin) in the lower insulating structure (115, Jin), wherein the source/drain region (140, Jin) is on the first active region (110-1, Jin), a portion of the lower insulating structure (Fig. 4-Annotated, Jin) separates the first active region (110-1, Jin) from the second active region (110-2, Jin), and the power contact structure (200, Jin) extends through the portion of the lower insulating structure (115, Jin).
Re: Claim 7, Jin modified by Xie discloses the integrated circuit device of Claim 6, wherein the first (110-1, Jin) and second (110-2, Jin) active regions are spaced apart from each other in a first direction (x-direction, Fig. 4-Annotated, Jin), and the power rail structure (120-125, Jin) extends in a second direction (y-direction, Fig. 4-Annotated, Jin) that is perpendicular to the first direction (x-direction, Jin).
Re: Claim 8, Jin modified by Xie discloses the integrated circuit device of Claim 6, wherein the source/drain region (140, Jin) comprises a lower surface facing the first active region (110-1, Jin) and an upper surface opposite the lower surface, and the integrated circuit device further comprises a source/drain contact (210 a source/drain contact layer in [0026], Figs. 3,4, Jin) that contacts (Fig. 4-Annotated, Jin) the upper surface of the source/drain region (140, Jin) and the power contact structure (200, Jin).
Re: Claim 9, Jin modified by Xie discloses the integrated circuit device of Claim 1, wherein the source/drain region (140, Jin) comprises a lower surface facing the lower insulating structure (115, Jin) and an upper surface opposite the lower surface (Fig. 4-Annotated, Jin), and the power contact structure (200, Jin) contacts (200 electrically contact 140, Fig. 4-Annotated, Jin) the lower surface of the source/drain region (140, Jin).
Claim(s) 2-4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jin in view of Xie and further in view of Smith et al. (US 20240047342 A1, hereinafter Smith, of the record).
Re: Claim 2, Jin modified by Xie discloses the integrated circuit device of Claim 1, wherein the power contact structure comprises a contact conductor (200 made of conductive materials in [0064], Jin)
Jin modified by Xie does not expressly disclose a contact barrier layer on an outer surface of the contact conductor, and the lower portion of the power contact structure is devoid of the contact barrier layer.
However, in the same semiconductor device field of endeavor, Smith discloses a contact barrier layer (215b barrier film made of titanium nitride in [0031,0039], Fig. 2) on an outer surface of the contact conductor (211 via structure in [0045], Fig. 2), and the lower portion of the power contact structure (215b-211) is devoid of the contact barrier layer (the barrier film 215b can cover or not cover the interface between the via structure 211 and the embedded power rail 210 in [0045]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Smith’s feature of a contact barrier layer on an outer surface of the contact conductor, and the lower portion of the power contact structure is devoid of the contact barrier layer to the combination of Jin and Xie to include a selectivity of the deposition process of the barrier layer ([0045], Smith).
Re: Claim 3, Jin modified by Xie and Smith discloses the integrated circuit device of Claim 2, wherein the contact barrier layer (215b, Smith) comprises a metal nitride layer (215b barrier film made of titanium nitride in [0031], Fig. 2, Smith).
Re: Claim 4, Jin modified by Xie and Smith discloses the integrated circuit device of Claim 2, wherein a portion of the contact conductor (200, Jin) in the power contact structure contacts the power rail structure (120-125, Jin).
Claim(s) 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jin in view of Xie and further in view of Xie et al. (US 20230207553 A1, hereinafter Xie-7553, of the record).
Re: Claim 10, Jin modified by Xie discloses the integrated circuit device of Claim 1,
Jin modified by Xie does not expressly disclose further comprising a back- end-of-line (BEOL) structure including a conductive wire on the transistor, wherein the transistor is between the BEOL structure and the power rail structure.
However, in the same semiconductor device field of endeavor, Xie-7553 discloses
a back- end-of-line (BEOL) structure (170 BEOL interconnect structure in [0047], Fig. 1A) including a conductive wire (170 having multilevel of wirings in [0047]) on the transistor (120-1,-2,-3,-4 plurality of nanosheet FET devices 120-1, 120-2, 120-3, and 120-4 in [0044], Fig. 1A), wherein the transistor (120-1,-2,-3,-4) is between the BEOL structure (170) and the power rail structure (190 backside power delivery structure in [0049], Fig. 1A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Xie-7353’s feature of further comprising a back- end-of-line (BEOL) structure including a conductive wire on the transistor, wherein the transistor is between the BEOL structure and the power rail structure to the combination of Jin and Xie for using via structures which connect the wiring between different wiring levels ([0047], Xie-7353).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ju et al. (US 20210305428 A1) teaches “FINFET DEVICES WITH BACKSIDE POWER RAIL AND BACKSIDE SELF-ALIGNED VIA”. This document is related to a semiconductor structure including a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
Xie et al. (US 20230178433 A1) teaches “BURIED POWER RAIL AT TIGHT CELL-TO-CELL SPACE”. This document is related to a semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA M RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 8:00am-5:00pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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