DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 12/5/2025 have been entered and considered. The amendments to claims 1, 8, and 10 have been acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claim recites a ratio between the thickness of the metal film and the contact hole depth into the silicon substrate. As recited in claim 1, the metal film is first deposited, then undergoes a first reverse sputtering treatment, and then a second reverse sputtering treatment. It is not clear at which step one is to compare the thickness of the metal film: upon deposition or after the first sputtering step before it is processed into the metal layer. For purposes of examination, the thickness of the metal film will be considered as the thickness when first deposited.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 7-10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gregoire US 20130065392 A1 (hereinafter referred to as Gregoire), in view of Grunow et al. US 20060024939 A1 (hereinafter referred to as Grunow).
Regarding claim 1, Gregoire teaches
A method for manufacturing a semiconductor structure (method of forming silicides in “transistor 10 of FIG. 1” para. 0040 FIG. 2-8), comprising:
providing a substrate (“silicon substrate (Si) 12” with “insulator layer 20” formed above, para. 0037 FIG. 1-8), and forming contact holes in the substrate (“holes 22,24” para. 0038);
depositing a metal at a bottom of each contact hole (“a nickel and platinum alloy, is then deposited for a first time into hole 24” para. 0043 FIG. 4), and performing a reverse sputtering treatment to form a metal layer (a bombarding step “to sputter the alloy located at the bottom of hole. The sputtered alloy then deposits on lateral wall 38 of hole 24, and especially on low portion 40 of lateral wall 38” para. 0044 FIG. 5); in the reverse sputtering treatment, metal atoms or metal ions are sputtered onto at least a part of a side wall of each contact hole (“The sputtered alloy then deposits on lateral wall 38 of hole 24, and especially on low portion 40 of lateral wall 38”); and
performing an annealing treatment, to cause the substrate reacts with the metal layer to form a metal silicide layer (“the forming of silicide, especially at the bottom of hole 24, for example, by performing an anneal” 14 so that “a silicide layer is formed at the bottom of the hole” para. 0046),
wherein
the depositing the metal at the bottom of the contact hole, and performing the reverse sputtering treatment to form the metal layer, comprises:
depositing the metal at the bottom of the contact hole to form a metal film (“nickel and platinum alloy” at bottom of “hole 24”); and
after the metal film is formed, performing the reverse sputtering treatment to the metal film (bombarding step “to sputter the alloy located at the bottom of the hole 24”);
However, Gregoire fails to teach wherein the reverse sputtering treatment comprises a first reverse sputtering treatment and a second reverse sputtering treatment which are performed in sequence; and a bias power of the second reverse sputtering treatment is greater than that of the first reverse sputtering treatment.
Nevertheless, Grunow teaches
wherein
the reverse sputtering treatment comprises a first reverse sputtering treatment (small resputtering component during low AC bias power deposition of “seed layer 126”, para. 0019 FIG. 1B) and a second reverse sputtering treatment (resputtering of material during high AC bias power deposition of more “seed layer 126” material, para. 0020 FIG. 1C) which are performed in sequence (“the low AC bias step is performed before the high AC bias step” para. 0029); and
a bias power of the second reverse sputtering treatment is greater than that of the first reverse sputtering treatment (low AC bias power step is at 0-600W and high AC bias power step is at 300-1200w, para. 0019-0020).
Gregoire and Grunow teach the deposition of metal into a hole and the use of reverse sputtering to obtain hole sidewall coverage. In Grunow, the low AC bias step deposits some “seed layer 126” on the bottom and sidewalls of the trench and the high AC bias step helps obtain improved sidewall coverage of the trench but may expose the bottoms and corners of the trench (para. 0020). A subsequent zero AC bias power step then covers portions that have been excessively reverse sputtered and achieves a “seed layer 126” with adequate coverage on the whole trench (para. 0021 FIG. 1D). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the low AC and high AC power steps of deposition and resputtering can be applied to the alloy in Gregoire to obtain a more uniform coverage of the alloy at the bottom of “hole 24”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Gregoire with the reverse sputtering treatment from Grunow. The first and second reverse sputtering steps, followed by a deposition step, achieve improved coverage of metal material along the bottom and sidewalls of the contact hole.
Regarding claim 7, Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 1, wherein the bias power of the first reverse sputtering treatment is 100-200 W (low AC bias power step is at 0-600W, para. 0019), and the bias power of the second reverse sputtering treatment is 200-300 W (high AC bias power step is at 300-1200W, para. 0020).
Regarding claim 8, Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 1, wherein after the first reverse sputtering treatment and before the second reverse sputtering treatment, the method further comprises: forming a first repairing layer on a surface of the metal film (the examiner understands that the first repairing layer is the sputtered and deposited “nickel and titanium alloy” after applying the first low AC bias power step to the first deposited “nickel and platinum layer” in Grunow, analogous to how the “thin seed layer 126” is formed in FIG. 1A of Grunow., para. 0019).
Regarding claim 9, Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 8, wherein after the second reverse sputtering treatment, the method further comprises: forming a second repairing layer which covers the first repairing layer, wherein the metal film, the first repairing layer and the second repairing layer form the metal layer (the examiner understands that the second repairing is the sputtered and deposited “nickel and titanium alloy” after applying the high AC bias power step from Grunow, analogous to the further “seed layer 126” material formed in FIG. 1C in Grunow).
Regarding claim 10, Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 5, wherein the substrate comprises a stack of a silicon substrate (“silicon layer 16” para. 0042) and a dielectric layer (“insulator layer 20” para. 0037);
each contact hole passes through the dielectric layer and extends into the silicon substrate (“hole 24” includes a portion within “silicon layer 16” with a depth of up to 10nm, para. 0042 FIG. 3).
However, Gregoire, modified by Grunow, fail to teach a ratio of a thickness of the metal film to a depth of the contact hole in the silicon substrate is 1/3-3/7.
Nevertheless, Gregoire teaches in para. 0007 that “the quality of the ohmic contact especially depends on the nickel silicide volume between the silicon and the metal contact”; larger volumes and surfaces areas lead to greater ohmic contact (para. 0009 and 0048). Silicon is sputtered onto the “lateral wall 38” (para. 0042). The examiner understands that the amount of silicon on the “lateral sidewall 38” depends on the amount that “silicon layer 16” is etched; if more of “silicon layer 16” is etched”, more can be sputtered onto “lateral sidewall 38” of “hole 24”. The examiner further understands that the more silicon there is available, the greater the amount of silicide can be formed after depositing “nickel and platinum alloy” and annealing. This means that the depth of “hole 24” in “silicon layer 16” is a result effective variable: the more silicon is etched and reverse sputtered, the more silicide can be formed in “hole 24”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the depth of “hole 24” in “silicon layer 16” can be set based on the desired amount of silicide to be formed. Even though a thickness of the first deposited “nickel and platinum alloy” is not given, it is understood the claimed range of ratios can be met depending on the desired depth of the “hole 24” in “silicon layer 16”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the depth of the contact hole is a result effective variable that helps determine the amount of possible silicide to be formed. Greater hole depths provide more reverse sputtered silicon on the sidewalls of the hole.
Regarding claim 14, Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 1, wherein after the annealing treatment, the method further comprises: forming a contact layer filled in each contact hole (“filling hole 24 with metal 34 (FIG. 8), for example, to form an electric contact” 16 FIG. 8), with the contact layer covering the metal silicide layer (“metal 34” covers the silicide layer, as seen in FIG. 8).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Gregoire, modified by Grunow, as applied to claim 1, in view of Lin et al. US 20170077032 A1 (hereinafter referred to as Lin).
Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 1 but fails to teach wherein before the annealing treatment, the method further comprises: forming a barrier layer on the side wall of each contact hole and a surface of the metal layer.
Nevertheless, Lin teaches
wherein before the annealing treatment, the method further comprises: forming a barrier layer on the side wall of each contact hole and a surface of the metal layer (“barrier layer 240” is formed, then annealing is performed, para. 0036-0037 FIG. 2D-2E).
Gregoire, modified by Grunow, and Lin teach the formation of silicide layers at bottoms of contact holes. Lin includes a “barrier layer 240” so that the subsequently formed “conductor 260” does not diffuse into the “dielectric layer 220” (para. 0036). Metal diffusion into the dielectric body deteriorates the performance of the device. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “barrier layer 240” can prevent metal diffusion into the surrounding dielectric so reliability is maintained.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught in Gregoire and Grunow with the barrier layer formation taught in Lin. A barrier layer covering sidewalls of the contact hole protect against metal diffusion into the substrate.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Gregoire, modified by Grunow, as applied to claim 1 above, in view of Sakurai et al. US 20010052648 A1 (hereinafter referred to as Sakurai), further in view of Cabral, Jr. et al US 20040123922 A1 (hereinafter referred to as Cabral).
Gregoire, modified by Grunow, teaches the method for manufacturing the semiconductor structure of claim 1 but fails to teach wherein the annealing treatment comprises first annealing treatment and second annealing treatment; the first annealing treatment is performed to the metal layer to form an initial metal silicide layer, and the second annealing treatment is performed to the initial metal silicide layer to form the metal silicide layer; and a temperature of the first annealing treatment is smaller than that of the second annealing treatment.
Nevertheless, Sakurai teaches
wherein the annealing treatment comprises first annealing treatment (“first annealing is performed” after depositing “metal layer 7”, para. 0075 FIG. 10) and second annealing treatment (“second annealing is performed” para. 0076); the first annealing treatment is performed to the metal layer to form an initial metal silicide layer (the first annealing “causes reaction between Si and Co in regions where metal layer 7 is in contact with gate electrode layer 6 and source/drain regions 4 so that CoSi layers 7aand 7b are formed′” para. 0076), and the second annealing treatment is performed to the initial metal silicide layer to form the metal silicide layer (“second annealing is performed. This changes the composition of CoSi layers 7aand 7b so that silicide layers 7aand 7b made of CoSi.sub.2 are formed” para. 0076); and
a temperature of the first annealing treatment is smaller than that of the second annealing treatment (“first annealing is performed at a relatively low temperature for a short time, and the second annealing is performed at a relatively high temperature for a short time” para. 0077).
Gregoire, modified by Grunow, and Sakurai teach the formation of silicide layers at the bottoms of contact structures. The second anneal in Sakurai modifies the “silicide layers 7a and 7b” of CoSi into CoSi.sub.2.). As evidenced in para. 0024 of Kawamura US 20060125022 A1, CoSi.sub2 has a lower resistance than CoSi. Furthermore, Cabral teaches a case where the metal precursor is Nickel and that “low temperature anneals form metal rich silicide phases” and “when a metal rich phase is produced a second higher temperature anneal is required to form the low resistivity Ni monosilicide.” (Cabral para. 0046). Second annealing processes for cobalt silicide and nickel silicide modify the composition of the silicide layer, reducing the resistivity. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the second anneal process at a higher temperature improves the performance of the conductive contact structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught between Gregoire and Grunow with the elevated second anneal temperature taught in Sakurai and Cabral. Performing the second annealing treatment at a higher temperature than the first anneal modifies the composition of the silicide layer into one of lower resistivity.
Regarding claim 13, Gregoire, modified by Grunow, Sakurai, and Cabral, teach the method for manufacturing the semiconductor structure of claim 12, wherein after the first annealing treatment and before the second annealing treatment, the method further comprises: removing unreacted metal layer (“The unreacted portions of the metal layer 7 are removed by mixed acid. Thereafter, second annealing is performed.” Para. 0076).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898