Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 6 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The “thermally conducting material” lacks antecedent basis. It is assumed the “thermally conducting solder” was intended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-9, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pat. Pub. No. 20220068906 to Chava et al. (Chava) in view of U.S. Pat. Pub. No. 20120139097 to Jin et al. (Jin).
Regarding Claims 1 and 19, Chava teaches a packaged semiconductor integrated circuit device comprising:
a die 104 comprising a first back-end-of-line region 106 coupled to a first side of a front-end-of-line region 114, a second back-end-of-line region 108 coupled to a second side of the front-end-of-line region , but does not explicitly teach a thermally conducting solder at least partially surrounding perimeter sidewalls of the front-end-of-line region, the first back-end-of-line region, and the second back-end-of-line region; and
a cover that conceals the die, the cover comprising a lateral heatsink portion in conduction connection with a sidewall of the thermally conducting solder.
However, in analogous art, Jin teaches a thermally conducting solder (142, described as metal paste, [0053], reading on solder) at least partially surrounding perimeter sidewalls of the front-end-of-line region, the first back-end-of-line region, and the second back-end-of-line region (surrounds entirety of die and interposer; analogous to 104/106/108 of Chava); and
a cover 30 that conceals the die, the cover comprising a lateral heatsink portion in conduction connection with a sidewall of the thermally conducting solder (heat sink 30 thermally coupled to 142).
It would have been obvious to the person of ordinary skill in the art before the time of filing to include the teaching of Jin to sink heat from the device of Chava.
Regarding Claims 2 and 20, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 1, wherein the first back-end-of-line region provides signal routing for one or more active devices in the front-end-of-line region, and wherein the second back-end-of-line region provides a power delivery structure for the one or more active devices in the front-end-of-line region [0028].
Regarding Claim 3, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 2, further comprising:
a carrier 116; and
a plurality of solder balls 110 that connect the carrier and the second back-end-of-line region.
Regarding Claim 4, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 3, wherein a reflow temperature of the thermally conducting solder is higher than a reflow temperature of the plurality of solder balls (although not explicit in the combination of Chava and Jin, the person of ordinary skill having the benefit of Chava and Jin would readily appreciate that the reflow of the metal paste/ solder 142 of Jin would have to have a higher reflow than the solder balls of Chava because if they were equal, the structure 142 of Jin would collapse; it is further worth nothing Jin shows similar solder balls 110 which would have to have a lower reflow temperature than 142).
Regarding Claim 7, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 1, wherein the lateral heatsink portion is in direct conduction connection with the sidewall of the thermally conducting solder (see Fig. 1 of Jin).
Regarding Claim 8, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 1, wherein a thermal interface material is between the lateral heatsink portion and the sidewall of the thermally conducting solder (Jin, [0056]).
Regarding Claim 9, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 1, wherein a width of the thermally conducting solder is 50 um or more (Jin, [0051], the thickness of 142 would directly affect its heat sinking capability, making it a result effective variable that may be optimized by the person of ordinary skill, see MPEP 2144.05(II)(B)).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chava and Jin as applied to claim 4 above, and further in view of U.S. Pat. Pub. No. 20230130923 to Liao.
Regarding Claim 5, Chava and Jin teach the packaged semiconductor integrated circuit device of claim 4, further comprising a molding layer between the thermally conducting solder and the front-end-of-line region (Jin shows a mold 136 surrounding the entirety of die/RDL 130, analogous to 106/114/108 of Chava) but do not explicitly teach that the mold is oxide. However, in analogous art, Liao teaches in [0030] that resin (non-limiting example of Jin) and oxide are obvious variants (MPEP 2144.06-07) for a heat dissipating package (taught by Liao throughout).
Regarding Claim 6, Chava, Jin and Liao teach the packaged semiconductor integrated circuit device of claim 5, further comprising an oxide layer between (i) the thermally conducting solder and (ii) the front-end-of-line region, the first back-end-of-line region, and the second back-end-of-line region (see above reasoning, mold 136 completely wraps the ICs of Jin as it would wrap the IC of Chava in combination).
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812
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