Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant overcame some but not all of the Examiner’s previous claim objections. Claim 25 is objected to because of the following informalities:
Claim 25 further recites, “and adjacent two of the first gate regions are spaced apart from each other by one of the portions of the well region…” The Examiner believes this recitation should read, “and two adjacent
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 40 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
This is because Claim 40 includes the limitation, “wherein the top surfaces of the first gate regions and the top surface of the first well region adjoin the top surface of the substrate”. The Examiner finds this limitation to be indefinite because Applicant’s intent is not clear to the Examiner. The Examiner believes and interprets the limitation to be the same as the limitation in claim 25, “wherein the first gate semiconductive regions adjoin a top surface of the substrate”. However the Examiner could interpret the claim to mean that the top surfaces of the first gate regions, the top surface of the well region, and the top surface of the substrate are all directly physically connected. The Examiner doesn’t believe this interpretation to be correct as such a feature is not demonstrated in any of the figures of Applicant’s elected species. In particular, claim 14 upon which claim 40 depends, is drawn to Applicant’s FIG. 7A. As can be seen in annotated FIG. 7A below, the top surface of the first gate semiconductive regions and the top surface of the substrate are not directly physically connected.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 40-42 are rejected under 35 U.S.C. 103 as being unpatentable over Harada et al US 20030168704 A1 and in view of Saito et al US 20160104724 A1 in further view of Endo US 5828101 A. Harada et al and Saito et al will be referenced to as Harada and Saito respectively henceforth.
Regarding Claim 14,
Harada teaches:
“A semiconductor device, comprising (FIG. 6):
a substrate (SiC substrate 1, p-type epitaxial layer 2, [0052]); a first source region (n-type source region 5, [0053]), a first drain region (n-type drain region layer 9, [0043]) formed in the first well region along a first direction (FIG. 6: 5 and 9 are formed in n-type epitaxial layer 3A along a horizontal direction. 3A is a well region.), wherein the first source and drain regions and the first well region have a same conductive type (5, 9, and 3A are all n-type.); and
a plurality of first gate regions formed in the first well region between the first source region and the first drain region ([0073], annotated FIG. 6 #5: the plurality of first gates are a portion of the gate layer 7A. The plurality of first gates are between 5 and 9.), wherein the first gate regions are located along a second direction perpendicular to the first direction (annotated FIG. 6 #5: the plurality of first gates are located along an into the page direction.), each of the first gate regions extends from a top surface of the first well region to a bottom surface of the first well region ([0073-0076], annotated FIG. 6 #5: 7L reaches 2 which is below 3A. 7A has a thickness dn which is the same thickness as layer 3A. This thickness is a height of each gate in the plurality of first gates.) wherein multiple channel regions are formed between the first gate regions ([0005], [0073], [0076]: The channel is between 3A and the gate layer 7A. When 7A is put in reverse bias, current through the channel is cut off by the extending of the depletion layer.).”
Harada doesn’t substantially teach:
“a first well region formed in a top surface of the substrate”
However, Saito teaches:
“a first well region formed in a top surface of the substrate (Saito: [0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701.);”
Neither Harada or Saito substantively teach:
“a plurality of top surfaces of the first gate regions are encircled and spaced apart from each other by the top surface of the first well region;”
However Endo teaches:
“a plurality of top surfaces of the first gate regions are encircled and spaced apart from each other by the top surface of the first well region (Endo, col 8 lines 28-37, FIG. 17: The gate electrodes 7 are surrounded by n-type semiconductor 2. The gate electrodes may be made of doped polysilicon and are therefore semiconductive.);”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Harada is modifiable in view of Saito and Endo.
This is because surrounding the channels by a p-type well region may reduce unwanted current flow from the source to a lower substrate. An advantage of removing these current flows is that greater precision of source to drain current may be acquired. (US 20110233562 A1: [0159]) In Harada, the n-well region is part of the channel. By forming the n-type well within a top surface of a p-well region, the advantages of US 20110233562 may be attained.
This is further because one of ordinary skill in the art would recognize that a large accumulation layer is beneficial. An accumulation layer has a low on resistance (Endo: col 9 lines 3-21, FIG. 17). By incorporating a long gate length, the length of an accumulation layer is increased (Endo: col 12 lines 5-22, FIG. 17). This results in a total resistance being decreased. One of ordinary skill in the art would find this to be beneficial because a low resistance results in the generation of less heat which can damage a semiconductor device’s properties.
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Regarding Claim 40,
Harada/Saito/Endo teaches:
“The semiconductor device of claim 14, wherein the top surfaces of the first gate regions and the top surface of the first well region adjoin the top surface of the substrate (Harada: [0073-0076], annotated FIG. 6 #5: 7L reaches 2 which is below 3A.). ”
Regarding Claim 41,
Harada/Saito/Endo teaches:
“The semiconductor device of claim 14, wherein the first well region has a plurality of portions, and each of the portions is between adjacent two of the first gate regions (Harada: FIG. 6: Each portion in the plurality of portions is between each of the first well regions.)”
Regarding Claim 42,
Harada/Saito/Endo teaches:
“The semiconductor device of claim 14, wherein the top surfaces of the first gate regions are substantially level with a top surface of the source region (Harada: annotated FIG. 6 #5).”
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Harada/Saito/Endo as applied to claims 14, and 40-42 above, and further in view of Fujikawa et al US 20090315082 A1. Fujikawa et al will be referenced to as Fujikawa henceforth.
Regarding Claim 15,
Harada/Saito/Endo teaches:
“The semiconductor device of claim 143,wherein a spacing between any two adjacent first gate regions are the same (Harada: FIG. 6: The length of 7H between the first gate regions is constant.),”
Harada/Saito/Endo doesn’t substantially teach:
“the spacing ranges from 0.5 µm to 2.5 µm.”
However, Fujikawa teaches:
“the spacing ranges from 0.5 µm to 2.5 µm (Fujikawa: [0354-0356], FIG. 58: semiconductor layer 83 separates gate electrodes 88A and 88B by 0.5 µm to 1 µm which is within the range.).”
It would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Harada/Saito/Endo is modifiable in view of Fujikawa.
This is because Harada/Saito does not explicitly teach the claimed range. However, Fujikawa teaches a range for the spacing between gate electrodes, namely that gate electrodes may be separated by 0.5 µm to 1 µm . By MPEP 2144.05.I, a prima facie case of obviousness exists.
Claims 21-23, 25-29 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Saito as applied to claims 14 and 40-42 above, and further in view of Saikaku et al US 20120025874 A1. Saikaku et al will be referenced to as Saikaku henceforth.
Regarding Claim 21,
Harada/Saito teaches:
“A semiconductor device, (Harada: FIG. 6) comprising:
a substrate (Harada: SiC substrate 1, p-type epitaxial layer 2, [0052]);
a source region (Harada: n-type source region 5, [0053]) and a drain region (Harada: n-type drain region layer 9, [0043]) in the substrate and spaced apart from each other along a first direction (Harada/Saito: Saito:[0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701. Harada: Fig. 6: The source and drain regions are formed in 3A and therefore, in combination with Saito, are formed in the substrate as well. The first direction is horizontal.), wherein the source and drain regions have a first conductive type (Harada: the source and drain regions are n-type.); and
a plurality of first gate semiconductive regions in the substrate and between the source region and the drain region (Harada: [0073], annotated FIG. 6 #1: the plurality of first gates are a portion of the gate layer 7A. The plurality of first gates are between 5 and 9. 7A is p-doped.), wherein the first gate semiconductive regions have a second conductive type opposite to the first conductive type (Harada: [0073]: 7A is a p-type region.), and the first gate semiconductive regions are separated from each other along a second direction different from the first direction (Harada: FIG. 6: The first gate regions are separated along an into the page direction. An into the page direction is a second direction.),”
Harada/Saito doesn’t substantially teach:
“wherein a length of a first group of the first gate semiconductive regions along the first direction is greater than a length of a second group of the first gate semiconductive regions along the first direction.”
However, Saikaku teaches:
“wherein a length of a first group of the first gate semiconductive regions along the first direction is greater than a length of a second group of the first gate semiconductive regions along the first direction (Saikaku: [0142], [0145], annotated FIG. 15A #1: The second group of the first gate semiconductive regions may have multiple regions, imaginary boundaries, or areas.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Harada/Saito is modifiable in view of Saikaku by using the geometry of the excess carrier injection suppression gate of Saikaku.
This is because Saikaku teaches that 56c (which belongs to the sixth embodiment) is an excess carrier injection suppression gate (Saikaku: [0145]). Saikaku further teaches that the sixth embodiment has the same effect as the fifth embodiment which has the same effect as the first embodiment (Saikaku: [0141], [0146]). Saikaku teaches that the effect of the excess carrier injection suppression gate is to reduce recovery loss and to reduce the probability of self-turn on from noise. One of ordinary skill in the art would recognize these effects to be beneficial because they allow for a more efficient and error-resistant device.
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Regarding Claim 22,
Harada/Saito teaches:
“The semiconductor device of claim 21, wherein the first gate semiconductive regions extend to a deeper position in the substrate than the source and drain regions do (Harada: FIG. 6: 7A extends deeper toward the substrate than 5 or 9.).”
Regarding Claim 23,
Harada/Saito teaches:
“The semiconductor device of claim 21, wherein the first gate semiconductive regions extend along the first direction (Harada: FIG. 6: The first gate regions extend horizontally.).”
Regarding Claim 25,
Harada/Saito teaches:
“The semiconductor device of claim 23, further comprising:
a well region in the substrate (Saito: [0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701.), wherein the first gate semiconductive regions adjoin a top surface of the substrate (Harada: [0073-0076], annotated FIG. 6 #1: 7L reaches 2 which is below 3A.), the well region has a plurality of portions adjoining the top surface of the substrate (Harada: annotated FIG. 6 #1: 3A is in contact with 2.), and adjacent [[to]]two of the first gate semiconductive regions are spaced apart from each other by one of the portions of the well region (Harada: annotated FIG. 6#1: The first gate regions are each separated by a portion of 3A.).”
Regarding Claim 26,
Harada/Saito teaches:
“The semiconductor device of claim 21, further comprising:
a second gate semiconductive region in the substrate and between the source region and the drain region (Harada: annotated FIG. 6 #2), wherein the second gate semiconductive region is connected to at least two of the first gate semiconductive regions (Harada: annotated FIG. 6 #2: the second gate region is connected to each of the first gate regions.).”
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Regarding Claim 27,
Harada/Saito teaches:
“The semiconductor device of claim 26, wherein the second gate semiconductive region extends to a shallower position in the substrate than the first gate semiconductive regions do (Harada: annotated FIG. 6 #2: the second gate region extends to a shallower level toward the substrate than the first gate regions do.).”
Regarding Claim 28,
Harada/Saito teaches:
“The semiconductor device of claim 26, wherein the second gate semiconductive region extends to a shallower position in the substrate than the source and drain regions do (Harada: [0074], annotated FIG. 6 #2: The second gate region extends to reach 3A. The topmost portion of 3A is higher than the bottommost portions of 5 and 9.).”
Regarding Claim 29,
Harada/Saito teaches:
“The semiconductor device of claim 21, wherein a distance between two of the first gate semiconductive regions measured along the second direction is less than a length of the source region measured along the second direction (Harada: annotated FIG. 6 #1: the length of 7H along the into the page direction is evidently less than the length of either 5 or 9 in the into the page direction.). ”
Claims 30-31, 36-37 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Saito as applied to claims 14 and 40-42 above and further in view of a different interpretation of Saikaku. The Examiner refers to the different interpretation of Saikaku as Saikaku #2.
Regarding Claim 30,
Harada/Saito teaches:
“A semiconductor device (Harada: FIG. 6), comprising:
a substrate (Harada: SiC substrate 1, p-type epitaxial layer 2, [0052]);
a source region (Harada: n-type source region 5, [0053]) and a drain region (Harada: n-type drain region layer 9, [0043]) in the substrate and spaced apart from each other along a first direction (Harada/Saito: Saito:[0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701. Harada: Fig. 6: The source and drain regions are formed in 3A and therefore, in combination with Saito, are formed in the substrate as well. The first direction is horizontal.), wherein the source and drain regions have a first conductive type (Harada: the source and drain regions are n-type.); and
a first gate semiconductive region (Harada: annotated FIG. 6 #3), a second gate semiconductive region (annotated FIG. 6 #3), and a third gate semiconductive region (Harada: annotated FIG. 6 #3) in the substrate and between the source region and the drain region (Harada: annotated FIG. 6 #3), wherein the first to third gate semiconductive regions extend along the first direction (Harada: annotated FIG. 6 #3: Each gate region extends in the horizontal direction.), the second gate semiconductive region is between semiconductive regions (Harada: annotated FIG. 6 #3), and the first to third gate semiconductive regions have a second conductive type opposite to the first conductive type (Harada: annotated FIG. 6 #3: The gate regions are p-type.),”
Harada/Saito doesn’t substantially teach:
“wherein the second gate semiconductive region is closer to the drain region than the first gate semiconductive region is.”
However, Saikaku #2 teaches:
“wherein the second gate semiconductive region is closer to the drain region than the first gate semiconductive region is (Saikaku #2: annotated FIG. 15A #2, FIG. 15 C).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Harada/Saito is modifiable in view of Saikaku #2 by Saikaku by using the geometry of the excess carrier injection suppression gate of Saikaku.
This is because Saikaku teaches that 56c (which belongs to the sixth embodiment) is an excess carrier injection suppression gate (Saikaku: [0145]). Saikaku further teaches that the sixth embodiment has the same effect as the fifth embodiment which has the same effect as the first embodiment (Saikaku: [0141], [0146]). Saikaku teaches that the effect of the excess carrier injection suppression gate is to reduce recovery loss and to reduce the probability of self-turn on from noise. One of ordinary skill in the art would recognize these effects to be beneficial because they allow for a more efficient and error-resistant device.
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Regarding Claim 31,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, wherein the first to third gate semiconductive regions are aligned with the source region along the first direction (Harada: annotated FIG. 6 #3: The first to third gate regions lie on horizontal lines with the source region.).”
Regarding Claim 34,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, wherein the first gate semiconductive region is closer to the source region than the second gate semiconductive region is (Saikaku #2: annotated FIG. 15A #2, FIG. 15C). ”
Regarding Claim 36,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, further comprising:
a top gate semiconductive region in the substrate and connecting the first to third gate semiconductive regions to each other (Harada: annotated FIG. 6 #3). ”
Regarding Claim 37,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, further comprising:
a well region in the substrate (Saito: [0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701.) and spacing the first to third gate semiconductive regions apart from each other (Harada: annotated FIG. 6 #3).”
Regarding Claim 39,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, wherein the first to third gate semiconductive regions extend to a deeper position in the substrate than the source and drain regions do (Harada: FIG. 6: 7A extends deeper toward the substrate than 5 or 9.). ”
Claims 30 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Harada/Saito as applied to claims 14 and 40-42 above and further in view of a different interpretation of Saikaku. The Examiner refers to the different interpretation of Saikaku as Saikaku #3.
Regarding Claim 30,
Harada/Saito teaches:
“A semiconductor device (Harada: FIG. 6), comprising:
a substrate (Harada: SiC substrate 1, p-type epitaxial layer 2, [0052]);
a source region (Harada: n-type source region 5, [0053]) and a drain region (Harada: n-type drain region layer 9, [0043]) in the substrate and spaced apart from each other along a first direction (Harada/Saito: Saito:[0094-0095], FIG. 12: The n-type drift region 702 is formed in a top surface of the p-type substrate 701. Harada: Fig. 6: The source and drain regions are formed in 3A and therefore, in combination with Saito, are formed in the substrate as well. The first direction is horizontal.), wherein the source and drain regions have a first conductive type (Harada: the source and drain regions are n-type.); and
a first gate semiconductive region (Harada: annotated FIG. 6 #3), a second gate semiconductive region (annotated FIG. 6 #3), and a third gate semiconductive region (Harada: annotated FIG. 6 #3) in the substrate and between the source region and the drain region (Harada: annotated FIG. 6 #3), wherein the first to third gate semiconductive regions extend along the first direction (Harada: annotated FIG. 6 #3: Each gate region extends in the horizontal direction.), the second gate semiconductive region is between and immediately adjacent to the first and third gate semiconductive regions (Harada: annotated FIG. 6 #3), and the first to third gate semiconductive regions have a second conductive type opposite to the first conductive type (Harada: annotated FIG. 6 #3: The gate regions are p-type.),”
Harada/Saito doesn’t substantially teach:
“wherein the second gate semiconductive region is closer to the drain region than the first gate semiconductive region is.”
However, Saikaku #3 teaches:
“wherein the second gate semiconductive region is closer to the drain region than the first gate semiconductive region is (Saikaku #3: annotated FIG. 15A #3, FIG. 15 C).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Harada/Saito is modifiable in view of Saikaku #2 by Saikaku by using the geometry of the excess carrier injection suppression gate of Saikaku.
This is because Saikaku teaches that 56c (which belongs to the sixth embodiment) is an excess carrier injection suppression gate (Saikaku: [0145]). Saikaku further teaches that the sixth embodiment has the same effect as the fifth embodiment which has the same effect as the first embodiment (Saikaku: [0141], [0146]). Saikaku teaches that the effect of the excess carrier injection suppression gate is to reduce recovery loss and to reduce the probability of self-turn on from noise. One of ordinary skill in the art would recognize these effects to be beneficial because they allow for a more efficient and error-resistant device.
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Regarding Claim 38,
Harada/Saito/Saikaku #2 teaches:
“The semiconductor device of claim 30, wherein a side of the first gate semiconductive region facing the source region and a side of the second gate semiconductive region facing the source region are substantially aligned with each other in a top view (Saikaku #3: annotated FIG. 15A #3, FIG. 15C).”
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 103 rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Endo, Saikaku, Saikaku #2, and Saikaku #3.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitations:
“wherein a length of two or more of the first gate semiconductive electrodes along the first direction is greater than a length of two or more of the first gate semiconductive electrodes along the first direction”
Along with,
“wherein the first gate semiconductive electrodes are rectangular in shape in a plan view of the semiconductor device”
This last limitation is to avoid any possible rejection using FIG. 50C of Endo. If the Applicant chooses to incorporate the above limitations, the Applicant should replace the term, “region” with the term, “electrode” where appropriate.
It would overcome the current rejections for claim 14, 21, and 30. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812