DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-13, 15 and 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (US 2021/0043763).
[claim 10] A semiconductor structure (fig. 8, 10), comprising: an isolation structure (122, 120a, fig. 10) formed over a substrate (103, fig. 10); a first fin structure (rightmost 106a, fig. 10) formed adjacent to the isolation structure; a dielectric wall (47a, 119a, fig. 10, [0046][0079]) extending above the isolation structure, wherein a bottom surface of the dielectric wall is lower than a top surface of the isolation structure (fig. 10); a plurality of first horizontal channels (10a/b/c of rightmost fin, fig. 8,10) formed over the first fin structure; a vertical channel layer comprising: a vertical channel (27, fig. 10, [0033]) formed adjacent to the dielectric wall, wherein the vertical channel is in direct contact with the dielectric wall (fig. 10), and the vertical channel extends from a position which is below a top surface of the first fin structure (fig. 10); and a layer portion (bottom portion of 118a, fig. 10) underlying the isolation structure; and a gate structure (49/49a, fig. 10, [0046]) surrounding the first horizontal channels and the vertical channel (fig. 10).
[claim 11] The semiconductor structure as claimed in claim 10, further comprising: a second fin structure (second rightmost 106a, fig. 10) formed adjacent to the isolation structure; and a plurality of second horizontal channels (10a/b/c of second rightmost fin, fig. 8,10) formed over the second fin structure, wherein the dielectric wall is between the first horizontal channels and the second horizontal channels (fig. 10).
[claim 12] The semiconductor structure as claimed in claim 10, further comprising: a sacrificial layer (top portion of 118a, fig. 10 could be a sacrificial layer) formed between and in direct contact with the first fin structure and the vertical channel.
[claim 13] The semiconductor structure as claimed in claim 10, wherein a portion of the gate structure is lower than a top surface of the first fin structure (fig. 10).
[claim 15] The semiconductor structure as claimed in claim 10, wherein each of the first horizontal channels has a first thickness, the vertical channel has a second thickness, and the first thickness is greater than or equal to the second thickness (fig. 10).
[claim 21] A semiconductor structure (fig. 8, 10), comprising: a substrate (103, fig. 10) a first source/drain (S/D) structure (140a, fig. 10, [0083]) on the substrate ; a second S/D structure (the other of (140a, fig. 10, [0083]) on the substrate; a dielectric wall (47a_2, fig. 10, [0046][0079]) between the first S/D structure and the second S/D structure (47a_2, is between 140a in fig. 10 right diagram); a vertical layer (27, fig. 10, [0033]) having an upper surface contiguous with a bottommost surface portion of the dielectric wall nearest the substrate (upper surface of 27 is the exterior surface of 27 that extends from top to bottom which contacts/is contiguous with the bottom surface portion of 47a which extends from the bottom of 47a to the top of 10a, fig., 10), wherein the vertical layer (27, fig. 10) in contact with the first S/D structure and the second S/D structure (fig. 10); and a gate electrode layer (49/49a, fig. 10) overlying the vertical layer and the dielectric wall.
[claim 22] The semiconductor structure as claimed in claim 21, further comprising: an interfacial layer (either 47a_1 or 118a, fig. 10) disposed between the vertical layer and the gate electrode layer (47a_1 is directly between 27 and gate electrode 49 while a portion of rightmost 118a is between a bottom recessed surface of the vertical layer 27 and a rightmost portion of the gate electrode 49, fig. 10) .
[claim 23] The semiconductor structure as claimed in claim 22, further comprising: a gate dielectric layer (47a_1, fig. 10) disposed between the interfacial layer and the gate electrode layer.
[claim 24] The semiconductor structure as claimed in claim 23, wherein the vertical layer is in contact with the interfacial layer and the gate dielectric layer (fig. 10).
[claim 25] The semiconductor structure as claimed in claim 21, further comprising: a horizontal channel (10a/b/c of rightmost fin, fig. 8,10) contacting the first S/D structure, wherein the vertical layer is disposed between the dielectric wall and the horizontal channel (fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2021/0043763) in view of Collinge (US 2014/0332859).
[claim 1] Jung discloses a semiconductor structure (fig. 8, 9, fig. 10 may also be used as an alternative to fig. 9), comprising: a plurality of first horizontal structures (10a/b/c of rightmost fin, fig. 8,9 optionally 10a/b/c of the leftmost fin may also be part of the first horizontal channels) formed over a substrate (103, fig. 9); a plurality of second horizontal structures (10a/b/c of second of rightmost fin, fig. 8,9) adjacent to the first horizontal structures; a dielectric wall (47a, 118a, 119a, fig. 9, [0046][0079]) formed between the first horizontal structures and the second horizontal nanostructures; a vertical structure (27, fig. 9, [0033] adjacent rightmost fin) between the dielectric wall and the first horizontal structures, wherein the vertical structure is in direct contact with the dielectric wall (fig. 9) and portion of the dielectric wall (portion of dielectric wall includes the whole of 118a,119a, and the portion 47a extending up until 12a1) nearest the substrate overlies the vertical structure; and a gate structure (49, fig. 9, [0046]) surrounding the first horizontal structures, the second horizontal structures and the vertical structure (fig. 9). Jung, however, does not expressly disclose that the structures are nanostructures.
Collinge discloses a semiconductor structure (fig. 1) wherein the semiconductor structures (16, fig. 1, [0019]) surrounded by the gate structure (18, fig. 1, [0020]) are nanostructures [0019].
It would have been obvious to one or ordinary skill in the art before the time of filing to have made the semiconductor structures out of nanostructures in order to further miniaturize the device thereby aiding device integration.
With this modification Jung discloses:
[claim 2] The semiconductor structure as claimed in claim 1, wherein the vertical nanostructure is connected to the first horizontal nanostructures (portion of 27 is directly connected to the side of the horizontal nanostructures 10 a/b/c in fig. 9).
[claim 3] The semiconductor structure as claimed in claim 1, wherein the vertical nanostructure is separated from the first horizontal nanostructures (top portion of 27 is separated from the first horizontal nanostructures 10 a/b/c in fig. 9).
[claim 4] The semiconductor structure as claimed in claim 3, wherein the vertical nanostructure is separated from the first horizontal nanostructures by a portion of the gate structure (e.g. horizontal nanostructures 10a/b/c of leftmost fin would be separated from the vertical nanostructure 27 of the rightmost fin by gate electrode 49) .
[claim 5] The semiconductor structure as claimed in claim 1, further comprising: an isolation structure (122, fig. 9, 10 [0077]) formed over the substrate, wherein a portion of the dielectric wall is lower than a top surface of the isolation structure (fig. 9).
[claim 6] The semiconductor structure as claimed in claim 5, wherein a portion of the gate structure is lower than the top surface of the isolation structure (note that in alternative fig. 10 the gate 49 is below the isolation structure 122).
[claim 7] The semiconductor structure as claimed in claim 1, further comprising: a first source/drain (S/D) structure (140a, fig. 9, [0083]) connected to the first horizontal nanostructures; and a spacer layer (12c1, fig. 9) adjacent to the first S/D structure, wherein a top surface of the spacer layer is lower than a top surface of the dielectric wall (fig. 9).
[claim 9] The semiconductor structure as claimed in claim 1, wherein the first horizontal nanostructures and the vertical nanostructure are made of different materials (10a/b/c may be made of SiGe [0029] while 27 may be made of silicon [0064]).
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (US 2021/0043763) or Jung (US 2021/0043763) in view of Collinge (US 2014/0332859).
Jung or Jung/Collinge discloses the semiconductor device of claims 1 and 10 but do not expressly disclose that the first horizontal channel nanostructures and the vertical channel nanostructure form an E-shaped structure.
Nevertheless it would have been obvious to have made the first horizontal channel nanostructures and the vertical channel nanostructure form an E-shaped structure, since it has been held that a particular shape configuration (E) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any interpretation applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898