DETAILED ACTION
This application, 18170522, attorney docket 2211647PCT-US-CXMT-CT, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Intel Inc, and is a continuation of PCT/CN2022/092008, filed 05/10/2022 and claims foreign priority to 202111033067.1, filed 09/03/2021. Claims 1 and 8-13 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claim 1 and correctly argues in his response filed 11/21/25, that the amendments overcome the §112 a and b rejections presented in the office action issued 8/25/2025 which are withdrawn.
Applicant further argues that the art of record Sugiura, U.S. 5674763 does teach or make obvious arrays of transistors that include a plurality of rows and a plurality of columns of transistors in a single well Examiner agrees and withdraws the §102 rejection. However, arrays of transistors is a duplication of parts that is not novel, which will be discussed below. Applicant further argues that Sugiura does not teach transistors in a common well that have two different threshold voltages adjusted by gate channel doping, gate dielectric thickness or gate metal work function values. Examiner disagrees. Sugiura teaches at paragraph co2, ln25 ‘ … there is provided a semiconductor device according to the invention, which comprises a semiconductor device comprising: a semiconductor substrate; a well region formed in the semiconductor substrate, the well region including a first portion having a first surface impurity concentration and a second portion having a second surface impurity concentration higher than the first surface impurity concentration; insulated-gate field-effect transistors formed in the well region, each of the insulated-gate field-effect transistors having a channel region and the channel region of at least one of the insulated-gate field-effect transistors formed in the first portion of the well region having the first surface impurity concentration.” And “the first portion of the well region which is the channel region of at least one of the insulated-gate field-effect transistors has an impurity concentration in its near-surface region which is lower than the impurity concentration of the near-surface region of another portion of the well region. The threshold voltage of the insulated-gate field-effect transistor can therefore be adjusted. Co3 ln 27. Claim 17 recites, “ A method of forming first and second transistors having different threshold voltages in a well region formed in a body of semiconductor material.
Finally, applicant argues that Sugiura does not teach transistor output currents that are different values. However, as discussed in the previous office action, output current is a result dependent variable that a designer uses to allow high and low power devices in the same device, and all transistors are capable of switching a range of current, so the limitation is not novel.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 and 8-13 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor regards as the invention.
Claims 1 and 13 recite the limitation " a drain of the transistor " There is insufficient antecedent basis for this limitation in the claim. IT is not clear which of the plurality of transistors is being limited.
Claims 1 and 13 recite, “wherein the second device area is connected to the first device area in a length direction of the well area of first conductive type” The length direction is not defined and it is not clear whether the areas are connected across the length direction or along the length direction.
Claims 1 and 13 recite, wherein the length direction of the well area of first conductive type is a row direction” this is indefinite because it is not clear the distinction between a row and a column.
Claim s 1 and 13 recite, “a difference between a work function of a gate of each of the plurality of transistors in the second device unit and a work function of the second active area is less than a difference between 3 work function of a gate of each of the plurality of transistors in the first device unit and a work function of the first active area,”
which requires that the active area and gates have a metal structure, but no metals are claimed, so the claim is indefinite.
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiura (U.S.5,674,763) in view of Baldwin et al. (U.S. 2012/0091531).
As for claims 1 and 13,
Sugiura teaches in figure 1 and 2, a semiconductor structure and the method for making the structure, comprising a well area (2), of first conductive type (p-type, [co6, ln60]), wherein the well area of first conductive type comprises:
a first device area (region surrounding 20-1), wherein a first active area (20-1) is formed in the first device area, a first device unit (2a) being formed in the first active area,
and a second device area (region surrounding 20-2), wherein the second device area is connected to the first device area in a length direction of the well area of first conductive type (connected at isolation region 13 in figure 2 ,which extends across a portion of the width, so is connected along the length of the well), a second active area (20-1) being formed in the second device area, a second device unit being formed in the second active area (transistor 2b),
wherein a width of well area of the first device area is the same as a width of well area of the second device area (well area is shown as a rectangle with constant width).
wherein a threshold voltage of each of the plurality of transistors in the second device unit is less than a threshold voltage of each of the plurality of transistors in the first device unit; wherein a doping concentration of the conductive channel of each of the plurality of transistors in the second device area is less than a channel doping concentration of the conductive channel of each of the plurality of transistors in the first device area, or a thickness of a gate dielectric layer of each of the plurality of transistors in the second device unit is less than a thickness of a gate dielectric layer of each of the plurality of transistors in the first device unit, or a difference between a work function of a gate of each of the plurality of transistors in the second device unit and a work function of the second active area is less than a difference between 3 work function of a gate of each of the plurality of transistors in the first device unit and a work function of the first active area. (Sugiura teaches adjusting threshold voltage for selected devices by altering the channel doping concentration [claim 17, co3 ln27])
Sugiura does not teach a drain of the transistor in the first device unit provides a first driving current. Transistors inherently switch to provide current in a circuit and “configured to provide a first or second of driving current” is an intended use of the device and does not provide any limitation to the structure. it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). Here the transistors will output any current input, and the current is a result dependent variable that one skilled in circuit design will select for the needs of the device, for example, higher power devices require a higher current, but low power devices may be destroyed by excessive current.
Sugiura does not teach that the first and second device units includes a plurality of transistors in an array.
However, Baldwin teaches arrays of transistors (26g) in doped regions (22).
It would have been obvious to one skilled in the art at the effective filing date of this application to form multiple transistors in the regions because it allows more complex integrated circuits. In re Harza establishes "a mere duplication of parts has no patentable significance unless a new and unexpected result is produced." 274 F.2d 669, 124 USPQ 378 (CCPA 1960); See, MPEP 2144.04 (VI)(C). One skilled in the art would have combined these elements with a reasonable expectation of success.
Sugiura does not teach a shallow trench isolation structure formed in the well area of the first conductive type, separates the first device area in the first active area and the second active area. Instead, it uses LOCOS 913 figure 3e
However, Baldwin teaches STI around each active area [0033], as an alternative to the locos taught by Sugiura.
It would have been obvious to one skilled in the art at the effective filing date of this application to use STI instead of LOCOS to reduce bird’s beak defect One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 8,
Sugiura in view of Baldwin makes obvious the semiconductor structure of claim 1, and makes obvious the use as a sense amplifier and a switch control circuit, wherein the sense amplifier comprises the first device unit; the switch control circuit is connected to the sense amplifier through a data signal line; and the switch control circuit comprises the second device unit.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). Here the devices must be connected in a circuit for a useful device and the connection is directed to the function of the device, which is an obvious use of the device.
As for claim 9,
Sugiura in view of Baldwin makes obvious the semiconductor structure of claim 8, and makes obvious the first device unit comprises a first transistor unit and a second transistor unit; the sense amplifier further comprises a third device unit, and the third device unit comprises a third transistor unit and a fourth transistor unit; the third transistor unit and the first transistor unit form a phase inverter, the fourth transistor unit and the second transistor unit form a phase inverter, gates of the fourth transistor unit and the second transistor unit are connected to drains of the third transistor unit and the first transistor unit, and drains of the fourth transistor unit and the second transistor unit are connected to gates of the third transistor unit and the first transistor unit.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). Here the devices must be connected in a circuit for a useful device and the connection is directed to the function of the device, which is an obvious use of the device.
As for claim 10,
Sugiura in view of Baldwin makes obvious the semiconductor structure of claim 8, wherein the second device unit comprises a fifth transistor unit, a sixth transistor unit, and a seventh transistor unit;
the data signal line comprises a first data line and a second data line;
a drain of the fifth transistor unit is connected to the first data line, a drain of the sixth transistor unit is connected to the second data line, a source of the seventh transistor unit is connected to the first data line, and a drain of the seventh transistor unit P3 is connected to the second data line.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). Here the devices must be connected in a circuit for a useful device and the connection is directed to the function of the device, which is an obvious use of the device.
As for claim 11,
Sugiura in view of Baldwin makes obvious the semiconductor structure of claim 10, and makes obvious the switch control circuit further comprises a fourth device unit, and the fourth device unit comprises an eighth transistor unit, a ninth transistor unit and a tenth transistor unit;
a drain of the eighth transistor unit is connected to the first data line, a drain of the ninth transistor unit is connected to the second data line, a source of the tenth transistor unit is connected to the first data line, and a drain of the tenth transistor unit is connected to the second data line.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). Here the devices must be connected in a circuit for a useful device and the connection is directed to the function of the device, which is an obvious use of the device.
As for claim 12,
Sugiura in view of Baldwin makes obvious the semiconductor structure of claim 11, wherein the switch control circuit further comprises a P-type switch unit and an N-type switch unit;
the P-type switch unit is configured to turn on the fourth device unit, and the N-type switch unit is configured to turn on the second device unit.
Language in an apparatus or product claim directed to the function, operation, intent-of-use, and materials upon which the components of the structure work that does not structurally limit the components or patentably differentiate the claimed apparatus or product from an otherwise identical prior art structure will not support patentability. See, e.g., In re Rishoi, 197 F.2d 342, 344-45 (CCPA 1952); In re Otto, 312 F.2d 937, 939-40 (CCPA 1963); In re Ludtke, 441 F.2d 660, 663-64 (CCPA 1971); In re Yanush, 477 F.2d 958, 959 (CCPA 1973). Here the devices must be connected in a circuit for a useful device and the connection is directed to the function of the device, which is an obvious use of the device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893