DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 12/26/2025.
Applicant’s amendments filed 12/26/2025 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claim 20.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-10, 12, 14-17, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0175149 to Takaya et al. (hereinafter Takaya) in view of Alexander et al. (US 2016/0241232, hereinafter Alexander) and Pesic (US 2022/0138544).
With respect to claim 1, Takaya discloses a semiconductor device (e.g., IGBT or MOSFET) (Takaya, Fig. 1, ¶0040-¶0067, ¶0088), comprising:
a drift layer (28) (Takaya, Fig. 1, ¶0040, ¶0042, ¶0045, ¶0048, ¶0049) above a substrate (30/29);
a source/drain region (22/26a) (Takaya, Fig. 1, ¶0043, ¶0044) above the drift layer (28), wherein the source/drain region (22/26a) comprises:
a first doping region (26a or 22) (Takaya, Fig. 1, ¶0044) having a first conductive type (e.g., p-type or n-type); and
a second doping region (22 or 26a) (Takaya, Fig. 1, ¶0043) having a second conductive type (e.g., n-type or p-type), wherein the first doping region and the second doping region form a top surface (12a) of the source/drain region (22/26a), the second conductive type (e.g., n-type or p-type) is different from the first conductive type (e.g., p-type or n-type);
a contact (80) (Takaya, Fig. 1, ¶0040); and
a gate structure (38/40) (Takaya, Fig. 1, ¶0041) adjacent to the source/drain region (22/26a).
Further, Takaya does not specifically disclose an oxide thin film on the source/drain region, a contact on the oxide thin film, wherein the oxide thin film directly contacts the top surface of the source/drain region, a conduction band energy level of the oxide thin film is lower than a conduction band energy level of the first doping region, wherein the oxide thin film directly contacts a bottom surface of the contact.
However, Alexander teaches forming a semiconductor device (Alexander, Fig. 13B, ¶0077-¶0082) comprising a contact (e.g., an emitter contact including polysilicon layer 1322 and metallization 1326) on an emitter region including n+ emitter region (1304B) and laterally adjacent portion of the p-type base region (102A) and an oxide thin film (e.g., a tunnel oxide 1324) on the emitter region (e.g., n+ emitter region 1304B and laterally adjacent portion of the p-type base region 102A), wherein the oxide thin film (1324) directly contacts the top surface of the emitter region (1304B), wherein the oxide thin film (e.g., the tunnel oxide 1324) directly contacts a bottom surface of the contact (1322/1326), to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Further, Pesic teaches forming a tunnelling layer (722) (Pesic, Fig. 7C, ¶0066- ¶0068, ¶0072) comprised of a small-bandgap oxide material (e.g., Co3O4, V2O5, or WO3) between the electrode (e.g., 702) and the active region (708) and having a conduction band energy level lower than that of the active region (708), to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya, wherein the tunnel oxide comprised of a small-bandgap oxide material as taught by Pesic to have the semiconductor device, comprising: an oxide thin film on the source/drain region, a contact on the oxide thin film, wherein the oxide thin film directly contacts the top surface of the source/drain region, a conduction band energy level of the oxide thin film is lower than a conduction band energy level of the first doping region, wherein the oxide thin film directly contacts a bottom surface of the contact, in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device; and to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer (Alexander, ¶0080, ¶0082; Pesic, ¶0067-¶0068, ¶0072).
Regarding claim 2, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya does not specifically disclose that a thickness of the oxide thin film is between 1 nm and 5 nm.
However, Alexander teaches forming the oxide thin film (e.g., a tunnel oxide 1324) having a thickness about 1 nm (Alexander, Fig. 13B, ¶0078), to provide a barrier for holes to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer having a specific thickness as taught by Alexander to have the semiconductor device, a thickness of the oxide thin film is between 1 nm and 5 nm, in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device (Alexander, ¶0078, ¶0080, ¶0082).
Regarding claims 3 and 4, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya discloses the semiconductor device, wherein the first conductive type (Takaya, Fig. 1, ¶0044) is p-type (e.g., p-type region 26a), but does not specifically disclose that the conduction band energy level of the oxide thin film is lower than a valance band energy level of the first doping region, and an energy gap between the conduction band energy level of the oxide thin film and the valance band energy level of the first doping region is larger than or equal to 0.1 eV (as claimed in claim 3); wherein the oxide thin film comprises MoO3, WO3, or V2O5 (as claimed in claim 4).
However, Pesic teaches forming a tunnelling layer (722) (Pesic, Fig. 7C, ¶0066- ¶0068, ¶0072) comprised of a small-bandgap oxide material (e.g., Co3O4, V2O5, or WO3) between the electrode (e.g., 702) and the active region (708) and having a conduction band energy level lower than that of the active region (708), wherein the oxide thin film comprises V2O5 or WO3 and wherein the difference between conduction band offsets of the tunneling layer (722) and the active layer (708) is about 0.7 eV, to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer, wherein the tunnel oxide comprised of a small-bandgap oxide material as taught by Pesic to have the semiconductor device, wherein the conduction band energy level of the oxide thin film is lower than a valance band energy level of the first doping region, and an energy gap between the conduction band energy level of the oxide thin film and the valance band energy level of the first doping region is larger than 0.1 eV (as claimed in claim 3); wherein the oxide thin film comprises WO3, or V2O5 (as claimed in claim 4), in order to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer (Pesic, ¶0067-¶0068, ¶0072).
Regarding claim 5, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 3. Further, Takaya does not specifically disclose that the contact comprises a metal material having a work function between 4.6 eV and 7.0 eV.
However, Pesic teaches forming the tunneling oxide (722) (Pesic, Fig. 7C, ¶0077-¶0079) in contact with a top electrode (702) having a work function of about 5.6 eV that is different from a work function of a bottom electrode (704) having a work function of about 4.6 eV to provide work function differential to tune ON/OFF ratio and the leakage of the device.
Thus, Pesic recognizes that a specific metal material of the contact impacts the work function differential and performance of the device. Thus, a specific metal material of the contact is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a specific metal material of the contact as Pesic has identified specific metal material of the contact as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific metal material of the contact comprising a metal material having a work function between 4.6 eV and 7.0 eV, in order to tune ON/OFF ratio and the leakage of the device as taught by Pesic (¶0077-¶0079) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by optimizing a specific metal material of the contact as taught by Pesic to have the semiconductor device, wherein the contact comprises a metal material having a work function between 4.6 eV and 7.0 eV, in order to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer, and to tune ON/OFF ratio and the leakage of the device as taught by (Pesic, ¶0067-¶0068, ¶0077-¶0079).
Regarding claims 6 and 7, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya discloses the semiconductor device, wherein the first conductive type (Takaya, Fig. 1, ¶0043) is n-type (e.g., n-type 22), but does not specifically disclose that an energy gap between the conduction band energy level of the oxide thin film and the conduction band energy level of the first doping region is smaller than or equal to 0.1 eV (as claimed in claim 6); wherein the oxide thin film comprises TiO2 (as claimed in claim 7).
However, Pesic teaches forming a tunnelling layer (722) (Pesic, Fig. 7C, ¶0066- ¶0068, ¶0073-¶0074) comprised of titanium oxide between the electrode (e.g., 702) and the active region (708), and the titanium oxide has a specific dielectric constant. Further, Pesic teaches that a conduction band energy level of the tunneling oxide (722) is lower than that of the active region (708), wherein the difference between conduction band offsets of the tunneling layer (722) and the active layer (708) is about 0.7 eV, to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer.
Thus, Pesic recognizes that a specific small-bandgap oxide material of the tunneling layer impacts the difference between conduction bands and operation of the device. Thus, a specific oxide material of the tunneling layer is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a specific oxide material of the tunneling layer as Pesic has identified a specific oxide material of the tunneling layer as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at a specific oxide material of the tunneling layer comprising TiO2, in order to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer as taught by Pesic (¶0067-¶0068, ¶0073) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer, wherein a material of the tunnel oxide comprised of a small-bandgap oxide material is optimized as taught by Pesic to have the semiconductor device, wherein an energy gap between the conduction band energy level of the oxide thin film and the conduction band energy level of the first doping region is smaller than or equal to 0.1 eV (as claimed in claim 6); wherein the oxide thin film comprises TiO2 (as claimed in claim 7), in order to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer (Pesic, ¶0067-¶0068, ¶0073).
Regarding claims 9 and 10, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya does not specifically disclose that the oxide thin film covers the first doping region and the second doping region, and the contact covers the oxide thin film (as claimed in claim 9); wherein the oxide thin film covers the first doping region, the contact covers the oxide thin film and the second doping region (as claimed in claim 10).
However, Alexander teaches forming the oxide thin film (e.g., a tunnel oxide 1324) covering the emitter region (e.g., n+ emitter region 1304B) and laterally adjacent portion of the p-type base region (102A), and contact (1322/1326) covers (1322/1326) the oxide thin film (1324) and the p-type base region (102A), to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya to have the semiconductor device, wherein the oxide thin film covers the first doping region and the second doping region, and the contact covers the oxide thin film (as claimed in claim 9); wherein the oxide thin film covers the first doping region, the contact covers the oxide thin film and the second doping region (as claimed in claim 10), in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Regarding claim 12, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya discloses the semiconductor device, wherein the source/drain region (22/26a) (Takaya, Fig. 1, ¶0043, ¶0044) further comprises: a third doping region (e.g., n-type source region 22 on the left/right side of the p-type region 26a) having the second conductive type (e.g., n-type), wherein the first doping region (e.g., p-type region 26a) is sandwiched between the second doping region (e.g., n-type source region 22 on the right/left side of the p-type region 26a) and the third doping region (e.g., n-type source region 22 on the left/right side of the p-type region 26a), and the first doping region, the second doping region, and the third doping region form the top surface (12a) of the source/drain region (22/26a).
Regarding claim 14, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya discloses the semiconductor device, wherein the gate structure (38/40) (Takaya, Fig. 1, ¶0041) comprises: a gate electrode layer (40), extending from the source/drain region (22/26a) into the drift layer (28); and a gate dielectric layer (38/36) surrounding the gate electrode layer (38/40), wherein the gate dielectric layer (38) isolates the gate electrode layer (40) from the source/drain region (22/26a) and isolates the gate electrode layer (40) from the drift layer (28).
Regarding claim 15, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 14. Further, Takaya discloses the semiconductor device, wherein the gate dielectric layer (e.g., 36) (Takaya, Fig. 1, ¶0041) extends onto the source/drain region (22/26a), and wherein the gate dielectric layer (36) directly contacts the top surface of the source/drain region (22/26a).
Regarding claims 16 and 17, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 14. Further, Takaya does not specifically disclose that the oxide thin film and the gate dielectric layer are laterally spaced by a distance (as claimed in claim 16); wherein the oxide thin film directly contacts the gate dielectric layer (as claimed in claim 17).
However, Alexander teaches forming the oxide thin film (e.g., a tunnel oxide 1324) covering the emitter region (e.g., n+ emitter region 1304B) and laterally adjacent portion of the p-type base region (102A), wherein the oxide thin film (1324) and the oxide layer (1328) filled in the trench (1330) are laterally spaced by a distance, wherein the oxide thin film (1324) contacts the oxide layer (1328) formed on the top surface of the emitter region (1304B,) to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya, wherein the thin oxide layer is distant from the gate dielectric layer extending in the gate trench and in direct contact with a gate dielectric layer formed on the top surface of the source/drain region to have the semiconductor device, wherein the oxide thin film and the gate dielectric layer are laterally spaced by a distance (as claimed in claim 16); wherein the oxide thin film directly contacts the gate dielectric layer (as claimed in claim 17), in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
With respect to claim 18, Takaya discloses a method of forming a semiconductor device (e.g., IGBT or MOSFET) (Takaya, Figs. 1-10, ¶0040-¶0067, ¶0088), comprising:
forming a drift layer (28) (Takaya, Figs. 1-10, ¶0040, ¶0042, ¶0045, ¶0048, ¶0049, ¶0052, ¶0065) above a substrate (30/29);
doping a top surface (12a) of the drift layer (28) (Takaya, Figs. 1, 9-10, ¶0064) with a first conductive type dopant (e.g., p-type or n-type) to form a first doping region (26a or 22) (Takaya, Fig. 1, ¶0044) of a source/drain region (22/26a);
doping the top surface (12a) of the drift layer (28) (Takaya, Figs. 1, 9-10, ¶0064) with a second conductive type dopant (e.g., n-type or p-type) to form a second doping region (22 or 26a) (Takaya, Fig. 1, ¶0064) of the source/drain region (22/26a), wherein the second conductive type dopant (e.g., n-type or p-type) is different from the first conductive type dopant (e.g., p-type or n-type);
forming a contact (80) (Takaya, Figs. 1, 10, ¶0065).
Further, Takaya does not specifically disclose forming an oxide thin film on the source/drain region, wherein the oxide thin film directly contacts a top surface of the source/drain region, a conduction band energy level of the oxide thin film is lower than a conduction band energy level of the first doping region, forming a contact on the oxide thin film, wherein a bottom surface of the contact directly contacts the oxide thin film.
However, Alexander teaches forming a semiconductor device (Alexander, Fig. 13B, ¶0077-¶0082) comprising a contact (e.g., an emitter contact including polysilicon layer 1322 and metallization 1326) on an emitter region including n+ emitter region (1304B) and laterally adjacent portion of the p-type base region (102A) and an oxide thin film (e.g., a tunnel oxide 1324) on the emitter region (e.g., n+ emitter region 1304B and laterally adjacent portion of the p-type base region 102A), wherein the oxide thin film (1324) directly contacts the top surface of the emitter region (1304B), wherein the oxide thin film (e.g., the tunnel oxide 1324) directly contacts a bottom surface of the contact (1322/1326), to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Further, Pesic teaches forming a tunnelling layer (722) (Pesic, Fig. 7C, ¶0066- ¶0068, ¶0072) comprised of a small-bandgap oxide material (e.g., Co3O4, V2O5, or WO3) between the electrode (e.g., 702) and the active region (708) and having a conduction band energy level lower than that of the active region (708), to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of forming the semiconductor device of Takaya by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya, wherein the tunnel oxide comprised of a small-bandgap oxide material as taught by Pesic to have the method of forming the semiconductor device, comprising: forming an oxide thin film on the source/drain region, wherein the oxide thin film directly contacts a top surface of the source/drain region, a conduction band energy level of the oxide thin film is lower than a conduction band energy level of the first doping region, forming a contact on the oxide thin film, wherein a bottom surface of the contact directly contacts the oxide thin film, in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device; and to provide a barrier for holes and to reduce operation voltage of the device due to the difference between the energy bands of the tunneling layer and the active layer (Alexander, ¶0080, ¶0082; Pesic, ¶0067-¶0068, ¶0072).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0175149 to Takaya in view of Alexander (US 2016/0241232) and Pesic (US 2022/0138544) as applied to claim 6, and further in view of Wada et al. (US 2012/0056202, hereinafter Wada).
Regarding claim 8, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 6. Further, Takaya does not specifically disclose that the contact comprises a metal material having a work function between 2.0 eV and 4.4 eV.
However, Wada teaches forming the contact (95) on a main surface of the drift layer (3) and comprised of aluminum (Wada, Fig. 1, ¶0001, ¶0072, ¶0145-¶0147) having a work function of 4.1eV that in the range between 2.0 eV and 4.4 eV, to provide a reduced contact resistance, and to obtain a semiconductor device with reduced on-resistance.
Note that a specific example in the prior art which is within a claimed range anticipates the range (M.P.E.P. §2131.03).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a metal contact comprised of a specific material as taught by Wada to have the semiconductor device, wherein the contact comprises a metal material having a work function between 2.0 eV and 4.4 eV, in order to provide a reduced contact resistance, and to obtain a semiconductor device with reduced on-resistance (Wada, ¶0001, ¶0072, ¶0145-¶0147).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0175149 to Takaya in view of Alexander (US 2016/0241232) and Pesic (US 2022/0138544) as applied to claim 1, and further in view of Xiang et al. (US Patent No. 6,369,421, hereinafter Xiang).
Regarding claim 11, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 1. Further, Takaya does not specifically disclose that the oxide thin film comprises a first film portion covering the first doping region and a second film portion covering the second doping region, and a material of the first film portion is different from that of the second film portion.
However, Alexander teaches forming the oxide thin film (e.g., a tunnel oxide 1324) (Alexander, Fig. 13B, ¶0077-¶0082) comprising a first film portion covering the first doping region (e.g., portion of the p-type base region 102A) and a second film portion covering the second doping region (e.g., n+ emitter region 1304B), to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Further, Xiang teaches forming a tunnel oxide film (50) (Xiang, Figs. 2, 3D, Col. 3, lines 19-28; lines 54-67; Col. 4, lines 1-41; Col. 5, lines 56-60; Col. 6, lines 17-23) having a first region (52) and a second region (53), wherein a material of the first region (52) is different from that of the second region (53), and the first region (52) covers the p-type region (e.g., a channel 14 between the n-type regions 34 and 36), and the second region (53) covers the n-type region (e.g., 26), to provide effective tunneling and to reduce current leakage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya, wherein the tunnel oxide layer includes a first region and a second region having different materials as taught by Xiang to have the semiconductor device, wherein the oxide thin film comprises a first film portion covering the first doping region and a second film portion covering the second doping region, and a material of the first film portion is different from that of the second film portion, in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device; and to provide effective tunneling and to reduce current leakage (Alexander, ¶0080, ¶0082; Xiang, Col. 3, lines 19-28; lines 54-67; Col. 4, lines 1-41; Col. 5, lines 56-60; Col. 6, lines 17-23).
Regarding claim 13, Takaya in view of Alexander and Pesic discloses the semiconductor device of claim 12. Further, Takaya does not specifically disclose that the oxide thin film comprises a first film portion covering the first doping region, a second film portion covering the second doping region, and a third film portion covering the third doping region, and a material of the first film portion is different from that of the second film portion and the third film portion.
However, Alexander teaches forming the oxide thin film (e.g., a tunnel oxide 1324) (Alexander, Fig. 13B, ¶0077-¶0082) comprising a first film portion covering the first doping region (e.g., portion of the p-type base region 102A) and a second film portion covering the second doping region (e.g., n+ emitter region 1304B), to reduce hole injection and recombination in the emitter region, to block holes from reaching the emitter contact to improve a performance of the semiconductor device (Alexander, ¶0080, ¶0082).
Further, Xiang teaches forming a tunnel oxide film (50) (Xiang, Figs. 2, 3D, Col. 3, lines 19-28; lines 54-67; Col. 4, lines 1-41; Col. 5, lines 56-60; Col. 6, lines 17-23) having a first region (53) and a second region (52), wherein a material of the first region (53) is different from that of the second region (52), and the first region (53) covers a portion of the n-type region (26), and the second region (53) covers the p-type region (e.g., a channel between n-type regions 24 and 26), and the third region (52) covers the p-type region (e.g., a channel between n-type regions 34 and 36) to provide effective tunneling and to reduce current leakage.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Takaya/Alexander/Pesic by forming a tunnel oxide of Alexander as a thin oxide layer between the source/drain region and the contact of Takaya, wherein the tunnel oxide layer includes a first region having a material different from that of the second region and the third region as taught by Xiang to have the semiconductor device, wherein the oxide thin film comprises a first film portion covering the first doping region, a second film portion covering the second doping region, and a third film portion covering the third doping region, and a material of the first film portion is different from that of the second film portion and the third film portion, in order to reduce hole injection and recombination in the emitter/source region, to block holes from reaching the emitter/source contact to improve a performance of the semiconductor device; and to provide effective tunneling and to reduce current leakage (Alexander, ¶0080, ¶0082; Xiang, Col. 3, lines 19-28; lines 54-67; Col. 4, lines 1-41; Col. 5, lines 56-60; Col. 6, lines 17-23).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0175149 to Takaya in view of Alexander (US 2016/0241232) and Pesic (US 2022/0138544) as applied to claim 18, and further in view of Grover et al. (US Patent No. 6,825,105, hereinafter Grover).
Regarding claim 19, Takaya in view of Alexander and Pesic discloses the method of forming the semiconductor device of claim 18. Further, Takaya does not specifically disclose that the drift layer is doped with the first conductive type dopant to a doping concentration between 5x1018/cm3 and 5x1020/cm3.
However, Grover teaches a method of forming a trench-gate MOSFET device (Grover, Figs. 1, 3-11, Col. 1, lines 4-12; Col. 6-10) comprising doping the drift layer (14) with the first conductive type dopant (e.g., p-type dopant) to a doping concentration between 1x1019/cm3 device (Grover, Figs. 1, 9, Col. 9, lines 24-48) that is in the range between 5x1018/cm3 and 5x1020/cm3, to provide p-type region (35) between the source regions (13) for the device structure having compact geometry in a self-aligned manner.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of forming the semiconductor device of Takaya/Alexander/Pesic by doping the drift layer as taught by Grover to have the method of forming the semiconductor device, wherein the drift layer is doped with the first conductive type dopant to a doping concentration between 5x1018/cm3 and 5x1020/cm3r, in order to provide an improved method of forming a semiconductor device having compact geometry in a self-aligned manner (Grover, Col. 1, lines 4-12; Col. 6, lines 38-50; Col. 9, lines 32-48).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0175149 to Takaya in view of Alexander (US 2016/0241232) and Pesic (US 2022/0138544) as applied to claim 18, and further in view of Mauder et al. (US 2018/0175150, hereinafter Mauder).
Regarding claim 20, Takaya in view of Alexander and Pesic discloses the method of forming the semiconductor device of claim 18. Further, Takaya discloses the method, further comprising: forming an opening (52a) in the drift layer (12/28) (Takaya, Fig. 3, ¶0054) and a protruding portion (e.g., portions of the semiconductor substrate 12 between the trenches 54) along the opening (52) before doping the top surface of the drift layer; doping (Takaya, Figs. 9-10, ¶0064) the protruding portion of the drift layer (12/28) with the first conductive type dopant (e.g., p-type or n-type) and the second conductive type dopant (e.g., n-type or p-type) to form the source/drain region (22/26a); forming a gate structure (38/40) (Takaya, Figs. 9-10, ¶0065) in the opening (52a), wherein the gate structure extends from the source/drain region (22/26a) into the drift layer (28), but does not specifically disclose forming a gate structure in the opening after doping the top surface of the drift layer.
However, Mauder teaches a method of forming the semiconductor device comprising doping the drift layer (131) (Mauder, Figs. 8A-8C, ¶0105-¶0111) to form source regions (110) by implantations along the front surface (101) directly at the mesa sidewalls of the gate trenches (250), wherein a gate structure (155/159) (Mauder, Figs. 8A-8C, ¶0109-¶0111) is formed in the opening (250) after doping the top surface of the drift layer (e.g., after formed the source regions 110), to provide a semiconductor device having high quality and reliability gate oxide and low gate leakage at large blocking voltage (Mauder, ¶0003, ¶0168, ¶0170).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of forming the semiconductor device of Takaya/Alexander/Pesic by forming a gate structure in the gate trench after doping the mesa structure as taught by Mauder to have the method of forming the semiconductor device, comprising: forming a gate structure in the opening after doping the top surface of the drift layer, in order to provide a semiconductor device having high quality and reliability gate oxide and low gate leakage at large blocking voltage (Mauder, ¶0003, ¶0108-¶0111, ¶0168, ¶0170).
Response to Arguments
Applicant's arguments filed 12/26/2025 have been fully considered but they are not persuasive.
In response to Applicant's argument that “Alexander provides an NPN B-TRAN, which is different from the MOSFET in Takaya, so a person skilled in the art would not combine Takaya and Alexander” and “Alexander cannot disclose the claimed feature of "a contact on the oxide thin film, wherein the oxide thin film directly contacts a bottom surface of the contact", the examiner submits that Alexander teaches (e.g., paragraph [0234]) that B-TRAN fabrication techniques can be applied to other switching devices, such as e.g. IGBTs. Further, Takaya teaches (e.g., paragraph [0088]) that a switching device includes MOSFET or an IGBT, and the invention of Takaya can be applied to an IGBT, wherein “the drain region 30 in the above-described MOSFETs is replaced by a collector region of p-type” to obtain an IGBT. Thus, a person of ordinary skill in the art would recognize that for the switching device including an IGBT, the source region would function as an emitter region, and forming a tunnel oxide of Alexander as a thin oxide layer between the emitter/source region and the contact of Takaya would provide a semiconductor device (an IGBT or MOSFET) comprising: an oxide thin film on the emitter/source region, wherein the oxide thin film directly contacts the top surface of the emitter/source region, and a contact on the oxide thin film, wherein the oxide thin film directly contacts a bottom surface of the contact, as required by claim 1. Therefore, the above Applicant's argument is not persuasive, and a person skilled in the art would combine Takaya and Alexander to obtain a semiconductor device with improved performance as stated in the current rejection of claim 1.
In response to applicant's arguments against the references individually (“Pesic utilizes the energy difference between tunneling layers 722, 724 and the active layer 708 to form a tunneling barrier, thereby preventing electrons from tunneling between the top electrode 702 and bottom electrode 704 when insufficient voltage is applied. Alexander's tunnel oxide 1324 is used to enhance electron injection from the emitter to the base. Therefore, the purposes of setting the oxide layer are different in Alexander and Pesic” and “[a] person skilled in the art have no reason or motivation to combine Alexander with Pesic”), the examiner submits that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
In the instant case, the secondary reference by Pesic teaches a small-bandgap oxide material including Co3O4, V2O5, or WO3, but the entire structure of the secondary reference by Pesic does not have to be bodily incorporated into the structure of the primary reference by Takaya or into the structure of the secondary reference by Alexander.
Further, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. In this case, a person of ordinary skill in the art would recognize that forming a tunnel oxide of Alexander as a thin oxide layer between the emitter/source region and the contact of Takaya, wherein the tunnel oxide comprised of a small-bandgap oxide material as taught by Pesic, would be advantageous because the tunnel oxide made of small-bandgap oxide material (e.g., V2O5, or WO3) would be capable of forming a barrier for holes that would reduce hole injection and recombination in the emitter/source region to improve a performance of the semiconductor device; and to reduce operation voltage of the semiconductor device. Thus, one of ordinary skill in the art would be motivated to combine the teachings of Takaya, Alexander and Pesic to produce the claimed invention.
Thus, the above applicant's arguments are not persuasive, and the rejection of claim 1 under 35 USC 103 over Takaya in view of Alexander and Pesic is maintained.
Regarding the independent claim 18, the examiner respectfully submits that the applicant’s arguments with respect to the independent claim 18 are not persuasive for the above reasons, and thus the rejection of the independent claim 18 is sustained.
Regarding dependent claims 2-17 and 19-20 which depend on the independent claims 1 and 18, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, and thus the rejections of the dependent claims are sustained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891