DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 1/6/2026 have been entered and considered. The amendments to claims 1, 10, and 16 and the newly added claims 27 and 28 are acknowledged.
Response to Arguments
Applicant’s arguments with respect to claim 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16-19 and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Tanida et al. US 20050186771 A1 (hereinafter referred to as Tanida), in view of Breuer et al. US 20140264890 A1 (hereinafter referred to as Breuer).
Regarding claim 16, Tanida teaches
A semiconductor device (“semiconductor device 10” para. 0065 FIG. 1) comprising:
a conductive probe plug (“diffusion prevention plug 4” para. 0068 FIG. 1) formed on a portion of a die pad (“electrode pad 3” para. 0068) through an opening in a top passivation layer (“opening 8a” in “passivation film 8”, para. 0068) of a semiconductor die (“semiconductor substrate 9” with an “active layer 2”, para. 0065), wherein a portion of the top surface of the conductive probe plug is substantially planar (“The end surface of diffusion prevention plug 4 becomes an substantially flat surface” para. 0080) and is located above a top surface of the top passivation layer (top surface of “diffusion prevention plug 4” lies above “passivation layer 8”);
a pillar (“protrusion electrode 7” and “seed layer 5” made of the same metal, para. 0069) formed over the top surface of the conductive probe plug and a portion of the top surface of the top passivation layer surrounding the top surface of the conductive probe plug such that a lower portion of the copper pillar extends below the top surface of the conductive probe plug toward the top surface of the top passivation layer (“protrusion electrode 7” and “seed layer 5” are formed over “diffusion prevention plug 4” and portions of “passivation layer 8”, para. 0071 and 0084-0085), and the lower portion of the copper pillar completely surrounds the top surface of the conductive probe plug (“protrusion electrode 7” and “seed layer 5” are formed around the “diffusion prevention layer 4, para. 0087); and
However, Tanida fails to teach a copper pillar, a solder cap formed on a top surface of the copper pillar.
Nevertheless, Breuer teaches
a copper pillar (“upper portion 104” made of copper, para. 0022 FIG. 2A),
a solder cap formed on a top surface of the copper pillar (“tin-silver bump 128” is formed over “upper portion 104”, para. 0023).
Tanida and Breuer teach conductive pillars formed over plugs in a passivation layer opening. The “upper portion 104” is made of copper, a well-known conductor, while the “base 102” can be a different material such as tin-lead (para. 0023). Tanida also discloses that the conventional protruding electrode can be made of copper (para. 0005 and 0014). Furthermore, “seed layer 5” and “protrusion electrode 7” can be made of a material that is different from that of “diffusion prevention plug 4”, so materials other than the nickel used “diffusion prevention plug 4” are understood to be appropriate. Copper is also used as seed layers when forming pillars, as evidenced in para. 0022 of Yamamoto et al. US 20210175193 A1. Also, Breuer teaches the use of a “tin-silver bump 128”. Tin-silver solder is known to melt at a lower temperature than copper, such that bonding with another device can be done at lower temperatures and pressures. This reduces the risk of potential damage to circuit elements due to elevated temperatures. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that copper is a known material suitable for use as a “seed layer 5” and “protrusion electrode 7”. A “tin-silver bump 128” allows for easier and lower temperature bonding to external devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device in Tanida with the copper pillar and solder cap taught in Breuer. Copper is a well-known material used for conductive pillars and the solder cap enables lower temperature bonding.
Regarding claim 17, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the die pad comprises an aluminum or aluminum alloy material (“electrode pad 3 is made of aluminum (Al)” para. 0081) and the conductive probe plug comprises a nickel or nickel alloy material (“diffusion prevention plug 4 can be made of nickel (Ni)” para. 0081).
Regarding claim 18, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the portion of the top surface of the conductive probe plug extends above the top surface of the top passivation layer by no more than 10 microns.
Regarding claim 19, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein a perimeter of the copper pillar is located within a perimeter of the die pad (“protrusion electrode 7” is made in the “opening 6a” of “resist film 6” and is shown as being narrower than “electrode pad 3” since portions of “resist film 6” overlap the “electrode pad 3”, para. 0083).
Regarding claim 21, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the conductive probe plug comprises nickel (“diffusion prevention plug 4 can be made of nickel (Ni)” para. 0081).
Regarding claim 22, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the top surface of the conductive probe plug extending above the top surface of the top passivation layer is substantially planar (“The end surface of diffusion prevention plug 4 becomes an substantially flat surface” para. 0080).
Regarding claim 23, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein a widest dimension of the copper pillar is less than a lesser of a width and a length dimension of the die pad (“protrusion electrode 7” is made in the “opening 6a” of “resist film 6” and is shown as being narrower than “electrode pad 3” since portions of “resist film 6” overlap the “electrode pad 3”, para. 0083).
Regarding claim 24, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein an outer perimeter portion of the conductive probe plug overlaps a portion of the top surface of the top passivation layer (“diffusion prevention plug 4” is formed such that “when opening 8a is completely filled, the film resulting from the plating grows so as to expand to a region wider than opening 8a”, para. 0079, and is shown as overlapping a portion of “passivation film 8”).
Regarding claim 25, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the substantially planar portion of the top surface of the conductive probe plug substantially spans a width of the opening (the planar top surface of “diffusion prevention plug 4” spans the width of “opening 8a” as seen in FIG. 1).
Regarding claim 26, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the conductive probe plug is formed directly on the die pad (“diffusion prevention plug 4 is formed by means of electroless plating so as to substantially completely coat electrode pad 3” as seen in the “opening 8a”, para. 0080); and
the copper pillar is formed directly on the conductive probe plug (“protrusion electrode 7” and “seed layer 5”, now made of copper as modified, is formed on “diffusion prevention plug 4”, para. 0082 and 0085).
Regarding claim 27, Tanida, modified by Breuer, teaches the semiconductor device of claim 16, wherein the lower portion of the copper pillar contacts the top surface of the top passivation layer (part of “seed layer 5” is formed on “passivation film 8”, para. 0082).
Regarding claim 28, Tanida, modified by Breuer, teaches the semiconductor device of claim 27, wherein a bottom circumference of the copper pillar surrounds a perimeter of the conductive probe plug (“protrusion electrode 7” is made in the “opening 6a” of “resist film 6” and is shown as being narrower than “electrode pad 3” since portions of “resist film 6” overlap the “electrode pad 3”, para. 0083. As such, “seed layer 5” and “protrusion electrode 7” have portions around the “diffusion prevention plug 4”.).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898