DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 6-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SUKEKAWA et al. (US 20210005611 A1, hereinafter Sukekawa)
With regards to claim 1, Sukekawa discloses a semiconductor structure, (FIG. 7B) comprising a plurality of memory cells (memory cells 10) located on a substrate, (handle substrate 94) each of the plurality of memory cells comprising:
a transistor; (transistor including at least word line 58, channel 25, and source/drain 22) and
a capacitor (at least capacitor 110,106, and 108) electrically connected to the transistor and located above the transistor along a third direction, (-Z direction) wherein the third direction is perpendicular to a top surface of the substrate, (See FIG. 7B, where the -Z direction is perpendicular to the top surface of the substrate 94) and
wherein the capacitor comprises a body portion, (at least portion comprising layers 110 and side portions of electrode 106) and at least one extension portion (extension portion of layer 106 contacting the source/drain electrode 22) located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion, (see FIG. 7B)
wherein a width of a projection of the at least one extension portion on the substrate along a first direction is greater than a width of a projection of the body portion on the substrate along the first direction, and the body portion is electrically connected to the transistor; (see FIG. 7B, where the width of electrode extension 106 is larger than the width of at side portion of electrode 106)
a corner structure (at least corner structure shown in annotated FIG. 7B) is formed by a intersection of the body portion and at least one extension portion, which increases the dimension and the capacitance of the capacitor. (See FIG. 7B, where the corner increases the dimensions of the capacitor relative to the portion 106, which based on the equation for capacitance (C = k e0 A/thickness, where C is capacitance, and A is area), the increase in area increases the capacitance, see also Response to Arguments)
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With regards to claim 4, Sukekawa discloses the semiconductor structure of claim 1, wherein the transistor comprises:
source electrode/drain electrode, (source/drain 22) one of the source electrode/drain electrode being electrically connected to the capacitor;
a channel layer (channel 25) located between the source electrode and the drain electrode of the source electrode/drain electrode; (see FIG. 7B) and
a gate electrode, (word line 58) the channel layer surrounding at least a portion of the gate electrode. (see FIG. 7B)
With regards to claim 6, Sukekawa discloses the semiconductor structure of claim 1, wherein the capacitor comprises:
a lower electrode layer, (lower electrode 106) comprising a first sub-lower electrode layer, (extending portion of 106 contacting source/drain 22) and a second sub-lower electrode layer (electrode layer 106 directly contacting dielectric 108) intersecting with the first sub-lower electrode layer, the lower electrode layer being in contact with the transistor and being electrically connected to the transistor; (see FIG. 7B, showing the contact to at least the source/drain 22 of the transistor)
a dielectric layer (dielectric 108) covering an inner surface of the lower electrode layer; (see FIG. 7B) and
an upper electrode layer (upper electrode 110) covering a surface of the dielectric layer,
wherein the first sub-lower electrode layer defines a position of the at least one extension portion, and the second sub-lower electrode layer defines a position of the body portion. (see FIG. 7B)
With regards to claim 7, Sukekawa discloses the semiconductor structure of claim 1, wherein the capacitor comprises:
a lower electrode layer, (lower electrode 106) comprising a first sub-lower electrode layer, (extending portion of 106 contacting source/drain 22) and a second sub-lower electrode layer (electrode layer 106 directly contacting dielectric 108) intersecting with the first sub-lower electrode layer, the lower electrode layer being in contact with the transistor and being electrically connected to the transistor; (see FIG. 7B, showing the contact to at least the source/drain 22 of the transistor)
a dielectric layer (dielectric 108) continuously wrapping a surface of the lower electrode layer; (see FIG. 7B) and
an upper electrode layer (upper electrode 110) covering a surface of the dielectric layer,
wherein the first sub-lower electrode layer defines a position of the at least one extension portion, and the second sub-lower electrode layer defines a position of the body portion. (see FIG. 7B)
With regards to claim 8, Sukekawa discloses the semiconductor structure of claim 1, wherein the transistor is located below the capacitor, and
a first isolation layer (at least insulative material 112, insulative material 40, and dielectric 52) is arranged between the transistor and the capacitor,
wherein the body portion of the capacitor penetrates through the first isolation layer to be electrically connected to the transistor. (See FIGS. 4B-7B, showing the penetration)
With regards to claim 9, Sukekawa discloses the semiconductor structure of claim 1, wherein the plurality of memory cells are arranged in an array along a first direction and a second direction, the first direction and the second direction are directions parallel to a top surface of the substrate, and the first direction intersects with the second direction; (see FIGS. 4A-7B, showing the array of memory devices)
the semiconductor structure further comprises:
a plurality of word lines (word lines 58) extending along the second direction, each of the plurality of word lines being electrically connected to respective ones of the plurality of memory cells arranged in the second direction; and
a plurality of bit lines (bit lines 32) extending along the first direction, the plurality of bit lines being located below the plurality of word lines, and each of the plurality of bit lines being electrically connected to respective ones of the plurality of memory cells arranged in the first direction. (see FIG. 7B, showing the placements)
With regards to claim 10, Sukekawa discloses the semiconductor structure of claim 1, wherein the plurality of memory cells are stacked onto one another along a third direction, wherein the third direction is a direction perpendicular to a top surface of the substrate. (See FIG. 7A-7B, showing the stacking in the third direction)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over SUKEKAWA et al. (US 20210005611 A1, hereinafter Sukekawa)
With regards to claim 2, Sukekawa discloses the semiconductor structure of claim 1.
However, Sukekawa does not explicitly teach wherein the capacitor comprises a plurality of extension portions, and the plurality of extension portions are distributed at least on one side of the body portion.
It should be noted that the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. (See MPEP 2144.04 VI. B)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device of Sukekawa to have multiple extension portions for at least controlling connection to the source/drain.
With regards to claim 3, Sukekawa discloses the semiconductor structure of claim 1.
However, Sukekawa does not explicitly teach wherein the capacitor comprises a plurality of extension portions, and the plurality of extension portions are distributed on two opposite sides of the body portion at least along a first direction, wherein the first direction is a direction parallel to a top surface of the substrate.
It should be noted that the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. (See MPEP 2144.04 VI. B)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the device of Sukekawa to have multiple extension portions for at least controlling connection to the source/drain.
Response to Arguments
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive.
Applicant essentially argues 1) Sukekawa does not teach the capacitor above the transistor in a third direction, and 2) Sukekawa does not teach the corner structure.
With regards to 1) Examiner notes that the capacitor is above the transistor in the -Z direction (i.e. from the top of the page to the bottom of the page in FIG. 7B). Therefore, this limitation is taught.
With regards to 2), as stated above, Examiner notes that the corner structure exists in the capacitor and joins the two portions together, as stated above.
Therefore, claim 1 is properly rejected, and claims 2-10 are rejected for at least their dependencies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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