DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 10-11 are objected to because of the following informalities:
In claim 1, line 2, “the multilayer substrate comprising" should read “the multilayer substrate comprises".
In claim 1, line 4, "a non-wired region insulating the vias and other wirings and" should read “a non-wired region, which insulates the vias and other wirings, and"
In claim 10, line 1, “to any one of claims 7" should read “to claim 7”.
In claim 11, line 4, “the multilayer substrate comprising" should read “the multilayer substrate comprises".
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5, 7-8 and 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinji et al. (JP 2012037689 from IDS) in view of Sakamoto et al. (US 20190098752 from IDS).
Regarding claim 1, Shinji teaches a multilayer substrate (fig. 13, mounting substrate 15; para. 0084) on which an image sensor (fig. 11, image sensor 1b mounted on 15; para. 0084) is mounted and which includes a plurality of conductive layers (conductive layers 155; para. 0084), the multilayer substrate (15) comprising:
a light-shielding portion (light shielding member 8 and 155; para. 0084) configured to shield light (block light; para. 0084) transmitted through a non-wired region (through hole 159; para. 0084) and traveling to the image sensor (1b).
Shinji fails to explicitly teach a plurality of vias piled and connected in a straight line; and
the non-wired region insulating the vias and other wirings.
However, Sakamoto teaches a plurality of vias (Sakamoto: fig. 1, first via conductors 156F, through-hole conductors 36, third via conductors 376F; para. 0013, 0014, 0018) piled and connected (electronically) in a straight line (vertical line); and
the non-wired region (Sakamoto: first resin insulating layers 150F, third resin insulating layers 170F with opening for through light; para. 0014, 0018, similar to 159 of Shinji) insulating the vias (Sakamoto: 156F, 376F) and other wirings (Sakamoto: first conductor layers 158F, third conductor layers 178F for wiring connection; para. 0014, 0018).
Sakamoto and Shinji are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the details of vias piled and connected in a straight line and the non-wired region insulating the vias and other wirings as taught by Sakamoto.
Doing so would realize via structure to connect conductor layers with more connection reliability (Sakamoto: para. 0063).
Regarding claim 2, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 1, wherein the light-shielding portion (Sakamoto: fig. 1, 158F, 178F, first via lands 156FL on fifth conductor layer 34F; para. 0015, similar to 155 of Shinji) is a land (Sakamoto: 156FL is a land; para. 0015) of the via (Sakamoto: 156F) formed in a range broader (Shinji: 155 is broader than 159, and similar to Sakamoto: bottom 156FL layer on 34F is broader than small through openings of 150F) than the non-wired region (Shinji: 159, similar to Sakamoto: small through openings of 150F) of another conductive layer (Sakamoto: another 158F layer above with small through openings) in at least one conductive layer (Sakamoto: 158F).
Regarding claim 3, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 2, wherein the land (Sakamoto: fig. 1, 156FL on 34F) is a land (Sakamoto: 156FL is a land; para. 0015) of a via (Sakamoto: through-hole conductors 36; para. 0013) of a core layer (Sakamoto: core layer 20; para. 0013).
Regarding claim 5, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 1, wherein the multilayer substrate (Sakamoto: fig. 1, printed wiring board 10; para. 0010, similar to 15 of Shinji) is a build-up substrate (Sakamoto: substrate with build-up layer Bu1, Bu2; para. 0010).
Regarding claim 7, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 1, wherein the light-shielding portion (Shinji: fig. 11, 8, 155) is provided on a surface (Shinji: top surface) of a solder resist (Sakamoto: fig. 1, first solder resist layer 90F and second solder resist layer 90S; para. 0011, similar to surfaces of 15 of Shinji).
Regarding claim 8, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 7, wherein the light-shielding portion (Shinji: fig. 11, 8) is one of a printed silk layer, a light-shielding sheet (Shinji: light shielding coating; para. 0012), and an adhesive with a light-shielding property.
Regarding claim 10, Shinji in view of Sakamoto further teaches the multilayer substrate according to any one of claims 7, wherein the solder resist (Sakamoto: fig. 1, 90F, 90S) is a solder resist (Sakamoto: 90F, 90S are solder resist) on an image sensor side (Shinji: fig. 11, 90F, 90S of Sakamoto as part of 15 on top side of 1b).
Regarding claim 11, Shinji teaches an image sensor unit (optical unit 100; para. 0083) comprising:
a multilayer substrate (fig. 13, mounting substrate 15; para. 0084) including a plurality of conductive layers (conductive layers 155; para. 0084); and
an image sensor (fig. 11, image sensor 1b mounted on 15; para. 0084) mounted on the multilayer substrate (15),
wherein the multilayer substrate (15) comprising:
a light-shielding portion (light shielding member 8 and 155; para. 0084) configured to shield light (block light; para. 0084) transmitted through a non-wired region (through hole 159; para. 0084) and traveling to the image sensor (1b).
Shinji fails to explicitly teach a plurality of vias piled and connected in a straight line; and
the non-wired region insulating the vias and other wirings.
However, Sakamoto teaches a plurality of vias (Sakamoto: fig. 1, first via conductors 156F, through-hole conductors 36, third via conductors 376F; para. 0013, 0014, 0018) piled and connected (electronically) in a straight line (vertical line); and
the non-wired region (Sakamoto: first resin insulating layers 150F, third resin insulating layers 170F with through opening for light; para. 0014, 0018, similar to 159 of Shinji) insulating the vias (Sakamoto: 156F, 376F) and other wirings (Sakamoto: first conductor layers 158F, third conductor layers 178F for wiring connection; para. 0014, 0018).
Sakamoto and Shinji are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the details of vias piled and connected in a straight line and the non-wired region insulating the vias and other wirings as taught by Sakamoto.
Doing so would realize via structure to connect conductor layers with more connection reliability (Sakamoto: para. 0063).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinji in view of Sakamoto as applied to claim 1 above, and further in view of Keiji et al. (JP 2016046270 from IDS).
Regarding claim 4, Shinji in view of Sakamoto teaches the multilayer substrate according to claim 1 including the multilayer substrate (Shinji: fig. 11, 15).
Shinji in view of Sakamoto fails to explicitly teach the multilayer substrate is an any-layer substrate.
However, Keiji teaches the multilayer substrate (Keiji: fig. 4, printed circuit board 10a; para. 0038, similar to 15 of Shinji) is an any-layer substrate (Keiji: so-called any-layer board; para. 0038).
Keiji, Sakamoto and Shinji are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the multilayer substrate is an any-layer substrate.
Doing so would realize an any-layer board are formed by laser via holes to reduce manufacturing costs (Keiji: para. 0038).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinji in view of Sakamoto as applied to claim 1 above, and further in view of Yukihiko et al. (JP 2002280737 from IDS).
Regarding claim 6, Shinji in view of Sakamoto teaches the multilayer substrate according to claim 1 including the via (Sakamoto: fig. 1, 156F).
Shinji in view of Sakamoto fails to explicitly teach the via is a high-speed transmission wiring.
However, Yukihiko teaches the via (Yukihiko: via hole; para. 0006, similar to 156F of Sakamoto) is a high-speed transmission wiring (Yukihiko: higher speed stacked via structure; para. 0006).
Yukihiko, Sakamoto and Shinji are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the via as a high-speed transmission wiring.
Doing so would realize a high-speed via structure for higher speed and higher density multilayer printed wiring board (Yukihiko: para. 0006).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shinji in view of Sakamoto as applied to claim 1 above, and further in view of Wang et al. (US 20210384368).
Regarding claim 9, Shinji in view of Sakamoto further teaches the multilayer substrate according to claim 1 including the light-shielding portion (fig. 11, 8, 155).
Shinji in view of Sakamoto fails to explicitly teach the light-shielding portion is a black solder resist.
However, Wang teaches the light-shielding portion (Wang: fig. 1, first light-shielding layer 21; para. 0039, similar to 8, 155 of Shinji) is a black solder resist (Wang: black solder resist material; para. 0039).
Wang, Sakamoto and Shinji are considered to be analogous to the claimed invention because they are in the same field of semiconductor devices.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the light-shielding portion is a black solder resist.
Doing so would realize a black solder resist light-shielding to improving the quality of the image signal (Wang: para. 0004). Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818