CTNF 18/171,384 CTNF 93533 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-31 AIA The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Examiner Notes Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The entire reference is considered to provide disclosure relating to the claimed invention. The claims & only the claims form the metes & bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner's Notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent & spirit of compact prosecution. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: Claim 15 recites “A circuit simulation management system, comprising: a model generation system; and a model interface (MI) configured to communicate with the model generation system,” A review of the specification shows that the following appears to be the corresponding structure described in the specification for the 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph limitation: [0101] Fig. 8-9. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. These claims are directed to an abstract idea without significantly more. As to claim 1, Step 1: Claim 1 is directed to a method. Therefore, the claim is eligible under Step 1 for being directed to processes. Step 2A Prong One Claim 1 recites accessing the semiconductor device characterization description; accessing a first starter code; (collecting input data) generating a first model authentication code (MAC) based on the semiconductor device characterization description and the first starter code; (mental process) and transmitting the first starter code, the first MAC, and the semiconductor device characterization description to a model interface (MI). (generic computer function) The claimed concept is a method of generating authentication code based on description / information directed to “Mental Process” grouping. These limitations can be performed in a human mind or using pen and paper. Therefore, claim 1 is an abstract idea. Step 2A Prong Two The collecting data step is recited at a high level of generality ( i.e. , as a general means of collecting input for use in the evaluation step) and amounts to mere data collecting, which is a form of insignificant extra-solution activity. The claim recites additional elements such as “model interface”. Each of the additional limitations is no more than mere instructions to apply the exception using a generic computer component. Simply implementing the abstract idea on a generic computer is not a practical application of the abstract idea. See applicant’s specification [0114] Fig. 9 for generic computer description. The judicial exception is not integrated into a practical application. Step 2B: The same analysis of Step 2A Prong Two applies here in 2B. The present claim does not recite any limitation that would integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. See MPEP 2106.05(d). The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Thus, claim 1 is not patent eligible. Same conclusion for dependent claims of claim 1. See below. 2. The method of claim 1, wherein the semiconductor device characterization description comprises one or more parameters for a semiconductor circuit simulator to simulate one or more semiconductor devices. (data description) 3. The method of claim 1, wherein the first MAC is generated using a MAC generation algorithm. (mental process) 4. The method of claim 1, further comprising: accessing a second starter code; (input) generating a second MAC based on the semiconductor device characterization description and the second starter code; (mental process) and transmitting the second MAC to the MI. (generic computer function) 5. The method of claim 1, further comprising: accessing an expiration date for the semiconductor device characterization description; and transmitting the expiration date to the MI. (generic computer function) 6. The method of claim 1, wherein the MI is configured to generate a second MAC. (mental process) Same conclusion for independent claims 7, 15 and dependent claims. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception. In particular, the claim limitations do not recite a combination of additional elements that tie or “integrate the invention into a practical application”. Thus, claims 1-20 are not patent eligible. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim(s) 1-4, 6- 12, 15-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marson et al (US 2021/0056053 A1), hereinafter Marson, in view of Chen et al (US 2020/0081785 A1), hereinafter Chen. 1. A meth od of using a semiconductor device characterization description, the method comprising: Marson discloses the semiconductor device characterization description; Marson: [0066] for semiconductor device characterization description. accessing a first starter code; Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224.” Marson discloses generating a first model authentication code (MAC) based on the semiconductor device characterization description and the first starter code; and transmitting the first starter code, the first MAC, and the semiconductor device characterization description to a model interface (MI). Marson [0023] “… The application 110 provides the authentication tag to the NVM controller in a registration process. After the registration process, in order to gain access to the NVM device(s), the application 110 can send an authentication request with the application ID and receives the first authentication nonce (e.g., AARN.sub.i) and a second authentication nonce (e.g., AARN.sub.i+1). The application 110 can send an access request with the authentication key and a second authentication tag. The NVM controller verifies that a result of hashing the first authentication key matches the first authentication tag. Additional details of the registration process and the authentication process are described below.” See [0026] for additional detail. See [0018] for detail of “model interface”. Marson does not appear to explicitly disclose accessing the semiconductor device characterization description. However, Chen discloses accessing the semiconductor device characterization description [0084] “… In the illustrated embodiment, semiconductor fabrication system 920 is configured to process the design information 915 stored on non-transitory computer-readable storage medium 910 and fabricate integrated circuit 930 based on the design information 915.” Fig. 9 and [0086] for additional detail of semiconductor device characterization description. Marson and Chen are analogous art because they are from the “same field of endeavor” software analysis. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Marson and Chen before him or her, to modify the method of Marson to include the monitoring feature of Chen because this combination improves the performance of the application. The suggestion/motivation for doing so would have been Chen [0020] “… The embodiments illustrated in the drawing and described below may provide techniques for monitoring program flow during execution of a software program or application, and detecting unintended changes in program flow, thereby improving the security of the computer system, without the added expense of redundancy.” Therefore, it would have been obvious to combine Marson and Chen to obtain the invention as specified in the instant claim(s). 2. The method of claim 1, Chen discloses wherein the semiconductor device characterization description comprises one or more parameters for a semiconductor circuit simulator to simulate one or more semiconductor devices. Chen [0039-0041] “As described above, software fault monitor circuit relies upon checkpoint data structures embedded within the code of a software program or application to determine if the order of execution of the software program or application is correct. An embodiment of such a data structure is depicted in the block diagram of FIG. 3. In the illustrated embodiment, checkpoint data structure 300 includes curve value 301, comp value 302, config value 303, and helper value 304. …” 3. The method of claim 1, Marson discloses wherein the first MAC is generated using a MAC generation algorithm. Marson: [0016] “… The application 110 is capable of computing cryptographic hashes and Message Authentication Codes (MACs). The application may also have the capability to encrypt and MAC data. The application 110 includes an authentication manager 120 that is capable of generating a set of memory addresses associated with its own set of program instructions. For example, the authentication manager 120 can use a nonce (random or pseudo random) and an address generation algorithm to generate the memory addresses. These memory addresses can be used to generate an authentication tag (AT) based on the application's own code. The AT can be considered a fingerprint or signature of at least some of the application's code. For example, the address generation algorithm can use a standard pseudo random number generation (PRNG) process that is seeded with the nonce. The resource controller 104 can provide the nonce to the authentication manager 120 to generate the AT. The output of the PRNG process can be modified to correspond to appropriate memory addresses where the application 110 is stored in system memory 140. Alternatively, a proprietary algorithm can receive the nonce from the resource controller 104 and output a set of memory addresses.” 4. The method of claim 1, Marson discloses further comprising: accessing a second starter code; generating a second MAC based on the semiconductor device characterization description and the second starter code; and transmitting the second MAC to the MI. Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” 6. The method of claim 1, Marson discloses wherein the MI is configured to generate a second MAC. Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” 7. A method of using a model interface, the method comprising: Marson discloses a valid semiconductor device characterization description; Marson: [0066] for semiconductor device characterization description. Marson discloses receiving a first starter code; Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224.” Marson discloses a stored semiconductor device characterization description; Marson: [0066] for semiconductor device characterization description. Marson discloses receiving a first model authentication code (MAC); accessing the first starter code; accessing the first MAC; Marson [0023] “… The application 110 provides the authentication tag to the NVM controller in a registration process. After the registration process, in order to gain access to the NVM device(s), the application 110 can send an authentication request with the application ID and receives the first authentication nonce (e.g., AARN.sub.i) and a second authentication nonce (e.g., AARN.sub.i+1). The application 110 can send an access request with the authentication key and a second authentication tag. The NVM controller verifies that a result of hashing the first authentication key matches the first authentication tag. Additional details of the registration process and the authentication process are described below.” See [0026] for additional detail. Marson discloses generating a second MAC based on the stored semiconductor device characterization description and the first starter code; Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” Marson discloses comparing the first MAC and the second MAC. Marson: [0043] “… The processing logic receives an access request, the first AK, and a second AT from the application. The second AT is derived by the application. The processing logic verifies that a result of hashing the first AK equals the first AT. The processing logic marks, the second AARN and the second AT in the table as valid responsive to the result being equal to the first AT; otherwise, the process is aborted.” Marson does not appear to explicitly disclose receiving a valid semiconductor device characterization description; accessing a stored semiconductor device characterization description; However, Chen discloses receiving a valid semiconductor device characterization description; accessing a stored semiconductor device characterization description; [0084] “… In the illustrated embodiment, semiconductor fabrication system 920 is configured to process the design information 915 stored on non-transitory computer-readable storage medium 910 and fabricate integrated circuit 930 based on the design information 915.” Fig. 9 and [0086] for additional detail of semiconductor device characterization description. Marson and Chen are analogous art because they are from the “same field of endeavor” software analysis. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Marson and Chen before him or her, to modify the method of Marson to include the monitoring feature of Chen because this combination improves the performance of the application. The suggestion/motivation for doing so would have been Chen [0020] “… The embodiments illustrated in the drawing and described below may provide techniques for monitoring program flow during execution of a software program or application, and detecting unintended changes in program flow, thereby improving the security of the computer system, without the added expense of redundancy.” Therefore, it would have been obvious to combine Marson and Chen to obtain the invention as specified in the instant claim(s). 8. The method of claim 7, Marson discloses wherein the first MAC was generated using a particular MAC generation algorithm with the first starter code and the valid semiconductor device characterization description. Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224. The address generation engine 224 can receive a nonce as an input and can generate a select a set of memory addresses associated with a set of program instructions of the application 110. In one embodiment, the address generation engine 224 can use an address generation algorithm to generate the memory addresses. These memory addresses can be used to generate an authentication tag (AT) based on the application's own code. The AT can be considered a fingerprint or signature of at least some of the application's code. For example, the address generation algorithm can use a standard PRNG process that is seeded with the nonce. The output of the PRNG process can be modified to correspond to appropriate memory addresses where the application 110 is stored in system memory 140. Alternatively, a proprietary algorithm can receive the nonce from the resource controller 104 and output a set of memory addresses. The values stored at these memory addresses can be used to generate the AT (e.g., fingerprint or signature) of at least a portion of the application 110. In one embodiment, the address generation engine 224 can access the memory address and can use the values stored at those memory addresses to generate the authentication key (AK) and the cryptographic hash engine 226 can hash the AK to generate the authentication tag (AT). In another embodiment, the key generation engine 223 can receive the memory addresses that are output from the address generation engine 224 and can generate the AK using the values at the memory addresses identified by the address generation engine 224. The cryptographic hash engine 226 can receive the AK from the key generation engine 223 and can hash the AK to generate the AT.” 9. The method of claim 8, Marson discloses wherein the second MAC is generated using the particular MAC generation algorithm. Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224. The address generation engine 224 can receive a nonce as an input and can generate a select a set of memory addresses associated with a set of program instructions of the application 110. In one embodiment, the address generation engine 224 can use an address generation algorithm to generate the memory addresses. These memory addresses can be used to generate an authentication tag (AT) based on the application's own code. The AT can be considered a fingerprint or signature of at least some of the application's code. For example, the address generation algorithm can use a standard PRNG process that is seeded with the nonce. The output of the PRNG process can be modified to correspond to appropriate memory addresses where the application 110 is stored in system memory 140. Alternatively, a proprietary algorithm can receive the nonce from the resource controller 104 and output a set of memory addresses. The values stored at these memory addresses can be used to generate the AT (e.g., fingerprint or signature) of at least a portion of the application 110. In one embodiment, the address generation engine 224 can access the memory address and can use the values stored at those memory addresses to generate the authentication key (AK) and the cryptographic hash engine 226 can hash the AK to generate the authentication tag (AT). In another embodiment, the key generation engine 223 can receive the memory addresses that are output from the address generation engine 224 and can generate the AK using the values at the memory addresses identified by the address generation engine 224. The cryptographic hash engine 226 can receive the AK from the key generation engine 223 and can hash the AK to generate the AT.” 10. The method of claim 7, further comprising: Chen discloses in response to the first MAC and the second MAC being identical, transmitting an allow simulation signal to a simulator, the allow simulation signal configured to allow a semiconductor circuit to be simulated using the stored semiconductor device characterization description; and in response to the first MAC and the second MAC not being identical, transmitting a disallow simulation signal to the simulator, the disallow simulation signal configured to prevent the semiconductor circuit from being simulated using the stored semiconductor device characterization description. Chen [0034] Hash circuit 202 is configured to generate X-value 207 using config value 205, comparison result 203, and curve value 204. In various embodiments, hash circuit 202 may be configured to generate a 64-bit message authentication code (commonly referred to as a “MAC”). Chen [0037] “As described below in more detail in regard to FIG. 6, check circuit 213 may use X-value 207 and Y-value 206 to determine if the current shared information matches the expected shared information. This is accomplished by using by combining X-value 207, and the values a and b from the previously received checkpoint data structure according to Equation 1 and determining if the result is the same as Y-value 206. If the result is the same, then no fault is detected. If the result of the calculation is not the same, then check circuit 213 generates program flow error signal 105.” Examiner considers “disallow simulation signal” as program flow error signal. 11. The method of claim 7, Marson discloses further comprising: receiving a second starter code; receiving a third MAC; accessing the second starter code; accessing the second MAC; generating a fourth MAC based on the stored semiconductor device characterization description and the second starter code; and comparing the third MAC and the fourth MAC. Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” 12. The method of claim 11, Marson discloses wherein the third MAC was generated using a particular MAC generation algorithm with the second starter code and the valid semiconductor device characterization description, wherein the fourth MAC is generated using the particular MAC generation algorithm with the first starter code and the stored semiconductor device characterization description, Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” Chen discloses wherein the method further comprises: in response to the third MAC and the fourth MAC being identical, transmitting an allow simulation signal to a simulator, the allow simulation signal configured to allow a semiconductor circuit to be simulated using the stored semiconductor device characterization description; and in response to the third MAC and the fourth MAC not being identical, transmitting a disallow simulation signal to the simulator, the disallow simulation signal configured to prevent the semiconductor circuit from being simulated using the stored semiconductor device characterization description. Chen [0034] Hash circuit 202 is configured to generate X-value 207 using config value 205, comparison result 203, and curve value 204. In various embodiments, hash circuit 202 may be configured to generate a 64-bit message authentication code (commonly referred to as a “MAC”). Chen [0037] “As described below in more detail in regard to FIG. 6, check circuit 213 may use X-value 207 and Y-value 206 to determine if the current shared information matches the expected shared information. This is accomplished by using by combining X-value 207, and the values a and b from the previously received checkpoint data structure according to Equation 1 and determining if the result is the same as Y-value 206. If the result is the same, then no fault is detected. If the result of the calculation is not the same, then check circuit 213 generates program flow error signal 105.” Examiner considers “disallow simulation signal” as program flow error signal. 15. A circuit simulation management system, comprising: a model generation system; and a model interface (MI) configured to communicate with the model Marson discloses generation system, wherein the model generation system is configured to: Marcon [0059] FIG. 9. Marson discloses a valid semiconductor device characterization description; Marson: [0066] for semiconductor device characterization description. Marson discloses access a first starter code; Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224.” Marson discloses generate a first model authentication code (MAC) based on the valid semiconductor device characterization description and the first starter code; and transmit the first starter code, the first MAC, and the valid semiconductor device characterization description to the MI, Marson [0023] “… The application 110 provides the authentication tag to the NVM controller in a registration process. After the registration process, in order to gain access to the NVM device(s), the application 110 can send an authentication request with the application ID and receives the first authentication nonce (e.g., AARN.sub.i) and a second authentication nonce (e.g., AARN.sub.i+1). The application 110 can send an access request with the authentication key and a second authentication tag. The NVM controller verifies that a result of hashing the first authentication key matches the first authentication tag. Additional details of the registration process and the authentication process are described below.” See [0026] for additional detail. See [0018] for detail of “model interface”. Marson discloses wherein the MI is configured to: a stored semiconductor device characterization description; Marson: [0066] for semiconductor device characterization description. Marson discloses generate a second MAC based on the stored semiconductor device characterization description and the first starter code; Marson [0017] “In some implementations, a subcomponent of the resource controller 104 (e.g., authentication manager 122) provides both a first nonce to the application 110 to generate the authentication tag as well as a second nonce to the application 110 to generate a key, such as an encryption key for encrypting data or a signing key for signing data, or both. In other implementations, the resource controller 104 provides three separate nonces—a first nonce for generating the authentication tag, a second nonce for generating the encryption key, and a third nonce for generating the signing key. Alternatively, the resource controller 104 provides a single nonce and the application 110 derives one or more keys from the single nonce. When deriving multiple keys from the same nonce, the application 110 can generate keys that are cryptographically separated keys.” Marson discloses compare the first MAC and the second MAC. Marson: [0043] “… The processing logic receives an access request, the first AK, and a second AT from the application. The second AT is derived by the application. The processing logic verifies that a result of hashing the first AK equals the first AT. The processing logic marks, the second AARN and the second AT in the table as valid responsive to the result being equal to the first AT; otherwise, the process is aborted.” Marson does not appear to explicitly disclose accessing a valid semiconductor device characterization description; accessing a stored semiconductor device characterization description; However, Chen discloses accessing a valid semiconductor device characterization description; accessing a stored semiconductor device characterization description; [0084] “… In the illustrated embodiment, semiconductor fabrication system 920 is configured to process the design information 915 stored on non-transitory computer-readable storage medium 910 and fabricate integrated circuit 930 based on the design information 915.” Fig. 9 and [0086] for additional detail of semiconductor device characterization description. Marson and Chen are analogous art because they are from the “same field of endeavor” software analysis. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Marson and Chen before him or her, to modify the method of Marson to include the monitoring feature of Chen because this combination improves the performance of the application. The suggestion/motivation for doing so would have been Chen [0020] “… The embodiments illustrated in the drawing and described below may provide techniques for monitoring program flow during execution of a software program or application, and detecting unintended changes in program flow, thereby improving the security of the computer system, without the added expense of redundancy.” Therefore, it would have been obvious to combine Marson and Chen to obtain the invention as specified in the instant claim(s). 16. The circuit simulation management system of claim 15, Marson discloses wherein the first MAC was generated using a particular MAC generation algorithm with the first starter code and the valid semiconductor device characterization description. Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224. The address generation engine 224 can receive a nonce as an input and can generate a select a set of memory addresses associated with a set of program instructions of the application 110. In one embodiment, the address generation engine 224 can use an address generation algorithm to generate the memory addresses. These memory addresses can be used to generate an authentication tag (AT) based on the application's own code. The AT can be considered a fingerprint or signature of at least some of the application's code. For example, the address generation algorithm can use a standard PRNG process that is seeded with the nonce. The output of the PRNG process can be modified to correspond to appropriate memory addresses where the application 110 is stored in system memory 140. Alternatively, a proprietary algorithm can receive the nonce from the resource controller 104 and output a set of memory addresses. The values stored at these memory addresses can be used to generate the AT (e.g., fingerprint or signature) of at least a portion of the application 110. In one embodiment, the address generation engine 224 can access the memory address and can use the values stored at those memory addresses to generate the authentication key (AK) and the cryptographic hash engine 226 can hash the AK to generate the authentication tag (AT). In another embodiment, the key generation engine 223 can receive the memory addresses that are output from the address generation engine 224 and can generate the AK using the values at the memory addresses identified by the address generation engine 224. The cryptographic hash engine 226 can receive the AK from the key generation engine 223 and can hash the AK to generate the AT.” 17. The circuit simulation management system of claim 16, Marson discloses wherein the second MAC is generated using the particular MAC generation algorithm. Marson: [0025] “… For example, the random number generator 232 can generate an AARN, an ERN, and a DARN and provide these nonces to the application 110. The nonce can be a seed value used by the address generation engine 224. The address generation engine 224 can receive a nonce as an input and can generate a select a set of memory addresses associated with a set of program instructions of the application 110. In one embodiment, the address generation engine 224 can use an address generation algorithm to generate the memory addresses. These memory addresses can be used to generate an authentication tag (AT) based on the application's own code. The AT can be considered a fingerprint or signature of at least some of the application's code. For example, the address generation algorithm can use a standard PRNG process that is seeded with the nonce. The output of the PRNG process can be modified to correspond to appropriate memory addresses where the application 110 is stored in system memory 140. Alternatively, a proprietary algorithm can receive the nonce from the resource controller 104 and output a set of memory addresses. The values stored at these memory addresses can be used to generate the AT (e.g., fingerprint or signature) of at least a portion of the application 110. In one embodiment, the address generation engine 224 can access the memory address and can use the values stored at those memory addresses to generate the authentication key (AK) and the cryptographic hash engine 226 can hash the AK to generate the authentication tag (AT). In another embodiment, the key generation engine 223 can receive the memory addresses that are output from the address generation engine 224 and can generate the AK using the values at the memory addresses identified by the address generation engine 224. The cryptographic hash engine 226 can receive the AK from the key generation engine 223 and can hash the AK to generate the AT.” 18. The circuit simulation management system of claim 15, Chen discloses wherein the MI is further configured to: communicate with a semiconductor circuit simulator; in response to the first MAC and the second MAC being identical, transmit an allow simulation signal to a simulator, the allow simulation signal configured to allow a semiconductor circuit to be simulated using the stored semiconductor device characterization description; and in response to the first MAC and the second MAC not being identical, transmit a disallow simulation signal to the simulator, the disallow simulation signal configured to prevent the semiconductor circuit from being simulated using the stored semiconductor device characterization description. Chen [0034] Hash circuit 202 is configured to generate X-value 207 using config value 205, comparison result 203, and curve value 204. In various embodiments, hash circuit 202 may be configured to generate a 64-bit message authentication code (commonly referred to as a “MAC”). Chen [0037] “As described below in more detail in regard to FIG. 6, check circuit 213 may use X-value 207 and Y-value 206 to determine if the current shared information matches the expected shared information. This is accomplished by using by combining X-value 207, and the values a and b from the previously received checkpoint data structure according to Equation 1 and determining if the result is the same as Y-value 206. If the result is the same, then no fault is detected. If the result of the calculation is not the same, then check circuit 213 generates program flow error signal 105.” Examiner considers “disallow simulation signal” as program flow error signal . Allowable Subject Matter Claims 5, 13-14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and to overcome the rejection(s) under 35 U.S.C. 101. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Marson et al (US 2021/0056053 A1) teaches a method for application authentication and/or data encryption without stored pre-shared keys. The processing device provides a current nonce responsive to the application ID and provides the application access to the system resource responsive to determining that a hash of a current key received from the application equals a current tag. The current key is generated by the application based on code of the application and the current nonce. The current tag was previously provided from the application to the resource controller. The current tag can also be hashed by the application using the current key. Kataria et al (US 20220027519 A1) teach a debug circuit configured to implement one or more debug features for the one or more functional circuits, and a validation circuit. The validation circuit is configured to receive a request to access debug features, and to send an identification value corresponding to the apparatus. The validation circuit is further configured to receive a certificate generated by a server computer system, the certificate including encoded debug permissions, and to decode the debug permissions using the identification value. Using the decoded debug permissions, the validation circuit is further configured to enable one or more of the debug features. Chen et al (US 20200081785 A1) teach a method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error. Ghose (US 8782435 B1) teach a simple hardware mechanism for validating the execution of a program continuously, as it executes. This mechanism not only validates the execution of the application, but also validates the execution of library functions and the kernel. The hardware enhancements required to implement the technique are very modest, and the execution overhead is negligible in most cases. There is also some compiler support provided for pre-execution analysis of the validated software components. The computing system is responsive to codes, e.g., program instructions or other signals, to deactivate some or all of the security features, and thereby allow exceptions to the normal prohibitions and control mechanisms. These codes are provided by the operating system or some other reliable entity, in order to provide authentication of the exceptions. These references taken either alone or in combination with the prior art of record fail to disclose limitations, including: 5. The method of claim 1, further comprising: accessing an expiration date for the semiconductor device characterization description; and transmitting the expiration date to the MI. 13. The method of claim 7, further comprising: receiving an expiration date for the valid semiconductor device characterization description; and determining whether the valid semiconductor device characterization description has expired based at least in part on the expiration date for the valid semiconductor device characterization description. 14. The method of claim 7, further comprising: at least partly in response to the valid semiconductor device characterization description being not expired, transmitting an allow simulation signal to a simulator, the allow simulation signal configured to allow a semiconductor circuit to be simulated using the stored semiconductor device characterization description; and at least partly in response to the valid semiconductor device characterization description being expired, transmitting a disallow simulation signal to the simulator, the disallow simulation signal configured to prevent the semiconductor circuit from being simulated using the stored semiconductor device characterization description. 19. The circuit simulation management system of claim 15, wherein the MI is further configured to: receive an expiration date for the valid semiconductor device characterization description; and determine whether the valid semiconductor device characterization description has expired based at least in part on the expiration date for the valid semiconductor device characterization description. in combination with the remaining elements and features of the claimed invention . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUEN-MEEI GAN whose telephone number is (469)295-9127. The examiner can normally be reached Monday-Friday 9:00 am to 4:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen can be reached at 571-272-3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHUEN-MEEI GAN/Primary Examiner, Art Unit 2189 Application/Control Number: 18/171,384 Page 2 Art Unit: 2189 Application/Control Number: 18/171,384 Page 3 Art Unit: 2189 Application/Control Number: 18/171,384 Page 4 Art Unit: 2189 Application/Control Number: 18/171,384 Page 5 Art Unit: 2189 Application/Control Number: 18/171,384 Page 6 Art Unit: 2189 Application/Control Number: 18/171,384 Page 7 Art Unit: 2189 Application/Control Number: 18/171,384 Page 8 Art Unit: 2189 Application/Control Number: 18/171,384 Page 9 Art Unit: 2189 Application/Control Number: 18/171,384 Page 10 Art Unit: 2189 Application/Control Number: 18/171,384 Page 11 Art Unit: 2189 Application/Control Number: 18/171,384 Page 12 Art Unit: 2189 Application/Control Number: 18/171,384 Page 13 Art Unit: 2189 Application/Control Number: 18/171,384 Page 14 Art Unit: 2189 Application/Control Number: 18/171,384 Page 15 Art Unit: 2189 Application/Control Number: 18/171,384 Page 16 Art Unit: 2189 Application/Control Number: 18/171,384 Page 17 Art Unit: 2189 Application/Control Number: 18/171,384 Page 18 Art Unit: 2189 Application/Control Number: 18/171,384 Page 19 Art Unit: 2189 Application/Control Number: 18/171,384 Page 20 Art Unit: 2189 Application/Control Number: 18/171,384 Page 21 Art Unit: 2189 Application/Control Number: 18/171,384 Page 22 Art Unit: 2189 Application/Control Number: 18/171,384 Page 23 Art Unit: 2189 Application/Control Number: 18/171,384 Page 24 Art Unit: 2189 Application/Control Number: 18/171,384 Page 25 Art Unit: 2189 Application/Control Number: 18/171,384 Page 26 Art Unit: 2189
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