Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants amendments filed on 06/22/2026 overcome the previous prior art rejection. Applicant persuasively argues that the prior art lacks the amended subject matter, but upon further search and consideration a new reference to Clark et al. has been found to read on the amended subject matter in the independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 9, 11-15, and 18-21 under 35 U.S.C. 103 as being unpatentable over Qian et al (US 20220165670 A1) in view of Clark et al (US 20190295891).
Regarding claims 1, 9 and 18
Qian et al teaches
[claim 1] A semiconductor structure comprising: a metal layer having a first pattern (figure 5, paragraphs 0033-0035, element 514 on the bottom of the device [element 500] is the first metal layer with a metal pattern),
a metal bridge located within the first pattern (figure 5, paragraphs 0033-0035, where element 514 is the metal bridge and exists in the first pattern);
at least one via disposed on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via (figure 5, paragraphs 0033-0035, where element 512 has a gap for a through via that is disposed into the gap and the metal bridge extends to a top surface of the via);
[claim 9] A semiconductor structure comprising: a metal layer having a first pattern (figure 5, paragraphs 0033-0035, where the layer below element 502 is the first metal layer with a first pattern),
a metal bridge directly contacting the metal layer (figure 5, paragraphs 0033-0035, where element 514 contacts the layer below element 502).
and a via disposed on a portion of the metal layer such that the metal bridge extends along a sidewall of the via to a topmost surface of the via (figure 5, paragraphs 0033-0035, where a via is disposed inside the gap of element 512, and the metal bridge [element 514] extends up sidewalls of the via to a top of the through via).
[claim 18] A method for constructing a semiconductor structure, the method comprising: forming a metal layer having a first pattern (figure 4, paragraph 0031, block 490 is the metal layer formed with a first patter on the bottom of element 502 of figure 5),
constructing a metal bridge located within the first pattern (figure 4, paragraph 0031, block 480 is the metal bridge formed on a metal layer surrounding the through via [element 512 of figure 5]),
forming at least one via on a portion of the metal layer such that the metal bridge extends to a top surface of the at least one via (figure 4, paragraph 0031, block 470 is the formation of the via that connects to a top metal layer [element 510 of figure 5], and block 490 forms the metal interconnect structure which connects the metal layer below element 502 of figure 5 to element 510 of figure 5);
However, Qian et al does not specifically disclose
[claim 1] a metal cap disposed directly on the top surface of the at least one via
[claim 9] a metal cap disposed directly on the topmost surface of the via
[claim 18] disposing a metal cap directly on the top surface of the at least one via
However, Clark et al does teach
[claim 1] a metal cap disposed directly on the top surface of the at least one via (figure 1B, paragraph 0040, where element 112 is the metal cap disposed directly on the top surface of the at least one via, which is read onto from Qian et al’s via).
[claim 9] a metal cap disposed directly on the topmost surface of the via (figure 1B, paragraph 0040, where element 112 is the metal cap disposed directly on the top surface of the at least one via, which is read onto from Qian et al’s via).
[claim 18] disposing a metal cap directly on the top surface of the at least one via (figure 1B, paragraph 0040, where element 112 is the metal cap disposed directly on the top surface of the at least one via, which is read onto from Qian et al’s via).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of Qian et al to incorporate the teaches of Clark et al to put a metal cap on top of a metal via in order to protect any degradation on the via from effects such as oxidation among other processes that degrade metal vias.
Regarding claims 2-6, 11-15, 19-21
Qian et al further teaches
[claim 2] The semiconductor structure of claim 1, wherein the metal bridge is at a same level as the metal layer (figure 5, paragraphs 0033-0035, where element 514 extends to the bottom of the device [element 500] and thus is in the metal layer).
[claim 3] The semiconductor structure of claim 1, wherein the metal bridge is at a same level as the at least one via (figure 5, paragraphs 0033-0035, where element 514 [the metal bridge] is at the same level as the through via [in gap element 512]).
[claim 4] The semiconductor structure of claim 1, wherein the metal bridge connects adjoining metal layers (figure 5, paragraphs 0033-0035, where the metal bridge [element 514] connects the metal at the bottom of the device [element 500] to the the top element 510).
[claim 5] The semiconductor structure of claim 1, wherein the metal bridge includes a plurality of metals bridges (figure 5, paragraphs 0033-0035, where element 514 comprises two different sides of element 512 which can be seen as a plurality of metal bridges that connects the bottom layer to the top metal layer [element 510]).
[claim 6] The semiconductor structure of claim 5, wherein the plurality of metal bridges are generally rectangular-shaped (figure 5, paragraphs 0033-0035, where element 514 is rectangular in shape [even though it may be tilted at an angle, the shape of the layer is rectangular]).
[claim 11] The semiconductor structure of claim 9, wherein the metal bridge is at a same level as the metal layer (figure 5, paragraphs 0033-0035, where element 514 [metal bridge] is on the same level as the metal layer [layer below element 502]).
[claim 12] The semiconductor structure of claim 9, wherein the metal bridge is at a same level as the via (figure 5, paragraphs 0033-0035, where element 514 is at the same level as the through via [element 512] as it extends up the sidewalls of the via).
[claim 13] The semiconductor structure of claim 9, wherein the metal bridge connects adjoining metal layers (figure 5, paragraphs 0033-0035, where element 514 connects the layer below element 502 and the element 510 [metal layer on top of via gap 512]).
[claim 14] The semiconductor structure of claim 9, wherein the metal bridge includes a plurality of metals bridges (figure 5, paragraphs 0033-0035, where element 514 is comprised of two sides of element 512 which make up the plurality of metal bridges which connect together on the top of element 512).
[claim 15] The semiconductor structure of claim 14, wherein the plurality of metal bridges are generally rectangular-shaped (figure 5, paragraphs 0033-0035, where element 514 [both sides of element 512] are rectangular shaped even though it is tilted a little bit, the shape is still rectangular).
[claim 19] The method of claim 18, wherein the metal bridge is at a same level as the metal layer (figure 5, paragraphs 0033-0035, where the metal layer is below element 502 and the metal bridge [element 514] extends to the metal layer).
[claim 20] The method of claim 18, wherein the metal bridge includes a plurality of metal bridges electrically connecting a plurality of adjoining metal layers (figure 5, paragraphs 0033-0035, where element 514 extends from below element 502 [metal layer] to above element 514 through element 510 [adjoining metal layer]).
[claim 21] The semiconductor structure of claim 1, wherein the metal bridge is at a same level as the at least one via (figure 5, paragraphs 0033-0035, where element 514 [the metal bridge] is at the same level as the through via [in gap element 512]).
Claim(s) 7-8 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Qian et al (US 20220165670 A1), and Clark et al (US 20190295891) in further view of Bonilla et al (US 9852980 B2).
Qian et al as modified teaches all of the limitations of the parent claim, claims 1 and 9, but does not specifically disclose
[claim 7] The semiconductor structure of claim 1, wherein a dielectric encompasses the metal bridge.
[claim 8] The semiconductor structure of claim 1, wherein the metal bridge includes ruthenium (Ru).
[claim 16] The semiconductor structure of claim 9, wherein a dielectric encompasses the metal bridge.
[claim 17] The semiconductor structure of claim 9, wherein the metal bridge includes ruthenium (Ru).
However, Bonilla et al does teach
[claim 7] The semiconductor structure of claim 1, wherein a dielectric encompasses the metal bridge (figure 2, col 5 lines 29-54, where element 206 is the dielectric layer and encompasses the metal bridge, element 203. Where element 203 supplants element 514 of Qian et al and element 202 supplants element 512 of Qian et al).
[claim 8] The semiconductor structure of claim 1, wherein the metal bridge includes ruthenium (Ru) (figure 2, col 7 lines 47-52, where element 203 [metal bridge] can be made of Ruthenium).
[claim 16] The semiconductor structure of claim 9, wherein a dielectric encompasses the metal bridge (figure 2, col 5 lines 29-54, where element 206 is the dielectric layer and encompasses the metal bridge, element 203. Where element 203 supplants element 514 of Qian et al and element 202 supplants element 512 of Qian et al).
[claim 17] The semiconductor structure of claim 9, wherein the metal bridge includes ruthenium (Ru) (figure 2, col 7 lines 47-52, where element 203 [metal bridge] can be made of Ruthenium).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Qian et al to incorporate the teachings of Bonilla et al in order to maximize maximize electrical durability by using Ruthenium as well as placing a dielectric layer around the metal connectors so no extra parasitic effects can affect the conductive material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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