DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (encompassing claims 1-3 and 5-20) in the reply filed on 12/12/25 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 2/21/23 and 7/2/25. The submissions are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Specification
The title of the invention is not descriptive as it is generic. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagihara et al. (U.S. 2022/0392887 A1; “Yanagihara”) in view of Yoshioka et al. (U.S. 2014/0284610 A1; “Yoshioka”).
Regarding claim 1, Yanagihara discloses a semiconductor device, comprising:
A first terminal (121, Fig. 1A);
A second terminal (123, Fig. 1A);
A third terminal (122, Fig. 1A);
A first transistor (111, Fig. 1A) of a normally-off type, the first transistor including a first source (11, Fig. 1A), a first drain (14, Fig. 1A), and a first gate (12, Fig. 1A), the first source (11, Fig. 1A) being electrically connected to the first terminal (121, Fig. 1A), the first drain (14, Fig. 1A) being electrically connected to the second terminal (123, Fig. 1A), and the first gate (12, Fig. 1A) being electrically connected to the third terminal (122, Fig. 1A);
A second transistor (112, Fig. 1A), the second transistor including a second source (18, Fig. 1A), a second drain (15, Fig. 1A), and a second gate (16, Fig. 1A), the second drain (15, Fig. 1A) being electrically connected to the second terminal (123, Fig. 1A), and the second gate (16, Fig. 1A) being electrically connected to the first terminal (121, Fig. 1A).
Yet, Yanagihara does not disclose the following
The second transistor is of a normally on-type;
A diode, the diode including an anode and a cathode, the anode being electrically connected to the first terminal, and the cathode being electrically connected to the second source.
However, Yoshioka discloses a semiconductor device comprising a diode (101, Fig. 1) including an anode (20, Fig. 1) and a cathode (22, Fig. 1), the anode (20, Fig. 1-2) being electrically connected to a first terminal (44, Fig. 2), and the cathode (22, Fig. 1) being electrically connected to a second source (32, Fig. 1) ([0015]), wherein the [second] transistor is of a normally on-type ([0020]). This has the advantage of improving device performance by increasing withstand or breakdown voltage and providing higher-speed operation with lower on-resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yanagihara with a diode including an anode being electrically connected to the first terminal, and a cathode being electrically connected to the second source wherein the second transistor is of a normally on-type, as taught by Yoshioka, so as to improve device performance.
Regarding claim 18, Yanagihara and Yoshioka disclose the diode includes a diode semiconductor member, and the diode semiconductor member includes silicon (Yoshioka: [0017]).
Regarding claim 20, Yanagihara and Yoshioka disclose a plurality of the first transistors (711, Fig. 7A) and a plurality of the second transistors (712, Fig. 7A) are provided, one of the plurality of second transistors (712, Fig. 7A) is located between one of the plurality of first transistors (711, Fig. 7A)and another one of the plurality of first transistors (711, Fig. 7A), and the one of the plurality of first transistors (711, Fig. 7A) is located between the one of the plurality of second transistors (712, Fig. 7A) and another one of the plurality of second transistors (712, Fig. 7A) ([0116]).
Claim(s) 2 and 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagihara et al. (U.S. 2022/0392887 A1; “Yanagihara”) as modified by Yoshioka et al. (U.S. 2014/0284610 A1; “Yoshioka”) as applied to claim 1 above, and further in view of Kadoguchi et al. (U.S. 2019/0027381 A1; “Kadoguchi”).
Regarding claim 2, Yanagihara and Yoshioka disclose a device substrate (Yanagihara: 1, Fig. 1A; Yoshioka: 10, Fig. 1) including a first substrate (top) face, positions of the first transistor (Yanagihara: 111, Fig. 1A), the second transistor (Yanagihara: 112, Fig. 1A; Yoshioka: 201, Fig. 1), and the diode (Yoshioka: 101, Fig. 1) with respect to the first substrate face being fixed, a first direction from the first transistor (Yanagihara: 111, Fig. 1A) to the second transistor (Yanagihara: 112, Fig. 1A) being along the first substrate face (Yanagihara: 1, Fig. 1A). Yet, Yanagihara and Yoshioka do not disclose a direction from the diode to at least a part of the second transistor being along the first substrate face and crossing the first direction. However, Kadoguchi discloses a direction from a diode (6, Fig. 4) to at least a part of a second transistor (5, Fig. 4) being along a first substrate face (22, Fig. 4) and crossing a first direction (direction between 3 and 5, Fig. 4) ([0035]). This has the advantage of reducing the footprint of components in the semiconductor device in the first direction. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yanagihara and Yoshioka with a direction from the diode to at least a part of the second transistor being along the first substrate face and crossing the first direction, as taught by Kadoguchi, so as to reduce the size of the semiconductor device in the first direction.
Regarding claim 5, Yanagihara, Yoshioka, and Kadoguchi disclose:
A second (vertical) direction from the first substrate face (Yanagihara: top surface of 2, Fig. 1A) to the first transistor (Yanagihara: 111, Fig. 1A) crosses the first direction (Yanagihara: direction between 111 and 112, Fig. 1A),
A direction from the first substrate face (Yanagihara: top surface of 2, Fig. 1A) to the second transistor (Yanagihara: 112, Fig. 1A) is along the second (vertical) direction,
A direction from the first source (Yanagihara: 11, Fig. 1A) to the first drain (Yanagihara:14, Fig. 1A) is along the first direction,
A position of the first gate (Yanagihara: 12, Fig. 1A) in the first direction is between a position of the first source (Yanagihara: 11, Fig. 1A) in the first direction and a position of the first drain (Yanagihara: 14, Fig. 1A) in the first direction,
A direction from the second drain (Yanagihara: 15, Fig. 1A) to the second source (Yanagihara: 18, Fig. 1A) is along the first direction,
A position of the second gate (Yanagihara: 16, Fig. 1A) in the first direction is between a position of the second drain (Yanagihara: 15, Fig. 1A) in the first direction and a position of the second source (Yanagihara: 18, Fig. 1A) in the first direction,
The first source (Yanagihara: 11, Fig. 1A-1B), the first drain (Yanagihara: 14, Fig. 1A-1B), the first gate (Yanagihara: 12, Fig. 1A-1B), the second source (Yanagihara: 18, Fig. 1A-1B), the second drain (Yanagihara: 15, Fig. 1A-1B) and the second gate (Yanagihara: 16, Fig. 1A-1B) are arranged in a third (width) direction (Fig. 1B), and the third (width) direction crosses a plane including the first (length) direction and the second (vertical) direction (Yanagihara: Fig. 1A-1B).
Regarding claim 6, Yanagihara, Yoshioka, and Kadoguchi disclose a first distance between the first gate (Yanagihara: 12, Fig. 1A) and the first drain (Yanagihara:14, Fig. 1A) along the first direction but do not disclose it is not less than 0.8 times and not more than 1.2 times a second distance between the second gate and the second drain along the first direction. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a first distance to be not less than 0.8 times and not more than 1.2 times a second distance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 7, Yanagihara, Yoshioka, and Kadoguchi disclose a first length along the third direction of a part of the first gate (Yanagihara: 12, Fig. 1A) facing the first drain (Yanagihara: 14, Fig. 1A) but do not disclose it is not less than 0.8 times and not more than to 1.2 times a second length along the third direction of a part of the second gate facing the second drain. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to select a first length to be not less than 0.8 times and not more than 1.2 times a second length, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, Yanagihara, Yoshioka, and Kadoguchi disclose the first transistor includes a first semiconductor region (Yanagihara: 4, Fig. 1A) including GaN and a second semiconductor region (Yanagihara: 3, Fig. 1A) including AlGaN (Yanagihara: [0044]).
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yanagihara et al. (U.S. 2022/0392887 A1; “Yanagihara”) in view of Yamaguchi et al. (U.S. 2020/0388610 A1; “Yamaguchi”).
Regarding claim 1, Yanagihara discloses a semiconductor device, comprising:
A first terminal (121, Fig. 1A);
A second terminal (123, Fig. 1A);
A third terminal (122, Fig. 1A);
A first transistor (111, Fig. 1A) of a normally-off type, the first transistor including a first source (11, Fig. 1A), a first drain (14, Fig. 1A), and a first gate (12, Fig. 1A), the first source (11, Fig. 1A) being electrically connected to the first terminal (121, Fig. 1A), the first drain (14, Fig. 1A) being electrically connected to the second terminal (123, Fig. 1A), and the first gate (12, Fig. 1A) being electrically connected to the third terminal (122, Fig. 1A);
A second transistor (112, Fig. 1A), the second transistor including a second source (18, Fig. 1A), a second drain (15, Fig. 1A), and a second gate (16, Fig. 1A), the second drain (15, Fig. 1A) being electrically connected to the second terminal (123, Fig. 1A), and the second gate (16, Fig. 1A) being electrically connected to the first terminal (121, Fig. 1A).
Yet, Yanagihara does not disclose the following
The second transistor is of a normally on-type;
A diode, the diode including an anode and a cathode, the anode being electrically connected to the first terminal, and the cathode being electrically connected to the second source.
However, Yamaguchi discloses a semiconductor device comprising a diode (2, Fig. 3) including an anode (21A, Fig. 3) and a cathode (21C, Fig. 3), the anode (21A, Fig. 3) being electrically connected to a first terminal (), and the cathode (21C, Fig. 3) being electrically connected to a second source ([0038]-[0041]), wherein the [second] transistor (1, Fig. 3) is of a normally on-type ([0038]). This has the advantage of improving device performance by increasing withstand or breakdown voltage and providing higher-speed operation with lower on-resistance. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Yanagihara with a diode including an anode being electrically connected to the first terminal, and a cathode being electrically connected to the second source wherein the second transistor is of a normally on-type, as taught by Yamaguchi, so as to improve device performance.
Regarding claim 3, Yanagihara and Yamaguchi disclose a device substrate (Yamaguchi: 30, Fig. 3) including a first substrate [top] face, a position of the diode (Yamaguchi: 2, Fig. 3) with respect to the first substrate face being fixed, and the cathode (Yamaguchi: 21C, Fig. 3) being located between the first substrate face (Yamaguchi: 30, Fig. 3) and the anode (Yamaguchi: 21A, Fig. 3).
Allowable Subject Matter
Claims 9-17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/REEMA PATEL/Primary Examiner, Art Unit 2812 3/17/26
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