DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/12/2026 has been entered.
Response to Arguments
Applicant's arguments filed 2/26/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zeng et al. (US PGPub 2009/0206924; hereinafter “Zeng”).
Re claim 1: Zeng teaches (e.g. figs. 4A, 4B and labeled fig. 4a below) a semiconductor device comprising: a plurality of trench portions (104, 112) provided in a semiconductor substrate (substrate 118 and epitaxial layer grown thereon; e.g. paragraph 47,64); a mesa portion (mesa region between 104, 112; hereinafter “MP”) provided between the plurality of trench portions (104, 112) in the semiconductor substrate (118); a front surface metal layer (electrode labeled “E” below) provided above the semiconductor substrate (118); and a base region (p-body 116; e.g. paragraph 51) of a second conductivity type (p-type) provided in the semiconductor substrate (118), wherein the plurality of trench portions (104, 112) include: a gate trench portion (102, 104) having a gate conductive portion (102) and a gate dielectric film (104); and a dummy trench portion (110, dielectric film under 110) having a dummy conductive portion (110) and a dummy dielectric film (dielectric film under 110), and the front surface metal layer (E) includes: an upper region (region of E that contacts top of mesa MP; hereinafter “UR”) that is in contact with an upper surface of the mesa portion (MP) in direct contact with the dummy trench portion (110, dielectric film under 110); and an embedded region (lower portion of E embedded in the substrate; hereinafter “ER” and labeled shaded region below) that is embedded in the semiconductor substrate (118) and that is in contact with a side wall (sidewall of mesa MP; hereinafter “SW”) of the mesa portion (MP) and the dummy conductive portion (110); and a lowermost surface (lower surface of ER; hereinafter “LE”) of the embedded region (ER) is shallower than a lowermost surface (lower surface of 116) of the base region (116).
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Re claim 2: Zeng teaches the semiconductor device according to claim 1, wherein the embedded region (ER) is in contact with the side wall (SW) of the mesa portion (MP) and the dummy conductive portion (110) above an upper end of the dummy dielectric film (dielectric film under 110).
Re claim 3: Zeng teaches the semiconductor device according to claim 1, further comprising an interlayer dielectric film (film labeled “ID”) provided on a front surface (upper surface of substrate which includes 118 and the epitaxial semiconductor layers formed above 118) of the semiconductor substrate (118), wherein the interlayer dielectric film (ID) is provided with a contact hole (opening for E within ID; hereinafter “CH”) above the dummy trench portion (110, dielectric film under 110).
Re claim 5: Zeng teaches the semiconductor device according to claim 4, wherein a distance from an upper end (upper end of ER) to the lowermost surface (lower end of ER in the middle) of the embedded region (ER) is 50% or less of a distance from a front surface (surface labeled “FS”) of the semiconductor substrate (118) to the lowermost surface of the base region (116).
Re claim 6: Zeng teaches the semiconductor device according to claim 1, further comprising a contact region (regions labeled “PCR”) of the second conductivity type (p-type) extending from a front surface (surface labeled “FS”) of the semiconductor substrate (118) into the semiconductor substrate (118), wherein the lowermost surface (lowermost surface of ER) of the embedded region (ER) is shallower than a lowermost surface (lowermost surface of PCR) of the contact region (PCR).
Re claim 7: Zeng teaches the semiconductor device according to claim 5, further comprising a contact region (regions labeled “PCR”) of the second conductivity type (p-type) extending from the front surface (FS) of the semiconductor substrate (118) into the semiconductor substrate (118), wherein the lowermost surface (lowermost surface of ER) of the embedded region (ER) is shallower than a lowermost surface (lowermost surface of PCR) of the contact region (PCR).
Re claim 10: Zeng teaches the semiconductor device according to claim 1, wherein, in a trench array direction, one side wall (left SW of mesa MP as shown in fig. 4a) of side walls (SW) of the upper region (UR) is located on a first mesa portion (mesa labeled MP1) that is in direct contact with the dummy trench portion (110, dielectric film under 110), and an other side wall (right SW of mesa MP as shown in fig. 4a) is located on a second mesa portion (mesa labeled MP2) that is in direct contact with the dummy trench portion (110, dielectric film under 110) on a side opposite to the first mesa portion (MP1).
Re claim 11: Zeng teaches the semiconductor device according to claim 1, comprising a plurality of dummy trench portions (plural 110, dielectric film under 110) adjacently arrayed, wherein the upper region (UR) is provided extending across the plurality of dummy trench portions (110, dielectric film under 110) in a trench array direction.
Re claim 12: Zeng teaches the semiconductor device according to claim 1, comprising a transistor portion (portion where 102, 104 are provided) provided with the gate trench portion (102, 104) and the dummy trench portion (110, dielectric film under 110), and a diode portion (portion where 110, dielectric film under 110 is provided) provided with the dummy trench portion (110, dielectric film under 110).
Re claim 13: Zeng teaches the semiconductor device according to claim 12, wherein a plurality of dummy trench portions (110, dielectric film under 110) are adjacently arrayed in the diode portion (portion where 110, dielectric film under 110 is provided; e.g. paragraph 20), and the upper region (UR) is provided extending from a dummy trench portion (110, dielectric film under 110) of the plurality of dummy trench portions (110, dielectric film under 110) that is adjacent to the gate trench portion (102, 104) to a dummy trench portion (110, dielectric film under 110) on an opposite side, in a trench array direction (left-right direction of fig. 4a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zeng as applied to claim 1 above, and further in view of Siemieniec et al. (US PGPub 2016/0079238; hereinafter “Siemieniec”).
Re claim 18: Zeng teaches the semiconductor device according to claim 1, wherein each of the upper region (UR) and the embedded region (ER) has a plug (region labeled “P”)
Zeng is silent as to explicitly teaching the plug containing tungsten (tungsten; e.g. paragraph 73) and a barrier metal containing titanium (sub-layer of Ti; e.g. paragraph 73).
Siemieniec teaches a plug containing tungsten (tungsten; e.g. paragraph 73) and a barrier metal containing titanium (sub-layer of Ti; e.g. paragraph 73).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the tungsten and Ti barrier layer for the plug as taught by Siemieniec in the device of Zeng in order to have the predictable result of using a known electrode plug structure which would have improved reliability for the electrodes which uses layers which prevent metal particles from diffusion into the surrounding areas.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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