DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 22, 2023, August 3, 2023, April 24, 2025, November 25, 2025 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D NAND Memory Device With Cross-Stacking Structure.
Election/Restrictions
Applicant’s election of Group I (claims 1-11) in the reply filed on September 15, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Additionally Claims 12-20 are amended to fall under group I.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “second source line” and “third source line” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities: line 5 recites the limitations “opposites to” it is believed this meant to be “opposite to” and will be interpreted as such. Appropriate correction is required. Claim 14 is objected to because of the following informalities: line 3 recites the limitations “wherein the bit lines is” it is believed this meant to be “wherein the bit lines are” and will be interpreted as such. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: line 6 recites the limitations “opposites to” it is believed this meant to be “opposite to” and will be interpreted as such. Appropriate correction is required.
Claim 20 is objected to because of the following informalities: line 6 recites the limitations “opposites to” it is believed this meant to be “opposite to” and will be interpreted as such. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-6, 8-14, and 16-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 4, line 3 recites the limitation “a second source line connected with the second connecting structure” however, the drawings only show one source line 34 connected a connecting structure 50 and even though the plan views shown the other connecting structure connected, it is to the same source line 34. For purposes of examination this will be interpreted as “a second portion of the first source line.” Similarly all references to “the second source line” in claims 6, 11, and 16 will be interpreted as “the second portion of the first source line.” Regarding Claim 11, line 2 recites the limitation “a third source line connected with the first source line and the second source line” however, the drawings only show one source line 34 connected a connecting structure 50. For purposes of examination this will be interpreted as “a third portion of the first source line.” Regarding Claim 13, lines: 2-3 recite the limitation “wherein the channel structures are between the bit lines and the connecting structures” however, the drawings do not show where channels 28 are between bit lines 24 and connecting structures 32. For purposes of examination this will be interpreted as “wherein the channel structures are adjacent to the bit lines and the connecting structures”
Regarding Claim 17, line 12 recites the limitation “a second source line connected with the second connecting structure” however, the drawings only show one source line 34 connected a connecting structure 50 and even though the plan views shown the other connecting structure connected, it is to the same source line 34. For purposes of examination this will be interpreted as “a second portion of the first source line.” Similarly all references to “the second source line” in claim 19 will be interpreted as “the second portion of the first source line.”
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation "the connecting structure" in lines 8-10. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the first connecting structure”
Claim 20 recites the limitation "the first source line" in line 10. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the source line”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 13, 15, 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee (US 2018/0308860). Claim 1, Lee discloses (Figs. 4-8) a semiconductor device, comprising (Fig. 8): a substrate (150, interlayer insulating layer, under broadest reasonable interpretation (BRI) 150 is considered a substrate as it holds further elements, Para [0073]); a stack structure (120/ES, insulating layers/electrode structure, Para [0050]) comprising alternating gate layers (ES) and insulating layers (120(; channel structures (VP, vertical pillars, Para [0063]) extending through the stack structure (VP extends through 120/ES in d1) in a first direction (vertical direction, hereinafter “d1”) and coupled to a first side (VP is physically coupled to the bottom side of 150) of the substrate (150) in the first direction (d1) and connecting structures (132, common source plug, Para [0072]) coupled to a second side (132 is physically coupled to top side of 150) of the substrate opposites to the first side (top side of 150 is opposite to bottom side of 150), wherein a first connecting structure (left 132, hereinafter “c1”) and a second connecting structure (middle 132, hereinafter “c2”) are two adjacent connecting structures of the connecting structures (c1 and c2 are considered adjacent to each other as there are no intervening 132s between them), first channel structures (only VP3/VP1/Vp5/VP7 are shown in Fig. 8, hereinafter “channels”) of the channel structures (VP) are between the first connecting structure and the second connecting structure in a second direction (horizontal direction, hereinafter “d2”) perpendicular to the first direction (channels are between c1 and c2 in d2 which is perpendicular to d1). Claim 2, Lee discloses (Figs. 4-8) the semiconductor device of claim 1, wherein an extended wall-shape of the first connecting structure or the second connecting structure is a tapered cross section or a frustoconical shape (as shown in Fig. 8, c2 has a tapered shape as the width decreases from top to bottom). Claim 3, Lee discloses (Figs. 4-8) the semiconductor device of claim 1, wherein the first channel structures (channels) are formed in rows and columns (although only VP3/VP1/VP5/VP7 are shown in Fig. 8 forming a row, there are other channels such as VP4 as shown in Fig. 4 that form columns). Claim 13, Lee discloses (Figs. 4-8) the semiconductor device of claim 1, further comprising (Fig. 8): bit lines (BL1/BL2, bit lines, Para [0080]) coupled to the channel structures (BL1/BL2 are coupled to VP through LCP, Para [0062]), wherein the channel structures (VP) are adjacent to the bit lines (VP are vertically adjacent to BL1/BL2) and the connecting structures (VP are laterally adjacent to 132). Claim 15, Lee discloses (Figs. 4-8) the semiconductor device of claim 1, wherein the connecting structures (132) are in rows and columns (Fig. 5 shows that 132s are in parallel rows and overlapping columns). Claim 20, Lee discloses (Figs. 4-8) a semiconductor device, comprising (Fig. 8): a substrate (150, interlayer insulating layer, under broadest reasonable interpretation (BRI) 150 is considered a substrate as it holds further elements, Para [0073]); a stack structure (120/ES, insulating layers/electrode structure, Para [0050]) comprising alternating gate layers (ES) and insulating layers (120); a channel structure (VP, vertical pillars, Para [0063]) extending through the stack structure (VP extends through 120/ES in d1) in a first direction (vertical direction, hereinafter “d1”) and coupled to a first side (VP is physically coupled to the bottom side of 150) of the substrate (150) in the first direction (d1) a first connecting structure (132, common source plug, Para [0072]) coupled to a second side (132 is physically coupled to top side of 150) of the substrate opposite to the first side (top side of 150 is opposite to bottom side of 150); and a source line (CSR, common source region, Para [0072]) connected with the first connecting structure (CSR is electrically coupled to 132, Para [0072]), wherein the first connecting structure (132) is between the source line and the stack structure in the first direction (132 is between CSR and 120/ES in vertical direction d1), the first connecting structure (132) extends from the source line (CSR) into the substrate (132 extends from CSR into 150). Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mushiga (US Pat. No. 10,354,987). Claim 1, Mushiga discloses (Fig. 4) a semiconductor device, comprising: a substrate (10, semiconductor material layer, Col. 10, lines: 15-25); a stack structure (146/246/132/232, electrically conductive layers/insulating layers, Col. 9, lines: 1-5, hereinafter “stack”) comprising alternating gate layers (146/246) and insulating layers (132/232); channel structures (58, memory stack structures, Col. 9, lines: 50-55)) extending through the stack structure (58 extends through stack in d1) in a first direction (vertical direction, hereinafter “d1”) and coupled to a first side of the substrate in the first direction (58 is coupled to top side of 10 in d1) and connecting structures (588, through-memory-level via structures, Col. 10, lines: 40-50) coupled to a second side of the substrate (588 is coupled to bottom side of 10) opposite to the first side (bottom side of 10 is opposite to top side of 10), wherein a first connecting structure (middle 588, hereinafter “c1”) and a second connecting structure (right 599, hereinafter “c2”) are two adjacent connecting structures of the connecting structures (c1 and c2 are considered adjacent as there are no intervening 588 between them), first channel structures (58s between c1 and c2, hereinafter “chan1”) of the channel structures (58) are between the first connecting structure and the second connecting structure (chan1 are between c1 and c2 in d2 direction) in a second direction (horizontal direction, hereinafter “d2”) perpendicular to the first direction (d2 is perpendicular to d1). Claim 7, Mushiga discloses (Fig. 4) the semiconductor device of claim 1, wherein the substrate (10) comprises doped region (61, source regions, Col. 10, lines: 10-15), the channel structures (58 is connected to 61 as shown) and the connecting structures (588) are connected to the doped region (588 are connected to 10 which is connected to 61).
Allowable Subject Matter
Claims 4-6, 8-12, 14, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejections above and in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Lee (US 2018/0308860), Mushiga (US Pat. No. 10,354,987), Manorotkul (US 2016/0056171), Sharangpani (US Pat. No. 11,201,139), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 4 (from which claims 5-6, 8-12, and 16 depend), a second portion of the first source line connected with the second connecting structure… the second connecting structure is between the second portion of the first source line and the stack structure in the first direction.
Regarding Claim 14, wherein the bit lines are between the channel structures and the periphery circuit.
Regarding Claim 17 (from which claims 18-19 depend), a second portion of the first source line connected with the second connecting structure, wherein the second connecting structure is between the first source line and the stack structure in the first direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Manorotkul (US 2016/0056171) discloses (Fig. 2C) common source structures CS surrounding a plurality of channels 180, however CS does not extend to a bottom side of 124 opposite to the top side of 124.
Sharangpani (US Pat. No. 11,201,139) discloses (Fig. 11C) connecting structures 488 surrounding a plurality of channels 58 with coned sections 388, but Sharangpani does not qualify as prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812