DETAILED ACTION
Election/Restrictions
Claims 5, 10-17 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to non-elected inventions. Election was made without traverse in the reply filed on 6/9/2026.
Claims 1-4, 6-9 and 18-19 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regards to claim 6, limitation stating “…further comprising a power controller, after the reduction of the frequency of the at least one of the second subset of the plurality of cores, to reduce a frequency of at least one of the second subset of the plurality of cores” lacks clarity because it is inconsistent with the specification. The limitations lack clarity in light of the specification because paragraphs [0041 and 0044] appear to be indicate that a power controller reduces a frequency of assured cores (at least the first subset of the plurality of cores) after reducing a frequency of opportunistic cores (at least the second subset of the plurality cores). However, the claim appears to be indicating reducing a frequency of the at least second subset of the plurality of cores twice. Therefore, it is unclear if the claim limitation is indicating a reduction in frequency of the at least second subset of cores occurs twice or if the claim is intended to reflect a reduction of frequency of both sets of cores as described in Fig. 4 and paragraphs [0041-0044]. For purposes of examination the examiner will interpret the limitation as the former.
In regards to claim 7, line 2 the limitation stating “the first threshold” lacks clarity because the limitation lacks proper antecedent basis. The examiner suggests amending the limitation to stating “a first threshold”.
In regards to claim 8, line 2 the limitation stating “the first threshold” lacks clarity because the limitation lacks proper antecedent basis. The examiner suggests amending the limitation to stating “a first threshold”.
In regards to claim 18, limitations stating “…a guaranteed workload within constraints of the processor…specified to execute a workload having a complexity less than the guaranteed workload…” lacks clarity. The limitation lacks clarity because it is unclear what constitutes “a guaranteed workload” and what “a workload of less complexity” means (e.g. the limitation is ambiguous)? For example, is a guaranteed workload a workload that operates at a first power level and any workload that operates at a power level lower than the first power level is of less complexity? Or is a workload of less complexity one that executes fewer instructions than a guaranteed workload that executes a threshold number of instructions? Thus, the metes and bounds of the claim cannot be reasonably determined by a person of ordinary skill in the art.
Claims 7-8 and 19 are dependent upon one or more claims above and therefore are similarly rejected on the same basis as one or more claims above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta, PGPUB No. 2021/0064426 and further in view of Al-Rawi, PGPUB No. 2018/0373287.
In regards to claim 1, Gupta discloses A processor comprising: a plurality of cores to execute instructions ([0128 and 0147]: wherein a heterogeneous multicore processor includes a plurality of cores to execute instructions ([0081-0088]]: wherein further details of cores are disclosed for clarity)) identify, for each of the plurality of cores, the core as an assured core or an opportunistic core ([0128-0132]: wherein each of the cores can be a low power core (assured core) or an high power/large core (opportunistic core). Wherein a low power core operates under a “assured” power/thermal limit and thus is an assured core as it is assured to operate under power/thermal constraints of processor. While, a high-power/large core is an opportunistic core as it takes advantage of opportunities when power/thermal budget is available to perform at higher power levels without constraints) wherein: the processor is specified with a first subset of the plurality of cores comprising assured cores and a second subset of the plurality of cores comprising opportunistic cores ([0128-0132]: wherein the processor includes one or more low power cores (assured core) and one or more high power/large cores (opportunistic core)) and the processor is to execute, within a specified power budget and a specified thermal budget, a specified workload on the first subset of the plurality of cores at a first performance level. ([0128-0132, 0135 and 0137]: wherein the processor is to execute, within specified power and thermal limits, a workload on low power cores at a lower power consumption (e.g. performance) level)
Gupta does not disclose a non-volatile storage coupled to the plurality of cores to store identification information regarding the plurality of cores, the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. Gupta does disclose storing information such as operating points, frequencies and voltages for low power and high-power cores. However, Gupta does not store information identifying whether each core is a low power or high-power core.
Al-Rawi discloses a table coupled to the plurality of cores to store identification information regarding the plurality of cores ([0031-0034 and 0042]: wherein a table is coupled to cores to store information identifying if they are high/critical processor core with a higher maximum frequency or a low/non-critical core with a lower maximum frequency) the identification information to identify, for each of the plurality of cores, the core as an assured core or an opportunistic core. ([0031-0034 and 0042]: wherein the information indicates if the core is a high/critical processor core with a higher maximum frequency (opportunistic core) or a low/non-critical core with a lower maximum frequency (assured core) (see [0008-0009]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Gupta, including high power and low power cores to include a table which identifies for each core which type of core it is as to group and prioritize the cores as taught in Al-Rawi. It would have been obvious to one of ordinary skill in the art because it would improve system performance (Al-Rawi [0009 and 0042]). Furthermore, it would allow for quick and efficient identification of an either a low or high-power core, which would allow for efficient allocation of a core based on workload.
The combination of Gupta and Al-Rawi thus far does not explicitly disclose a non-volatile storage coupled to the plurality of cores to store identification information. Al-Rawi discloses a table coupled to the cores to store the identification information ([0031-0034 and 0042]), but not that the table is stored in a non-volatile storage.
However, both Gupta and Al-Rawi disclose a non-volatile storage (Gupta [0088] |Al-Rawi [0064]))
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the table to be stored in a non-volatile memory. It would have been obvious to one of ordinary skill in the art because it would have been the simple substitution of one known element (storing data in a non-volatile memory) another (storing data in a generic memory storage) to yield predictable results (storing a table including core identification information in a non-volatile memory) (MPEP 2143 Example B). Furthermore, it is advantageous to use non-volatile memory storage for benefits such as energy efficiency and persistent data retention (e.g. retaining data during power loss).
In regards to claim 2, the combination of Gupta and Al-Rawi discloses The processor of claim 1 (see rejection of claim 1 above) further comprising: at least one monitor circuit coupled to the plurality of cores to measure power information and temperature information (Gupta [0151-0153]: wherein sensors (and combination of other circuits used to monitor cores such as counters, buses, etc.) coupled to the cores to measure power and thermal (temperature) consumption information (see [0031-0032]: wherein both power and thermal consumption is disclosed)) and a hardware feedback circuit coupled to the at least one monitor circuit (Gupta [0151 and See Figs. 20-21)) the hardware feedback circuit to determine hardware feedback information comprising an energy efficiency capability and a performance capability of at least some of the plurality of cores (Gupta [0138-0139, 0149-0150 and See Figs. 19-20) based at least in part on the power information and the temperature information. (Gupta [0151-0164]: wherein the power and thermal (temperature) consumption information is used to generate hardware feedback information comprising performance values and energy efficiency values (see Figs. 20-21))
In regards to claim 3, the combination of Gupta and Al-Rawi discloses The processor of claim 2 (see rejection of claim 2 above) wherein the hardware feedback circuit is to allocate at least one hardware feedback data structure to store the hardware feedback information and the identification information (Gupta [0149-0150]: wherein HW feedback circuitry allocates a feedback data structure to store the hardware feedback information) the hardware feedback data structure accessible to an operating system. (Gupta [0150 and Fig. 20])
The combination of Gupta and Al-Rawi thus far does not disclose wherein the hardware feedback circuit is to allocate at least one hardware feedback data structure to store the identification information. However, Gupta discloses a hardware feedback circuit that allocates information to a hardware feedback data structure, wherein the data structure entries for each core and each entry includes a portion reserved for future capabilities ([0138-0139 and Figs. 19-20]). While, Al-Rawi discloses the core information to identify each core type ([0031-0034 and 0042]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to store the core identification information into the reserved (free portion) in each core entry of the hardware feedback data structure of Gupta. It would have been obvious to one of ordinary skill in the art because including core information that identifies whether a core is a low or high-power core is feedback information that takes in account power and thermal constraints, and storing said information in the feedback data structure would allow an OS to access said information to make scheduling decisions that improve overall system performance and efficiency (Gupta [0035]).
In regards to claim 4, the combination of Gupta and Al-Rawi discloses The processor of claim 3 (see rejection of claim 3 above) wherein the identification information comprises hint information for the operating system (Gupta [0155-0158]: wherein energy performance preference values (hint values) are disclosed) wherein the operating system is to schedule one or more threads to one or more of the second subset of the plurality of cores based at least in part on the hint information. (Gupta [0128 and 0155-0158])
In regards to claim 18, Gupta discloses A system (See Figs. 1 and 20) comprising: a processor ([0039 and 0147]) comprising: a first plurality of cores to execute instructions ([0040, 0046 and 0128] (also see Figs. 4-9 for disclosure of cores executing instructions)) a second plurality of cores to execute instructions, ([0040, 0046 and 0128] (also see Figs. 4-9 for disclosure of cores executing instructions)) a power controller to control delivery of an operating voltage and an operating frequency to the first plurality of cores and the second plurality of cores ([0040-0042 and 0147]: wherein PCU controls delivery of voltage and frequency to cores) and a control circuit coupled to the first plurality of cores and the second plurality of cores ([0043 and 0149]: wherein hardware feedback control circuitry is coupled to cores (See Figs. 1 and 20)) the control circuit to provide hardware feedback information regarding the first plurality of cores and the second plurality of cores, the control circuit to allocate a hardware feedback structure to store the hardware feedback information ([0043 and 0148-0150]: wherein hardware feedback circuitry provides and allocates a hardware feedback structure with hardware feedback information (See Figs. 19-20)) the at least one hardware feedback structure accessible by an operating system ([0150 and Fig. 20]: wherein hardware feedback structure is accessible by OS (element 2070)) and a system memory coupled to the processor, the system memory to store the hardware feedback structure. (See Fig. 20: wherein system memory (element 2060) is coupled to processor and stores hardware feedback structure)
Gupta does not disclose the first plurality of cores comprising assured cores specified to execute a guaranteed workload within constraints of the processor; a second plurality of cores to execute instructions, the second plurality of cores comprising opportunistic cores specified to execute a workload having a complexity less than the guaranteed workload, and allocate a structure to store core identification information to identify the assured cores and the opportunistic cores. Gupta discloses a first plurality of cores and second plurality of cores specified to execute different workloads, however Gupta does not explicitly disclose the first set of cores executing a guaranteed workload within constraints nor the second plurality of cores to executing a workload having a complexity less than the guaranteed workload.
Al-Rawi discloses the first plurality of cores comprising assured cores specified to execute a guaranteed workload within constraints of the processor ([0008-0009, 0026, 0032, 0042-0044]: wherein a first plurality of cores (cores in group 204p) execute a guaranteed critical workload within limits of processor (maximum frequency limit, thermal limit, reliability limit, etc.). Wherein the workload is guaranteed or assured to be a high computationally intensive task for a critical core and therefore is a guaranteed workload for an assured core) the second plurality of cores comprising opportunistic cores specified to execute a workload having a complexity less than the guaranteed workload ([0008-0009, 0026, 0032, 0042-0044]: wherein a second plurality of cores (cores in group 204q) execute a workload including non-critical and low computational tasks that are less complex than the guaranteed high computationally intensive workload. Wherein the cores take the opportunity to operate under a lower maximum frequency limit based on operating non-critical tasks and therefore are opportunistic cores) allocate a structure to store core identification information to identify the assured cores and the opportunistic cores. ([0031-0034 and 0042]: wherein a table is allocated with core identification information which indicates if the core is a high/critical processor core with a higher maximum frequency (assured core) or a low/non-critical core with a lower maximum frequency (opportunistic core) (see [0008-0009]))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the multi-core processor of Gupta to group cores based on critical and non-critical workloads an operate under different frequency limits as the multi-core processor of Al-Rawi. It would have been obvious to one of ordinary skill in the art because it would allow overall improved system performance with increased power reduction (Al-Rawi [0009 and 0042]).
It would have been further obvious to one of ordinary skill in the art to store the core identification information into the reserved (free portion) in each core entry of the hardware feedback data structure of Gupta. It would have been obvious to one of ordinary skill in the art because including core information that identifies whether a core is a low or high-power core is feedback information that takes in account power and thermal constraints, and storing said information in the feedback data structure would allow an OS to access said information to make scheduling decisions that improve overall system performance and efficiency (Gupta [0035]).
In regards to claim 19, the combination of Gupta and Al-Rawi discloses The system of claim 18 (see rejection of claim 18 above) wherein the first plurality of cores comprise heterogeneous core types. (Gupta [0100, 0128 and 0134])
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta, Al-Rawi and further in view of Varma, PGPUB No. 2014/0157021.
In regards to claim 6, the combination of Gupta and Al-Rawi discloses The processor of claim 1 (see rejection of claim 1 above) further comprising a power controller (Gupta [0042 and 0147]: wherein a power control unit is disclosed)
The combination of Gupta and Al-Rawi does not disclose a power controller, after the reduction of the frequency of the at least one of the second subset of the plurality of cores, to reduce a frequency of at least one of the second subset of the plurality of cores.
Varma discloses a power controller, after the reduction of the frequency of the at least one of the second subset of the plurality of cores, to reduce a frequency of at least one of the second subset of the plurality of cores. ([0021, 0025-0029 and 0034]: wherein a power control unit reduces a frequency limit of cores of a processor a first time and then again after a decrement hold time (see elements 270 back to 210-240) (See Figs. 1-2))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the power control unit of Gupta to reduce frequency of processor cores as the power control unit of Varma. It would have been obvious to one of ordinary skill in the art because it would reduce power consumption in a processor (Varma [0021 and 0034]).
In regards to claim 8, the combination of Gupta, Al-Rawi and Varma discloses The processor of claim 6 (see rejection of claim 6 above) wherein the power controller, when the power consumption of the processor exceeds the first threshold, is to duty cycle at least one of the second subset of the plurality of cores. (Varma [0017, 0021, 0028 and Figs. 2-3])
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta, Al-Rawi, Varma and further in view of Varma, PGPUB No. 2015/0058650 hereby referred to as Varma 650’.
In regards to claim 7, the combination of Gupta, Al-Rawi and Varma discloses The processor of claim 6 (see rejection of claim 6 above).
The combination of Gupta, Al-Rawi and Varma does not disclose wherein the power controller, when the power consumption of the processor exceeds the first threshold, is to communicate shed information to an operating system to indicate that the operating system is not to schedule threads to the second subset of the plurality of cores. Gupta does disclose a power controller determining power consumption is exceeding a threshold and reporting the change to an OS (see [0160-0164]), but does not disclose indicating to the OS not to schedule threads to cores based on the determination.
Varma 650’ discloses wherein the power controller, when the power consumption of the processor exceeds the first threshold, is to communicate shed information to an operating system to indicate that the operating system is not to schedule threads to the second subset of the plurality of cores ([0016, 0034 and 0041]: wherein PCU determines power consumption exceeds a threshold (element 320) it communicates one or more core offline requests to the OS which indicates the OS is to stop scheduling work to one or more cores)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the power control unit of Gupta to prevent scheduling of work to cores when a power consumption level has been exceeded as the power control unit of Varma. It would have been obvious to one of ordinary skill in the art because it would provide greater power saving in a processor (Varma [0025 and 0033-0034]).
9. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta, Al-Rawi, and further in view of Varma, PGPUB No. 2015/0058650 hereby referred to as Varma 650’.
In regards to claim 9, the combination of Gupta and Al-Rawi discloses The processor of claim 2 (see rejection of claim 2 above). the processor to identify the first subset of the plurality of cores and the second subset of the plurality of cores to an operating system (Gupta [0125-0132] (See Figs. 16 and 20-21))
The combination of Gupta and Al-Rawi does not disclose wherein the processor further comprises one or more unavailable cores, the processor to identify the first subset of the plurality of cores and the second subset of the plurality of cores to an operating system and to not identify the one or more unavailable cores to the operating system.
Varma 650’ discloses wherein the processor further comprises one or more unavailable cores ([0023, 0040, 0044 and 0053]: wherein offline cores are disclosed) the processor to identify cores to an operating system ([0023, 0040 and 0044]: wherein the active cores are identified to an OS) and to not identify the one or more unavailable cores to the operating system. ([0053 and 0094]: wherein the offline cores are not visible to OS)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Gupta to place cores in an unavailable state which an OS cannot identify as taught in the processor of Varma. It would have been obvious to one of ordinary skill in the art because it would provide greater power saving in a processor (Varma [0025 and 0033-0034]).
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Beckett, PGPUB No. 2022/0164196 for teaching a core mapping table which identifies for each core a core ID, core aggregate group the core belongs too, wherein each aggregate group has an associated C-state, minimum frequency, and code size based on workload
Weissmann, PGPUB No. 2021/0026708 for teaching storing efficiency/performance preference group data in a register, wherein each EPP group ID identifies a list of cores associated with a set of efficiency/performance preferences
Ahuja, PGPUB No. 2019/0041925 for teaching a non-volatile memory storage storing guaranteed operating frequencies, maximum temperatures and core count values
Dorsey, PGPUB No. 2018/0349191 for teaching storing dynamic voltage and frequency scaling states for two different types of cores (e.g. efficiency cores and performance cores)
Bhandaru, USPAT No. 9,436,245 for teaching a PCU which classifies cores into one of an inactive, turbo or guaranteed groups
Paul, PGPUB No. 2015/0355692 for teaching assigning power limits based on thermal budget to heterogenous processing units
Weissmann, PGPUB No. 2016/0147275 for teaching thermal design power values assigned to processor cores
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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