Status of Claims
Claims 1-20 are pending.
Claims 16-20 are withdrawn from consideration.
Response to Amendment
The amendment filed 12/23/2025 has been accepted and entered.
Response to Arguments
Applicant’s amendments to independent claims 1 and 9, see page 8-9 of Applicant’s remarks filed 12/23/2025, with respect to the 35 U.S.C. 102 rejections of claims 1-13 have been fully considered and are persuasive. Cheng (with respect to independent claim 1) does not teach all of the limitations of amended claims 1 and 9 (i.e. the intergate insulator having an interface between the upper portion and the lower portion) and thus and its respective dependent claims. In view of the amendments, a new reference has been applied (US 2022/0238652 A1 Gardner et al, see below).
Claims 1-13 now stand rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al in view of US 2022/0238652 A1 Gardner et al.
Claim 14 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al in view of US 2022/0238652 A1 Gardner et al and further in view of US 2022/0157936 A1 Khaderbad et al.
Claim 15 now stands rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al in view of US 2022/0238652 A1 Gardner et al and further in view of US 2022/0157936 A1 Khaderbad et al and further in view of US 2022/0037528 A1 Chuang et al.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al (herein “Cheng”) in view of US 2022/0238652 A1 Gardner et al (herein “Gardner”).
Regarding Claim 1, Cheng discloses:
An integrated circuit device (see generally Figs. 8A, 8B, and 8C showing formed IC stacked nanosheet device, Figs. 1A-8C show processing steps of forming the IC device) comprising:
a first upper channel region (#116, see annotated Fig. 8C below) on a substrate (#104);
a first lower channel region (#108, see annotated Fig. 8C below) between the substrate (#104) and the first upper channel region (#116);
a first intergate insulator (#112, see annotated Fig. 8C below) that is between the first lower channel region (#108) and the first upper channel region (#116) and comprises a lower portion (bottom half of #112) and an upper portion (top half of #112);
an upper gate electrode (#802, top half of #802), wherein the first upper channel region (#116) and the upper portion of the first intergate insulator (top half of #112) are in the upper gate electrode (#802); and
a lower gate electrode (#802, bottom half of #802) between the substrate (#104) and the upper gate electrode (#802), wherein the first lower channel region (#108) and the lower portion of the first intergate insulator (#112) are in the lower gate electrode (#802).
Note, the upper gate electrode and the lower gate electrode are assigned the same element number as they comprise the same gate material, see paragraphs [0073]-[0074]. As interpreted by the examiner, the bounds of the upper gate electrode and lower gate electrode are represented as the top half and the bottom half of the gate electrode #802, that intersects the midpoint of the integrate insulator #112 shown in annotated Fig. 8C below.
Cheng does not explicitly disclose:
wherein the upper portion and the lower portion of the first intergate insulator are in contact with each other with an interface therebetween.
However, in analogous art, Gardner teaches:
See Figs. 9A-9G, see also paragraphs [0057]-[0059].
wherein the upper portion (#3224) and the lower portion (#3112) of the first intergate insulator (combination of #3224 and #3112, see [0058]) are in contact with each other with an interface (interface between #2224 and #2112, see Fig. 9G and [0058]) therebetween.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Gardner to the device disclosed by Cheng and include a multilayer isolation structure like shown in Gardner Fig. 9G. Doing so would provide the device additional bonding capabilities as well as isolation between tiers to enable separate processing for NMOS and PMOS transistors before they are stacked.
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Cheng Fig. 8C – Annotated by Examiner
Regarding Claim 2, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
wherein the upper gate electrode (#802) comprises a lower surface (bottom surface) that faces the substrate (#104) and contacts the lower gate electrode (#802).
Regarding Claim 3, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
wherein the upper gate electrode (#802) contacts opposing side surfaces (left and right side surfaces as shown in Fig. 8C) of the upper portion of the first intergate insulator (#112).
Regarding Claim 4, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
wherein the lower gate electrode (#802) contacts opposing side surfaces (left and right side surfaces as shown in Fig. 8C) of the lower portion of the first intergate insulator (#112).
Regarding Claim 5, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
wherein an entirety of the first upper channel region (#116) overlaps the first lower channel region (#108).
Note, as interpreted by the examiner, “overlaps” is in reference to a top-down view. In this case, the outer boundaries (the outer surfaces) of the upper and lower channel regions vertically line up with each other as shown in Figs. 8B and 8C, therefore they overlap.
Regarding Claim 6, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
wherein a side surface (left or right side surface) of the first lower channel region (#108) and a side surface (left or right side surface) of the first upper channel region (#116) are in the same plane.
Note, as interpreted by the examiner, “overlaps” is in reference to a top-down view. In this case, the outer boundaries (the outer surfaces) of the upper and lower channel regions vertically line up with each other as shown in Figs. 8B and 8C, therefore they overlap. As a result, the side surfaces of the upper and lower channel regions are in the same plane, shown in Fig. 8C.
Regarding Claim 7, Cheng in view of Gardner discloses: The integrated circuit device of Claim 1,
Cheng further discloses:
a second upper channel region (#116, see annotated Fig. 8C above, herein #116-2) that is on the substrate (#104) and is spaced apart from the first upper channel region (#116) in a first direction (horizontally with respect to the page);
a second lower channel region (#108, see annotated Fig. 8C above, herein #108-2) that is between the substrate (#104) and the second upper channel region (#116-2) and is spaced apart from the first lower channel region (#108) in the first direction (horizontally with respect to the page); and
a second intergate insulator (#112, see annotated Fig. 8C above, herein #112-2) that is between the second lower channel region (#108-2) and the second upper channel region (#116-2) and comprises a lower portion (bottom half of #112) and an upper portion (top half of #112),
wherein the second upper channel region (#116-2) and the upper portion (top half of #112) of the second intergate insulator (#112-2) are in the upper gate electrode (#802), and
the second lower channel region (#108-2) and the lower portion (bottom half of #112) of the second intergate insulator (#112-2) are in the lower gate electrode (#802).
Note, the upper gate electrode and the lower gate electrode are assigned the same element number as they comprise the same gate material, see paragraphs [0073]-[0074]. As interpreted by the examiner, the bounds of the upper gate electrode and lower gate electrode are represented as the top half and the bottom half of the gate electrode #802, that intersects the midpoint of the integrate insulator #112 shown in annotated Fig. 8C above.
Regarding Claim 8, Cheng in view of Gardner discloses: The integrated circuit device of Claim 8,
Cheng further discloses:
wherein each of the first (#112) and second intergate insulators (#112-2) comprises a lower surface (bottom surface) facing the substrate (#104), and
the lower surfaces (bottom surfaces) of the first (#112) and second intergate insulators (#112-2) are equidistant (see Fig. 8C) from the substrate (#104).
Regarding Claim 9, Cheng discloses:
An integrated circuit device comprising:
an upper transistor (see annotated Fig. 8B below, herein “#UT”) on a substrate (#104), wherein the upper transistor (#UT) comprises an upper channel region (#116) and an upper source/drain region (#602) contacting a side surface (left and right surfaces) of the upper channel region (#116);
a lower transistor (see annotated Fig. 8B below, herein “#LT”) between the substrate (#104) and the upper transistor (#UT), wherein the lower transistor (#LT) comprises a lower channel region (#108) and a lower source/drain region (#402) contacting a side surface (left and right surfaces) of the lower channel region (#108); and
an intergate insulator (#112) between the upper channel region (#116) and the lower channel region (#108), wherein an entirety of the intergate insulator (#112) overlaps the lower channel region (#108).
Note, as interpreted by the examiner, “overlaps” is in reference to a top-down view. In this case, the outer boundaries (the outer surfaces) of the upper and lower channel regions vertically line up with the integrate insulator as shown in Figs. 8B and 8C, therefore they overlap.
Cheng does not explicitly disclose:
wherein the intergate insulator comprises an upper portion and a lower portion between the upper portion and the substrate, and
wherein an upper surface of the lower portion of the intergate insulator is in contact with a lower surface of the upper portion of the intergate insulator.
However, in analogous art, Gardner teaches:
See Figs. 9A-9G, see also paragraphs [0057]-[0059].
wherein the intergate insulator (combination of #3224 and #3112) comprises an upper portion (#3224) and a lower portion (#3112) between the upper portion (#3224) and the substrate (silicon 3102/dielectric 3104/silicon 3106 substrate, see Fig. 9A and [0058]), and
wherein an upper surface (top surface) of the lower portion (#3112) of the intergate insulator (combination of #3224 and #3112) is in contact with a lower surface (bottom surface) of the upper portion (#3224) of the intergate insulator (combination of #3224 and #3112).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Gardner to the device disclosed by Cheng and include a multilayer isolation structure like shown in Gardner Fig. 9G. Doing so would provide the device additional bonding capabilities as well as isolation between tiers to enable separate processing for NMOS and PMOS transistors before they are stacked.
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Cheng Fig. 8B – Annotated by Examiner
Regarding Claim 10, Cheng in view of Gardner discloses: The integrated circuit device of Claim 9,
Cheng further discloses:
wherein a side surface of the intergate insulator (#112) and the side surface (left and right surfaces) of the upper channel region (#116) are in the same plane.
Note, as interpreted by the examiner, “overlaps” is in reference to a top-down view. In this case, the outer boundaries (the outer surfaces) of the upper channel regions and the intergate insulator vertically line up with each other as shown in Figs. 8B and 8C, therefore they overlap. As a result, the side surfaces of the upper and lower channel regions are in the same plane, shown in Fig. 8C.
Regarding Claim 11, Cheng in view of Gardner discloses: The integrated circuit device of Claim 9,
Cheng further discloses:
wherein a side surface of the intergate insulator (#112) and the side surface (left and right surfaces) of the lower channel region (#116) are in the same plane.
Note, as interpreted by the examiner, “overlaps” is in reference to a top-down view. In this case, the outer boundaries (the outer surfaces) of the lower channel regions and the intergate insulator vertically line up with each other as shown in Figs. 8B and 8C, therefore they overlap. As a result, the side surfaces of the upper and lower channel regions are in the same plane, shown in Fig. 8C.
Regarding Claim 12, Cheng in view of Gardner discloses: The integrated circuit device of Claim 9,
Cheng further discloses:
further comprising a source/drain insulator (#502) between the upper source/drain region (#602) and the lower source/drain region (#402), wherein the source/drain insulator (#502, see paragraph [0064], “…the buffer layer 502 can include an oxide, such as, for example, silicon dioxide.”) comprises a material different from the intergate insulator (#112, see paragraph [0044]: “…The second REO layer 112 can be made from a similar material and can be formed in a similar manner as the first REO layer 102.” Therefore, see also paragraph [0035]: “The first REO layer 102 can be made of any suitable rare earth oxide material, such as, for example, yttrium oxide (Y.sub.2O.sub.3),… thulium oxide (Tm.sub.2O.sub.3).”).
Regarding Claim 13, Cheng in view of Gardner discloses: The integrated circuit device of Claim 12,
Cheng further discloses:
wherein the source/drain insulator (#502) contacts a side surface (see Fig. 8B) of the intergate insulator (#112).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al in view of US 2022/0238652 A1 Gardner et al and further in view of US 2022/0157936 A1 Khaderbad et al (herein “Khaderbad”).
Regarding Claim 14, Cheng in view of Gardner discloses:
The integrated circuit device of Claim 13
Cheng in view of Gardner does not explicitly disclose:
wherein the source/drain insulator comprises an outer layer that contacts the side surface of the intergate insulator and comprises nitrogen.
However, in analogous art, Khaderbad teaches:
See Fig. 1A.
wherein the source/drain insulator (#140) comprises an outer layer (#140a) that contacts the side surface (left and right surfaces) of the intergate insulator (#145) and comprises nitrogen (see paragraph [0017]: “…In some embodiments, first dielectric layer 140a includes silicon nitride (SiN)…”).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Khaderbad to the device disclosed by Cheng in view of Gardner and include a multilayer isolation dielectric layer instead of a monolayer isolation dielectric layer. Doing so would be a simple substitution of one known element for another that would produce a predictable result.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0118892 A1 Cheng et al in view of US 2022/0238652 A1 Gardner et al and further in view of US 2022/0157936 A1 Khaderbad et al and further in view of US 2022/0037528 A1 Chuang et al (herein “Chuang”).
Regarding Claim 15, Cheng in view of Gardner and further in view of Khaderbad discloses:
The integrated circuit device of Claim 14.
Cheng in view of Gardner and further in view of Khaderbad does not explicitly disclose:
wherein the source/drain insulator further comprises an inner layer that comprises a material different from the outer layer, and the outer layer of the source/drain insulator contacts opposing side surfaces and a lower surface of the inner layer.
However, in analogous art, Chuang teaches:
See deposition of pertinent layers in Fig. 9 and completed device in Fig. 31.
wherein the source/drain insulator (#230/232) further comprises an inner layer (#232) that comprises a material different from the outer layer (#230, see paragraph [0025]: “ …The first CESL 230 may include silicon nitride, silicon oxynitride, and/or other materials known…” and “…The first ILD layer 232 may include materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials...”), and
the outer layer (#230) of the source/drain insulator (#230/232) contacts opposing side surfaces (left and right surfaces) and a lower surface (bottom surface) of the inner layer (#232).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Chuang to the device disclosed by Cheng in view of Gardner and further in view of Khaderbad and include an outer layer that contacts the side surfaces and the bottom surface of the inner layer, instead of the vertically stacked layers disclosed by Khaderbad. Doing so would be a simple substitution of one known dielectric structure for another that would also have the benefit of improved etch selectivity for the pertinent dielectric layers.
Citation of Other Pertinent Prior Art
US 2023/0085628 A1 Xie et al
US 2022/0122892 A1 Smith et al
US 20220367658 A1 Yim et al
US 2021/0265348 A1 Xie et al
US 2020/0035569 A1 Frouglier et al
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812