Last updated: May 29, 2026

Application No. 18/174,007

NANORIBBON-BASED TRANSISTORS WITH ETCH STOP LAYER TO ASSIST SUBFIN REMOVAL

Non-Final OA

Filed

Feb 24, 2023

Examiner

GARCES, NELSON Y

Art Unit

2814

Tech Center

2800 — Semiconductors & Electrical Systems

Assignee

Intel Corporation

OA Round

1 (Non-Final)

Interview Optional

— +2.7% interview lift. Interview lift (+2.7%) is below the 15.0% threshold. A written response is recommended.

Based on 582 resolved cases, 2023–2026

Examiner Intelligence

GARCES, NELSON Y View full profile →

Grants 80% — above average

Career Allowance Rate

467 granted / 582 resolved

+12.2% vs TC avg

Minimal +3% lift

Without

With

+2.7%

Interview Lift

resolved cases with interview

Typical timeline

2y 5m

Avg Prosecution

39 currently pending

Career history

618

Total Applications

across all art units

Statute-Specific Performance

§101

0.1%

-39.9% vs TC avg

§103

76.5%

+36.5% vs TC avg

§102

15.7%

-24.3% vs TC avg

§112

5.7%

-34.3% vs TC avg

Black line = Tech Center average estimate • Based on career data from 582 resolved cases

Prosecution Timeline

Feb 24, 2023

Application Filed

Aug 09, 2023

Response after Non-Final Action

Dec 22, 2023

Response after Non-Final Action

May 26, 2026

Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

18/095,041

Patent 12641772

SEMICONDUCTOR DEVICE INCLUDING ACTIVE REGION AND SEMICONDUCTOR LAYER ON SIDE SURFACE OF ACTIVE REGION

3y 4m to grant Granted May 26, 2026

18/360,622

Patent 12641892

METHOD FOR FORMING PHOTOELECTRIC CONVERSION ELEMENT OF IMAGE SENSING DEVICE

2y 10m to grant Granted May 26, 2026

18/676,161

Patent 12641896

LIGHT DETECTING DEVICE WITH OXIDE SEMICONDUCTOR TRANSITORS

1y 12m to grant Granted May 26, 2026

18/475,675

Patent 12635178

SILICON CARBIDE SEMICONDUCTOR DEVICE

2y 7m to grant Granted May 19, 2026

18/228,782

Patent 12628428

An Array Of Capacitors, An Array Of Memory Cells, Method Used In Forming An Array Of Memory Cells, Methods Used In Forming An Array Of Capacitors, And Methods Used In Forming A Plurality Of Horizontally-Spaced Conductive Lines

2y 9m to grant Granted May 12, 2026

Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.

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Prosecution Projections

1-2

Expected OA Rounds

80%

Grant Probability

83%

With Interview (+2.7%)

2y 5m (~0m remaining)

Median Time to Grant

Low

PTA Risk

Based on 582 resolved cases by this examiner. Grant probability derived from career allowance rate.