Office Action Predictor
Application No. 18/174,039

SHIELDED LEAD PACKAGE FOR HIGH VOLTAGE DEVICES

Non-Final OA §102§103
Filed
Feb 24, 2023
Examiner
CHAMBLISS, ALONZO
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
68%
With Interview

Examiner Intelligence

90%
Career Allow Rate
1048 granted / 1166 resolved
Without
With
+-21.4%
Interview Lift
avg trend
2y 3m
Avg Prosecution
26 pending
1192
Total Applications
career history

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
35.5%
-4.5% vs TC avg
§102
36.2%
-3.8% vs TC avg
§112
14.8%
-25.2% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 2/24/2023 was filed before the mailing date of the Non-final rejection on 9/28/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Drawings The formal drawings filed on 2/24/2023 have been approved by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 3-5, 14, and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Hasegawa et al. (US 2015/0028462). With respect to Claims 1 and 14, Hasegawa teaches an electronic component 3 attached to a package substrate 1,2 , wherein the package substrate 1, 2 having an exposed surface on the microelectronic device. A lead 9 electrically connected to the electronic component 3, wherein the lead 9 extending away from the exposed surface of the package substrate 1, 2. A shielding dielectric material 14 laterally surrounding the lead 9. A heatsink 102 attached to the exposed surface of the package substrate (see paragraph 39-54; Figs. 1A-1C and 2). With respect to Claims 3 and 16, Hasegawa teaches the microelectronic device includes a carrier 111 located opposite from the exposed surface of the package substrate. The lead 9 extending through the carrier 111 (see Fig. 2). With respect to Claims 4 and 17, Hasegawa teaches a second electronic component 7 attached to the package substrate. A second lead 9 electrically connected to the second electronic component 7 and extending away from the exposed surface of the package substrate, and laterally surrounded by the shielding dielectric material (see Fig. 2). With respect to Claims 5 and 18, Hasegawa teaches the lead has a straight configuration extending away from the exposed surface of the package substrate (see Fig. 2). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 6, 7, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa et al.(US 2015/0028462) as applied to claims 1 and 14 above, and further in view of Kim et al. (US2023/0245942). With respect to Claim 6, 7, 12, and 13, Hasegawa discloses the claimed invention except for the lead has a J-lead configuration or a gull wing configuration. However, it is well known in the semiconductor industry to have a lead modified in the shape of a J-lead configuration or a gull wing configuration as evident by Kim (see paragraph 19; Fig. 1C). Allowable Subject Matter 9. Claims 8-13 are allowed. 10. Claims 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 11. The following is a statement of reasons for the indication of allowance subject matter: none of the prior art of record does not teach or suggest the combination of the electronic component and the package substrate are contacted by an encapsulation material, separate from the shielding dielectric material in claim 2. Forming a shielding dielectric material laterally surrounding a lead. The lead, the electronic component, and the package substrate are contacted by encapsulation material. An exposed surface of the package substrate extends through the encapsulation material and is exposed on the microelectronic device in claim 8. The prior art made of record and not relied upon is cited primarily to show the product of the instant invention. Conclusion 12. Any inquiry concerning the communication or earlier communications from the examiner should be directed to Alonzo Chambliss whose telephone number is (571) 272-1927. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Y. Choi can be reached on (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system Status information for published applications may be obtained from either Private PMR or Public PMR. Status information for unpublished applications is available through Private PMR only. For more information about the PMR system see hittp://pair-dkect.uspto. gov. Should you have questions on access to the Private PMR system contact the Electronic Center (EBC) at 866-217-9197 (toll-free). AC/September 28, 2025 /Alonzo Chambliss/ Primary Examiner, Art Unit 2897
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Prosecution Timeline

Feb 24, 2023
Application Filed
Sep 28, 2025
Non-Final Rejection — §102, §103
Mar 30, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
68%
With Interview (-21.4%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1166 resolved cases by this examiner