DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Species 1, as shown in FIG. 6A, was elected.
Amendment filed May 29, 2026 is acknowledged. Claims 1-2 and 9 have been amended.
Non-Elected Species, claims 5 and 7-8 have been withdrawn from consideration. Claims 1-10 are pending.
Action on merits of the Elected Species 1, claims 1-4, 6 and 9-10 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-4, 6 and 9-10 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There does not appear to be a written description of the claim limitation “a distance between the periphery of the active region and each of the plurality of second first-conductivity-type column regions and second second-conductivity-type column regions surrounding the periphery, measured along a direction normal to the periphery is substantially the same for the entire periphery” (amended claim 1) (emphasis added) in the application as filed.
As shown in FIG. 1, the distances along normal vectors (A-A’, B-B’ and C-C’) and along diagonal vector (not normal) are not the same.
Therefore, the new limitation is new matter.
Applicant must cancel the un-support new matters in response to the Office Action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over TAMAKI et al. (US. Pub. No. 2011/0115033) of record, in view of KAWADA (US. Pub. No. 2005/0167742) both of record.
With respect to claim 1, As best understood by the Examiner, TAMAKI teaches a semiconductor device, substantially as claimed including:
a semiconductor substrate that contains silicon and has a first main surface (1a) and a second main surface (1b) opposite to each other, the semiconductor substrate (1) having an active region (3) and a termination region (4b) surrounding a periphery of the active region in a plan view of the silicon semiconductor device;
a first parallel pn layer in which a plurality of first first-conductivity-type column regions (1e), each being of a first conductivity type (n), and a plurality of first second-conductivity-type column regions (6i), each being of a second conductivity type (p), are disposed adjacently and repeatedly alternate with one another, the first parallel pn layer being provided in the semiconductor substrate, in the active region (3);
a second parallel pn layer in which a plurality of second first-conductivity-type column regions (1e), each being of the first conductivity type (n), and a plurality of second second-conductivity-type column regions (6b), each being of the second conductivity type (p) are disposed adjacently and repeatedly alternate with one another, the second parallel pn layer being provided in the semiconductor substrate, in the termination region (4b), the second parallel pn layer being in contact with the first parallel pn layer;
a device structure provided in the semiconductor substrate, between the first main surface (1a) of the semiconductor substrate and the first parallel pn layer;
a first electrode (14) provided at the first main surface and electrically connected to the device structure; and
a second electrode (drain) provided at the second main surface (1b) of the semiconductor substrate, wherein
the plurality of second first-conductivity-type column regions (1e) and the plurality of second second-conductivity-type column regions (6b) are disposed in concentric shapes surrounding a periphery of the first parallel pn layer in the plan view of the silicon semiconductor device, a distance between the periphery of the active region (3) and each of the plurality of second first-conductivity-type column regions (1e) and second second-conductivity-type column regions (6b) surrounding the periphery, measured along a direction normal to the periphery (A-A’ or B-B’), is substantially the same for the entire periphery. (See FIGs. 22, 23).
Thus, TAMAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor substrate contains silicon carbide.
However, KAWADA teaches a silicon carbide semiconductor device including:
a semiconductor substrate that contains silicon carbide and has a first main surface (40a) and a second main surface opposite to each other, the semiconductor substrate having an active region (10) and a termination region (30) surrounding a periphery of the active region (10) in a plan view of the silicon carbide semiconductor device. (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the silicon semiconductor device of TAMAKI utilizing semiconductor substrate that contains silicon carbide as taught by KAWADA to provide a high voltage semiconductor device.
Further, it has been held to be within the general skill of a worker in the art to select a known material, silicon or silicon carbide, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 2, the semiconductor device of TAMAKI further comprises a voltage withstanding structure (8) provided in the semiconductor substrate, between the first main surface (1a) and the second parallel pn layer, the voltage withstanding structure (8) having:
a first second-conductivity-type region (8b) electrically connected to the first electrode (14), and
a second second-conductivity-type region (8c) provided adjacent to the first second-conductivity-type region (8), but closer to an end of the semiconductor substrate than is the first second-conductivity-type region (8b), wherein
the second second-conductivity-type region (8c) has an impurity concentration that is lower than an impurity concentration of the first second-conductivity-type region (8b), and
the first second-conductivity-type region (8b) and the second second-conductivity-type region (8c) are provided in concentric shapes surrounding the periphery of the active region (3) in the plan view of, in view of KADAWA, the silicon carbide semiconductor device.
With respect to claim 3, a border column region, of TAMAKI which is one of the plurality of second second-conductivity-type column regions (6b) that is disposed closest to a border between the first second-conductivity-type region (6i) and the second second-conductivity- type region (6b), satisfies
D1≥D2>D3, or
D2>D1 and D2-D1<1pm, where
D1 is a first distance from the active region (3) to an outer side surface of the border column region, in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate, the outer side surface facing the end of the semiconductor substrate,
D2 is a second distance from the active region to the border between the first second-conductivity-type region and the second second-conductivity-type region, in the direction of the normal vector, and
D3 is a third distance from the active region (3) to the border column region, in the direction of the normal vector.
With respect to claim 4, the plurality of second second-conductivity-type column regions (6b) of TAMAKI of KAWADA are electrically connected to the first electrode (14) via the voltage withstanding structure (8).
With respect to claim 6, the second parallel pn layer of TAMAKI or KAWADA is exposed at the first main surface.
With respect to claim 9, in view of KAWADA, the silicon carbide semiconductor device further comprises, in the device structure:
a first semiconductor region (4) of the second conductivity type, provided between the first main surface (40a) and the first parallel pn layer;
a plurality of second semiconductor regions (5) of the first conductivity type, selectively provided between the first main surface (40a) and the first semiconductor region (4);
a plurality of trenches (7) penetrating through the plurality of second semiconductor regions (5) and the first semiconductor region (4) and reaching the plurality of first first-conductivity-type column regions (3);
a plurality of gate electrodes (9) provided in the plurality of trenches (7), via a plurality of gate insulating films (8), respectively; and
a plurality of second-conductivity-type high-concentration regions (11a) selectively provided between the first semiconductor region (4) and the first parallel pn layer, closer to the second electrode (16) than are bottoms of the plurality of trenches (7), the plurality of second-conductivity-type high-concentration regions (11a) having an impurity concentration (p+) that is higher than an impurity concentration (p) of the first semiconductor region (4), wherein
the first electrode (15) is electrically connected to the plurality of second semiconductor regions (5), the first semiconductor region (4), and the plurality of second-conductivity-type high-concentration regions (11a),
the plurality of second-conductivity-type high-concentration regions (11a) extends between the first main surface (40a) and the second parallel pn layer in a direction from the active region (10) to the termination region (30), the plurality of second-conductivity-type high-concentration regions (11a) being in contact with the plurality of second second-conductivity-type column regions in a depth direction of the silicon carbide semiconductor device, and being in contact with the voltage withstanding structure (34) in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate (A), and
the plurality of second second-conductivity-type column regions is electrically connected to the first electrode (15), via the plurality of second-conductivity-type high-concentration regions (11a) or via the plurality of second-conductivity-type high-concentration regions (11a) and the voltage withstanding structure (34). (See FIGs. 1-2).
With respect to claim 10, the plurality of first first-conductivity-type column regions (1e) and the plurality of first second-conductivity-type column regions (6i) are disposed adjacently and repeatedly alternate with one another in a first direction that is parallel to the first main surface and extend in a striped pattern in a second direction that is parallel to the first main surface and orthogonal to the first direction. (See FIG. 23).
Claims 1-4, 6 and 10 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over TAMAKI ‘033, of record, in view of YAMAGUCHI et al. (US. Pub. No. 2003/0222327).
With respect to claim 1, As best understood by the Examiner, TAMAKI teaches a semiconductor device, substantially as claimed including:
a semiconductor substrate that contains silicon and has a first main surface (1a) and a second main surface (1b) opposite to each other, the semiconductor substrate (1) having an active region (3) and a termination region (4b) surrounding a periphery of the active region in a plan view of the silicon semiconductor device;
a first parallel pn layer in which a plurality of first first-conductivity-type column regions (1e), each being of a first conductivity type (n), and a plurality of first second-conductivity-type column regions (6i), each being of a second conductivity type (p), are disposed adjacently and repeatedly alternate with one another, the first parallel pn layer being provided in the semiconductor substrate, in the active region (3);
a second parallel pn layer in which a plurality of second first-conductivity-type column regions (1e), each being of the first conductivity type (n), and a plurality of second second-conductivity-type column regions (6b), each being of the second conductivity type (p) are disposed adjacently and repeatedly alternate with one another, the second parallel pn layer being provided in the semiconductor substrate, in the termination region (4b), the second parallel pn layer being in contact with the first parallel pn layer;
a device structure provided in the semiconductor substrate, between the first main surface (1a) of the semiconductor substrate and the first parallel pn layer;
a first electrode (14) provided at the first main surface and electrically connected to the device structure; and
a second electrode (drain) provided at the second main surface (1b) of the semiconductor substrate, wherein
the plurality of second first-conductivity-type column regions (1e) and the plurality of second second-conductivity-type column regions (6b) are disposed in concentric shapes surrounding a periphery of the first parallel pn layer in the plan view of the silicon semiconductor device, a distance between the periphery of the active region (3) and each of the plurality of second first-conductivity-type column regions (1e) and second second-conductivity-type column regions (6b) surrounding the periphery, measured along a direction normal to the periphery (A-A’ or B-B’), is substantially the same for the entire periphery. (See FIGs. 22, 23).
Thus, TAMAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor substrate contains silicon carbide, hence silicon carbide semiconductor device.
However, YAMAGUCHI teaches a silicon carbide semiconductor device including:
a semiconductor substrate (20) that contains silicon carbide and has a first main surface (top) and a second main surface (bottom) opposite to each other, the semiconductor substrate (20) having an active region (cell region) and a termination region surrounding a periphery of the active region in a plan view of the silicon carbide semiconductor device;
plurality of second first-conductivity-type column regions (22) and the plurality of second second-conductivity-type column regions (29) are disposed in concentric shapes surrounding a periphery of a first parallel pn layer (26/28) in the plan view of the silicon carbide semiconductor device, a distance between the periphery of the active region and each of the plurality of second first-conductivity-type column regions (22) and second second-conductivity-type column regions (29) surrounding the periphery, measured along a direction normal to the periphery (A-A), is substantially the same for the entire periphery. (See FIGs. 8-10).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of TAMAKI utilizing semiconductor substrate that contains silicon carbide, hence silicon carbide semiconductor device, as taught by YAMAGUCHI to provide a high voltage semiconductor device.
Further, it has been held to be within the general skill of a worker in the art to select a known material, silicon or silicon carbide, on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 2, the semiconductor device of TAMAKI further comprises a voltage withstanding structure (8) provided in the semiconductor substrate, between the first main surface (1a) and the second parallel pn layer, the voltage withstanding structure (8) having:
a first second-conductivity-type region (8b) electrically connected to the first electrode (14), and
a second second-conductivity-type region (8c) provided adjacent to the first second-conductivity-type region (8), but closer to an end of the semiconductor substrate than is the first second-conductivity-type region (8b), wherein
the second second-conductivity-type region (8c) has an impurity concentration that is lower than an impurity concentration of the first second-conductivity-type region (8b), and
the first second-conductivity-type region (8b) and the second second-conductivity-type region (8c) are provided in concentric shapes surrounding the periphery of the active region (3) in the plan view of, in view of KADAWA, the silicon carbide semiconductor device.
With respect to claim 3, a border column region, of TAMAKI which is one of the plurality of second second-conductivity-type column regions (6b) that is disposed closest to a border between the first second-conductivity-type region (6i) and the second second-conductivity- type region (6b), satisfies
D1≥D2>D3, or
D2>D1 and D2-D1<1pm, where
D1 is a first distance from the active region (3) to an outer side surface of the border column region, in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate, the outer side surface facing the end of the semiconductor substrate,
D2 is a second distance from the active region to the border between the first second-conductivity-type region and the second second-conductivity-type region, in the direction of the normal vector, and
D3 is a third distance from the active region (3) to the border column region, in the direction of the normal vector.
With respect to claim 4, the plurality of second second-conductivity-type column regions (6b) of TAMAKI or YAMAGUCHI are electrically connected to the first electrode (14) via the voltage withstanding structure (8).
With respect to claim 6, the second parallel pn layer of TAMAKI or YAMAGUCHI is exposed at the first main surface.
With respect to claim 10, the plurality of first first-conductivity-type column regions (1e) and the plurality of first second-conductivity-type column regions (6i) are disposed adjacently and repeatedly alternate with one another in a first direction that is parallel to the first main surface and extend in a striped pattern in a second direction that is parallel to the first main surface and orthogonal to the first direction. (See FIG. 23).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over TAMAKI ‘033 and YAMAGUCHI ‘327 as applied to claim 2 above, and further in view of KAWADA ‘167.
TAMAKI, in view of YAMAGUCHI, teaches the silicon carbide semiconductor device as described in claim 2 above further including, in the device structure:
a first semiconductor region (7) of the second conductivity type (p), provided between the first main surface (1a) and the first parallel pn layer (1e/6i);
a plurality of second semiconductor regions (21) of the first conductivity type (n), selectively provided between the first main surface (1a) and the first semiconductor region (7); and
a plurality of gate electrodes (9) provided via a plurality of gate insulating films (19), respectively, wherein
the first electrode (14) is electrically connected to the plurality of second semiconductor regions (21), the first semiconductor region (7), and
the plurality of second second-conductivity-type column regions (6b) is electrically connected to the first electrode (15), via the voltage withstanding structure (8).
Thus, TAMAKI and YAMAGUCHI are shown to teach all the features of the claim with the exception of explicitly disclosing the plurality of gate electrode being provided in a plurality of trenches.
However, KAWADA teaches a silicon carbide semiconductor device including:
a silicon carbide semiconductor device further comprises, in the device structure:
a first semiconductor region (4) of the second conductivity type (p), provided between first main surface (40a) and first parallel pn layer (67/68);
a plurality of second semiconductor regions (5) of the first conductivity type (n), selectively provided between the first main surface (40a) and the first semiconductor region (4);
a plurality of trenches (7) penetrating through the plurality of second semiconductor regions (5) and the first semiconductor region (4) and reaching the plurality of first first-conductivity-type column regions;
a plurality of gate electrodes (9) provided in the plurality of trenches (7), via a plurality of gate insulating films (8), respectively; and
a plurality of second-conductivity-type high-concentration regions (11) selectively provided between the first semiconductor region (4) and the first parallel pn layer, closer to second electrode (16) than are bottoms of the plurality of trenches (7), the plurality of second-conductivity-type high-concentration regions (11) having an impurity concentration (p+) that is higher than an impurity concentration (p) of the first semiconductor region (4), wherein
first electrode (15) is electrically connected to the plurality of second semiconductor regions (5), the first semiconductor region (4), and the plurality of second-conductivity-type high-concentration regions (11),
the plurality of second-conductivity-type high-concentration regions (11) extends between the first main surface (40a) and the second parallel pn layer (67/68) in a direction from the active region (10) to the termination region (30), the plurality of second-conductivity-type high-concentration regions (11) being in contact with the plurality of second second-conductivity-type column regions (68) in a depth direction (Z) of the silicon carbide semiconductor device, and being in contact with voltage withstanding structure (34) in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate (A), and
the plurality of second second-conductivity-type column regions (68) is electrically connected to the first electrode (15), via the plurality of second-conductivity-type high-concentration regions (11) or via the plurality of second-conductivity-type high-concentration regions (11) and the voltage withstanding structure (34). (See FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the silicon carbide semiconductor device of TAMAKI, having the plurality of the gate electrode being formed in the plurality of the trenches as taught by KAWADA for the same intended purpose of providing active device within the active region.
Response to Arguments
Applicant's arguments filed May 29, 2026 have been fully considered but they are not persuasive.
First of all, Applicant cited paragraph ¶ [0050] to support the new limitation.
However, for the record, the correct paragraph to be cited is ¶ [0054] not [0050].
Note that, the term “in the direction of the normal” refers to vectors A-A’; B-B’; and C-C’. as shown in FIG. 1.
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The diagonal line across 4 corners are not normal. At the corners, the distance are not the same.
As shown in FIG. 1 above, the distance at the corner are clearly not the same.
The evidence is very clear as shown in FIGs. 11-14 of the prior art.
Therefore, Claims 1 is unpatentable over TAMAKI ‘033 in view of KAWADA ‘167.
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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