DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election of Species 1, FIG. 6A, in the reply filed on November 26, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant identified claims 1-4, 6 and 9-10 are readable on the Elected Species 1.
Claims 1-10 are pending. Non-Elected Species, claims 5 and 7-8 have been withdrawn from consideration.
Action on merits of the Elected Species 1, claims 1-4, 6 and 9-10 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 27, 2023 and December 08, 2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
SILICON CARBIDE SEMICONDUCTOR DEVICE HAVING A PLURALITY OF PARALLEL PN COLUMNS SURROUNDING A PERIMETER OF ACTIVE REGION AND CONTACTING A VOLTAGE WITHSTANDING STRUCTURE
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over TAMAKI et al. (US. Pub. No. 2011/0115033) in view of KAWADA (US. Pub. No. 2021/0167167) of record.
With respect to claim 1, TAMAKI teaches a semiconductor device, substantially as claimed including:
a semiconductor substrate that contains silicon and has a first main surface (1a) and a second main surface (1b) opposite to each other, the semiconductor substrate (1) having an active region (3) and a termination region (4b) surrounding a periphery of the active region in a plan view of the semiconductor device;
a first parallel pn layer in which a plurality of first first-conductivity-type column regions (1e), each being of a first conductivity type, and a plurality of first second-conductivity-type column regions (6i), each being of a second conductivity type, are disposed adjacently and repeatedly alternate with one another, the first parallel pn layer being provided in the semiconductor substrate, in the active region (3);
a second parallel pn layer in which a plurality of second first-conductivity-type column regions (1e) and a plurality of second second-conductivity-type column regions (6b) are disposed adjacently and repeatedly alternate with one another, the second parallel pn layer being provided in the semiconductor substrate, in the termination region (4b), the second parallel pn layer being in contact with the first parallel pn layer;
a device structure provided in the semiconductor substrate, between the first main surface (1a) of the semiconductor substrate and the first parallel pn layer;
a first electrode (14) provided at the first main surface and electrically connected to the device structure; and
a second electrode (drain) provided at the second main surface (1b) of the semiconductor substrate, wherein the plurality of second first-conductivity-type column regions (1e) and the plurality of second second-conductivity-type column regions (6b) are disposed in concentric shapes surrounding a perimeter of the first parallel pn layer in the plan view of the semiconductor device. (See FIGs. 22, 23).
Thus, TAMAKI is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor substrate contains silicon carbide.
However, KAWADA teaches a silicon carbide semiconductor device including:
a semiconductor substrate that contains silicon carbide and has a first main surface (40a) and a second main surface opposite to each other, the semiconductor substrate having an active region (10) and a termination region (30) surrounding a periphery of the active region (10) in a plan view of the semiconductor device. (Se FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of TAMAKI utilizing semiconductor substrate that contains silicon carbide as taught by KAWADA to provide a high voltage semiconductor device.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416., 125 USPQ 416.
With respect to claim 2, the semiconductor device of TAMAKI further comprises a voltage withstanding structure (8) provided in the semiconductor substrate, between the first main surface (1a) and the second parallel pn layer, the voltage withstanding structure (8) having:
a first second-conductivity-type region (8b) electrically connected to the first electrode (14), and
a second second-conductivity-type region (8c) provided adjacent to the first second-conductivity-type region (8), but closer to an end of the semiconductor substrate than is the first second-conductivity-type region (8b), wherein
the second second-conductivity-type region (8c) has an impurity concentration that is lower than an impurity concentration of the first second-conductivity-type region (8b), and
the first second-conductivity-type region (8b) and the second second-conductivity-type region (8c) are provided in concentric shapes surrounding the periphery of the active region (3) in the plan view of the semiconductor device.
With respect to claim 3, a border column region, of TAMAKI which is one of the plurality of second second-conductivity-type column regions (6b) that is disposed closest to a border between the first second-conductivity-type region (6i) and the second second-conductivity- type region (6b), satisfies
D1≥D2>D3, or
D2>D1 and D2-D1<1pm, where
D1 is a first distance from the active region (3) to an outer side surface of the border column region, in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate, the outer side surface facing the end of the semiconductor substrate,
D2 is a second distance from the active region to the border between the first second-conductivity-type region and the second second-conductivity-type region, in the direction of the normal vector, and
D3 is a third distance from the active region (3) to the border column region, in the direction of the normal vector.
With respect to claim 4, the plurality of second second-conductivity-type column regions (6b) of TAMAKI of KAWADA are electrically connected to the first electrode (14) via the voltage withstanding structure (8).
With respect to claim 6, the second parallel pn layer of TAMAKI or KAWADA is exposed at the first main surface.
With respect to claim 9, in view of KAWADA, the silicon carbide semiconductor device further comprises, in the device structure:
a first semiconductor region (4) of the second conductivity type, provided between the first main surface (40a) and the first parallel pn layer;
a plurality of second semiconductor regions (5) of the first conductivity type, selectively provided between the first main surface (40a) and the first semiconductor region (4);
a plurality of trenches (7) penetrating through the plurality of second semiconductor regions (5) and the first semiconductor region (4) and reaching the plurality of first first-conductivity-type column regions (3);
a plurality of gate electrodes (9) provided in the plurality of trenches (7), via a plurality of gate insulating films (8), respectively; and
a plurality of second-conductivity-type high-concentration regions (11a) selectively provided between the first semiconductor region (4) and the first parallel pn layer, closer to the second electrode (16) than are bottoms of the plurality of trenches (7), the plurality of second-conductivity-type high-concentration regions (11a) having an impurity concentration (p+) that is higher than an impurity concentration (p) of the first semiconductor region (4), wherein
the first electrode (15) is electrically connected to the plurality of second semiconductor regions (5), the first semiconductor region (4), and the plurality of second-conductivity-type high-concentration regions (11a), the plurality of second-conductivity-type high-concentration regions (11a) extends between the first main surface (40a) and the second parallel pn layer in a direction from the active region (10) to the termination region (30), the plurality of second-conductivity-type high-concentration regions (11a) being in contact with the plurality of second second-conductivity-type column regions in a depth direction of the device, and being in contact with the voltage withstanding structure (34) in a direction of a normal vector from a center of the semiconductor substrate to the end of the semiconductor substrate (A), and the plurality of second second-conductivity-type column regions is electrically connected to the first electrode (15), via the plurality of second-conductivity-type high-concentration regions (11a) or via the plurality of second-conductivity-type high-concentration regions (11a) and the voltage withstanding structure (34). (See FIGs. 1-2).
With respect to claim 10, the plurality of first first-conductivity-type column regions (1e) and the plurality of first second-conductivity-type column regions (6i) are disposed adjacently and repeatedly alternate with one another in a first direction that is parallel to the first main surface and extend in a striped pattern in a second direction that is parallel to the first main surface and orthogonal to the first direction. (See FIG. 23).
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893