Prosecution Insights
Last updated: October 01, 2026
Application No. 18/174,906

PARALLEL WORKLOAD SCHEDULING BASED ON WORKLOAD DATA COHERENCE

Non-Final OA §103
Filed
Feb 27, 2023
Priority
Sep 19, 2022 — provisional 63/408,094
Examiner
WAI, ERIC CHARLES
Art Unit
2195
Tech Center
2100 — Computer Architecture & Software
Assignee
NVIDIA Corporation
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
541 granted / 659 resolved
+27.1% vs TC avg
Strong +27% interview lift
Without
With
+27.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
17 currently pending
Career history
685
Total Applications
across all art units

Statute-Specific Performance

§101
14.4%
-25.6% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
10.1%
-29.9% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 659 resolved cases

Office Action

§103
DETAILED ACTION Claims 1-20 are presented for examination. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/28/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 7-11, 13-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singh et al. (US PG Pub No. 2023/0410403 A1) in view of Szerszen et al. (US PG Pub No. 2021/0201558 A1). Regarding claim 1, Singh teaches a computer-implemented method, comprising: determining enqueuing the plurality of workload items into one or more queue segments ([0011], wherein the secondary rays are sorted and batched; [0061]); sorting the plurality of workload items in the one or more queue segments based at least on respective coherence information ([0011], wherein the secondary rays are sorted and batched; [0062]); and processing, using a set of processing units, the plurality of workload items in the one or more queue segments at least partially in parallel the order ([0013]; [0100]; [0102]). Singh does not teach a plurality of coherence keys representing coherence information associated with a plurality of workload items, each coherence key of the plurality of coherence keys corresponding to a respective workload item of the plurality of workload items; wherein the sorting is performed to place the plurality of workload items into an order based at least on a similarity of one or more key values of the respective coherence keys. Szerszen teaches the scheduling of rays (each ray is a unit of parallel work) based on its associated shader record key plus “quantized direction value” into a plurality of ray queues (abstract; [0285-286]). Szerszen further teaches “ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data” and grouping one or more of the plurality of rays into the plurality of ray queues based on a combination of the quantized direction value and a shader record key associated with the ray” ([0294-300]). In other words, the “quantized” direction value is itself a similarity mechanism whereby quantization buckets rays with similar direction values into the same queues. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to sort the plurality of workload items into an order based at least on a similarity of one or more key values of the respective coherence keys. One would be motivated by the desire to improve the efficiency of parallel processing as grouping workload items into the same queue increases the likelihood that items dispatched together to a parallel processing unit will follow the same execution path and access the same underlying data. Regarding claim 2, Singh teaches wherein the plurality of workload items are associated with one or more ray hit points detected in data for a scene to be rendered ([0008-12]); and wherein the coherence information is determined based at least on shader identifier data associated with one or more objects detected in the scene ([0075]). Regarding claim 3, Singh teaches wherein the coherence information includes at least one of execution coherence or data coherence ([0061-64]). Regarding claim 4, Szerszen teaches computing the plurality of coherence keys corresponding to the coherence information ([0285-286]). Regarding claim 7, Singh teaches partitioning the plurality of workload items into one or more segments organized as a ring buffer in memory ([0051]); sorting the plurality of workload items after a segment has been filled with unsorted items ([0062]); and after the workload items have been processed, providing the segment for use for additional workload items ([0064]). Regarding claims 8-11, 13, 15-18, they are the processor and system claims of claims 1-4 and 7 above. Therefore, they are rejected for the same reasons as claims 1-4 and 7 above. Regarding claims 14 and 20, Singh teaches wherein the processor is comprised in at least one of: a system for performing simulation operations; a system for performing simulation operations to test or validate autonomous machine applications; a system for performing digital twin operations; a system for performing light transport simulation; a system for rendering graphical output ([0006]); a system for performing deep learning operations; a system implemented using an edge device; a system for generating or presenting virtual reality (VR) content; a system for generating or presenting augmented reality (AR) content; a system for generating or presenting mixed reality (MR) content; a system incorporating one or more Virtual Machines (VMs); a system implemented at least partially in a data center; a system for performing hardware testing using simulation; a system for synthetic data generation; a collaborative content creation platform for 3D assets; or a system implemented at least partially using cloud computing resources. Allowable Subject Matter Claims 5-6, 12, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC C WAI whose telephone number is (571)270-1012. The examiner can normally be reached Monday - Friday 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Eric C Wai/Primary Examiner, Art Unit 2195
Read full office action

Prosecution Timeline

Show 2 earlier events
Sep 10, 2025
Non-Final Rejection mailed — §103
Dec 08, 2025
Examiner Interview Summary
Dec 08, 2025
Applicant Interview (Telephonic)
Feb 12, 2026
Response Filed
Mar 30, 2026
Final Rejection mailed — §103
Aug 28, 2026
Request for Continued Examination
Sep 02, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+27.3%)
3y 8m (~1m remaining)
Median Time to Grant
High
PTA Risk
Based on 659 resolved cases by this examiner. Grant probability derived from career allowance rate.

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