Attorney’s Docket Number: 55068-1268001
Filing Date: 02/27/2023
Claimed Foreign Priority Date: 07/12/2022 (KR 10-2022-0090386)
Applicants: Song et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 03/06/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 03/06/2026, responding to the Office action mailed on 12/17/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claims 8-9, 12, 14, and 16-20, and added new claims 21-24. Accordingly, pending in this application are claims 1-7, 10-11, 13, 15, and 21-24.
Response to Amendment
Applicant’s amendments to the Claims have overcome the respective claim objections and claim rejections under 35 U.S.C. 112, 35 U.S.C. 102, and 35 U.S.C. 103, as set forth in the Non-Final Office action mailed on 12/17/2025. Accordingly, all previous claim objections and claim rejections are hereby withdrawn. However, and new grounds of rejections are presented below, as necessitated by Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7, 10-11, 13, 15, and 21-23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee at al. (US2022/0367623).
Regarding Claim 1, Lee (see, e.g., Figs. 1, 2A-2J) shows all aspects of the instant invention including a semiconductor device (e.g., semiconductor device structure 10a) comprising:
- a substrate (e.g., substrate 102) including an active pattern (e.g., fin structures 108 later defining GAAs)
- a pair of channel patterns (e.g., pair of channel stacks each including a plurality of semiconductor layers 106) spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns (e.g., 106)
- a source/drain pattern (e.g., source/drain epitaxial structure 128 comprising epi portions 128a-c) between the pair of channel patterns
- a pair of conductive gate electrodes (e.g., each comprising work function layers 138 and a gate electrode layer 140) on the pair of channel patterns
- an active contact (e.g., contact comprising barrier layer 154 and contact structure 156) between the pair of conductive gate electrodes
- outer spacers (e.g., outer spacer portions 120b) on side surfaces of the pair of conductive gate electrodes
- wherein a distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern along the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned (see, e.g., Fig. 2J)
- inner spacers (e.g., inner spacer portions 120a) between the side surfaces of the pair of conductive gate electrodes and the outer spacers (e.g., 120a are L-shaped and include vertically extending portion)
- wherein each of the inner spacers includes a corner part which extends between lower surfaces of the outer spacers and the source/drain pattern (e.g., 120a are L-shaped and include a horizontally extending portion)
- wherein an upper surface of the source/drain pattern is in contact with the corner part of a first inner spacer of the inner spacers (see, e.g., Fig. 2J)
- wherein the source/drain pattern is vertically non-overlapping with the pair of conductive gate electrodes (see, e.g., Fig. 2J)
Regarding Claim 2, Lee (see, e.g., Fig. 2J) shows that a portion of the source/drain pattern (e.g., 128) at the first level at least partially vertically overlaps the outer spacers (e.g., 120b).
Regarding Claim 3, Lee (see, e.g., Fig. 2J) shows that the outer spacers (e.g., 120b) are vertically spaced apart from the source/drain pattern (e.g., 128).
Regarding Claim 4, Lee (see, e.g., Fig. 2J) shows that a width of the source/drain pattern (e.g., 128) in the first direction at the first level is greater than at each other levels.
Regarding Claim 7, Lee (see, e.g., Fig. 2J) shows that:
- the semiconductor patterns (e.g., 106) are vertically spaced apart from each other
- each of the pair of conductive gate electrodes (e.g., 138,140) are interposed respectively between the semiconductor patterns of the pair of channel patterns
- the semiconductor device further includes horizontal insulating patterns (e.g., inner spacer 126) interposed between the semiconductor patterns, and between the source/drain pattern and the pair of conductive gate electrodes.
Regarding Claim 10, Lee (see, e.g., Fig. 2J) shows that each of the outer spacers (e.g., 120b) is spaced apart from the source/drain pattern by the corner parts of the inner spacers (e.g., horizontal portion of 120a).
Regarding Claim 11, Lee (see, e.g., Fig. 2J) shows that a distance between the corner parts (e.g., horizontal portion of 120a) spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern (e.g., 128) at the first level in the first direction.
Regarding Claim 21, Lee (see, e.g., Fig. 2J) shows that an angle between the upper surface of the source/drain pattern and a side surface of the source/drain pattern, adjoining the upper surface of the source/drain pattern, is less than or equal to 900.
Regarding Claim 22, Lee (see, e.g., Fig. 2J) shows that the side surface of the source/drain pattern terminates at the corner part of the first inner spacer (e.g., horizontal portion of 120a).
Regarding Claim 23, Lee (see, e.g., Fig. 1) shows in isometric view that the exposed sides of semiconductor layers 106 are substantially planar to each other, and parallel to the side surfaces of dummy gate structures 114. Therefore, the examiner understand that Lee would implicitly shows that, in a plan view, widths in the first direction of upper surfaces of the channel patterns (e.g., 106) are substantially constant.
Regarding Claim 13, Lee (see, e.g., Figs. 1, 2A-2J) shows all aspects of the instant invention including a semiconductor device (e.g., semiconductor device structure 10a) comprising:
- a substrate (e.g., substrate 102) including an active pattern (e.g., fin structures 108 later defining GAAs)
- an isolation pattern (e.g., isolation structure material 112) surrounding the active pattern (see, e.g., Fig. 1)
- a pair of channel patterns (e.g., pair of channel stacks each including a plurality of semiconductor layers 106) spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns (e.g., 106)
- a source/drain pattern (e.g., source/drain epitaxial structure 128 comprising epi portions 128a-c) between the pair of channel patterns
- a pair of conductive gate electrodes (e.g., each comprising work function layers 138 and a gate electrode layer 140) on the pair of channel patterns
- gate capping patterns (e.g., gate cap comprising seal liner layer 160 and filling film 164) on upper surfaces of the pair of conductive gate electrodes
- an interlayer insulating layer (e.g., dielectric layer 150) between the pair of conductive gate electrodes
- outer spacers (e.g., outer spacer portions 120b) on side surfaces of the pair of conductive gate electrodes
- inner spacers (e.g., inner spacer portions 120a) between the side surfaces of the pair of conductive gate electrodes and the outer spacers
- gate insulating patterns (e.g., gate dielectric layer 136) between the pair of conductive gate electrodes and the inner spacers
- an active contact (e.g., contact comprising barrier layer 154 and contact structure 156) connected to the source/drain pattern through the interlayer insulating layer, wherein
- the outer spacers (e.g., 120b) and the inner spacers (e.g., 120a) extend on side surfaces of the gate capping patterns
- a distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern in the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned (see, e.g., Fig. 2J)
- each of the inner spacers includes a corner part which extends between lower surfaces of the outer spacers and the source/drain pattern (e.g., 120a are L-shaped and include a horizontally extending portion)
- an upper surface of the source/drain pattern is in contact with the corner part of a first inner spacer of the inner spacers (see, e.g., Fig. 2J)
- the source/drain pattern is vertically non-overlapping with the pair of conductive gate electrodes (see, e.g., Fig. 2J)
Regarding Claim 15, Lee (see, e.g., Fig. 2J) shows that the outer spacers (e.g., 120b) are spaced apart from the source/drain pattern by the inner spacers (e.g., 120a).
Allowable Subject Matter
Claim 24 is allowable.
Claims 5 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 03/06/2026 have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814
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