DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 05/06/2026 have been fully considered but they are not persuasive. Applicant argued that “Kim doesn't disclose that an end of the flexible circuitry 140 (the asserted FPC) is directly disposed on an upper surface of PCB 120.” Examiner respectfully disagreed as it can be seen in Fig. 5 Kim discloses this limitation.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 – 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130181360 A1, “Kim”) in view of CHANG et al. (US 20120241795 A1, “CHANG”) and further in view of SHIRAO et al. (US 20220057256 A1, “SHIRAO”).
Regarding claim 15, Kim discloses (Figs. 3, 6, 9) an optoelectronic apparatus, comprising: a printed circuit board (PCB) (120); a first substrate (110) and a second substrate (310) separately disposed on the PCB; an application specific integrated circuit (ASIC) (105) disposed on the first substrate; an optoelectronic component (305) disposed on the second substrate; and a flexible printed circuit (FPC) (140) and a conducting wire, wherein a first end of the FPC is directly disposed on an upper surface of the PCB (In a different embodiment, fig. 5: Kim discloses that a first end of the FPC directly disposed on the upper surface of the PCB. it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified one embodiment of Kim fig. 3 to incorporate the teachings of the embodiment in fig. 5) and is electrically connected to the ASIC disposed on the first substrate (para [0059]), a first end of the conducting wire is directly disposed on a second end of the FPC, a second end of the conducting wire is directly disposed on an upper surface of the second substrate, and Kim further discloses the conducting wire is configured to electrically connect the FPC to the optoelectronic component (See Fig. 6).
Kim is silent on an optoelectronic apparatus and an optoelectronic component.
However, CHANG discloses (Fig. 8) an optoelectronic apparatus (10) and an optoelectronic component (106)
Kim and CHANG are both considered to be analogous to the claimed invention because they are in the same field of PCN. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teachings of CHANG and provide an optoelectronic apparatus (10) and an optoelectronic component (106). Doing so would provide high energy efficiency, design flexibility and low operating costs and long lifespan.
Kim in view of CHANG is silent a first end of the conducting wire is directly disposed on a second end of the FPC, a second end of the conducting wire is directly disposed on an upper surface of the second substrate.
However, SHIRAO discloses (Fig. 1) a first end of the conducting wire is directly disposed on a second end of the FPC, a second end of the conducting wire is directly disposed on an upper surface of the second substrate (See annotated figure below).
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Kim in view of CHANG and SHIRAO are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG to incorporate the teachings of SHIRAO and provide a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate (See annotated figure above). Doing so can prevent deterioration of high frequency characteristics (para [0112]).
Regarding claim 16, Kim in view of CHANG and SHIRAO discloses the optoelectronic apparatus according to claim 15, wherein the second substrate is thicker than the first substrate (Having the second substrate thicker than the first substrate, does not include any inventive step, also the applicant does not provide any benefit for such limitation. Ogiso et al. us20250070888 A1 teaches this limitation).
Regarding claim 17, Kim in view of CHANG and SHIRAO discloses the optoelectronic apparatus according to claim 15, wherein the upper surface of the second substrate is higher over the PCB than an upper surface of the first substrate (Having the upper surface of the second substrate higher than an upper surface of the first substrate, does not include any inventive step, also the applicant does not provide any benefit for such limitation. Ogiso et al. us20250070888 A1 teaches this limitation).
Regarding claim 18, the optoelectronic apparatus according to claim 15, wherein Kim further discloses that the second end of the FPC (140) is directly disposed on the upper surface of the second substrate (310) (See Fig. 3).
Allowable Subject Matter
Claim 1, 3 – 5, 7 – 14 and 19 - 22 allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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/SIDI M MAIGA/
Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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