Prosecution Insights
Last updated: April 19, 2026
Application No. 18/175,227

Optoelectronic Apparatus and Optoelectronic Integration Method

Non-Final OA §103§112
Filed
Feb 27, 2023
Examiner
MAIGA, SIDI MOHAMED
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
85%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
22 granted / 29 resolved
+7.9% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
61
Total Applications
across all art units

Statute-Specific Performance

§103
64.2%
+24.2% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
6.6%
-33.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 29 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 2 – 5 and 10 - 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. “A difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold” is a vague idea which lacks particularity and distinctness in which to interpret the claim language. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 6 – 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130181360 A1, “Kim”) in view of CHANG et al. (US 20120241795 A1, “CHANG”). Regarding claim 1, Kim discloses (Figs. 3, 6, 9) an optoelectronic apparatus (100), comprising: a printed circuit board (PCB) (120); a first substrate (110) and a second substrate (310) separately disposed on the PCB (120); an application specific integrated circuit (ASIC) (105) disposed on the first substrate (para [0022] – [0024]); an optoelectronic component (305) disposed on the second substrate (310); and a flexible printed circuit (FPC) (140), wherein a first end of the FPC is disposed on an upper surface of the first substrate (110) and is electrically connected to the ASIC (para [0027]), and a second end of the FPC is disposed on the second substrate (310) and is electrically connected to the optoelectronic component (See Fig. 3). Kim is silent on an optoelectronic apparatus and an optoelectronic component. However, CHANG discloses (Fig. 8) an optoelectronic apparatus (10) and an optoelectronic component (106) Kim and CHANG are both considered to be analogous to the claimed invention because they are in the same field of PCN. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teachings of CHANG and provide an optoelectronic apparatus (10) and an optoelectronic component (106). Doing so would provide high energy efficiency, design flexibility and low operating costs and long lifespan. Regarding claim 6, Kim in view of CHANG discloses the optoelectronic apparatus according to claim 1, wherein Kim further discloses the optoelectronic apparatus further comprises a first conducting wire, and the first conducting wire is configured to electrically connect the second end of the FPC to the second substrate (See annotated Figure below). PNG media_image1.png 536 1309 media_image1.png Greyscale Regarding claim 8, Kim in view of CHANG discloses the optoelectronic apparatus according to claim 1, wherein Kim further discloses the optoelectronic apparatus further comprises a second conducting wire, and the second conducting wire is configured to electrically connect the first end of the FPC to the first substrate (See annotated Figure above). Regarding claim 7, Kim discloses the optoelectronic apparatus according to claim 1, wherein Kim further discloses the first end of the FPC is soldered to the upper surface of the first substrate (para [0027]). Claim(s) 2 – 5 and 10 – 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130181360 A1, “Kim”) in view of CHANG et al. (US 20120241795 A1, “CHANG”) and HUANG (US 20170141469 A1, “HUANG”) Regarding claim 2, Kim in view of CHANG discloses the optoelectronic apparatus according to claim 1, wherein Kim further discloses the optoelectronic apparatus further comprises a third substrate (615) disposed on an upper surface of the second substrate, the second end of the FPC is disposed on an upper surface of the third substrate, the third substrate is configured to electrically connect the FPC to the optoelectronic component (See Fig. 6, para [0073]), and Kim in view of CHANG is silent a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold. However, HUANG discloses a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold (para [0039], [0051], [0063] and [0077]). Kim in view of CHANG and HUANG are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG to incorporate the teachings of HUANG and provide a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold (para [0039], [0051], [0063] and [0077]).Doing so would provide impedance matching, structural flexibility and integration (para [0040] – [0043]). Regarding claim 3, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 2, wherein Kim further discloses the upper surface of the third substrate is electrically connected to the second end of the FPC, a lower surface of the third substrate is electrically connected to the upper surface of the second substrate, (See para [0063]), and Kim in the embodiment of (Fig. 6) is silent on the upper surface of the third substrate is electrically connected to the lower surface of the third substrate using at least one through-hole. However Kim discloses in the embodiment of (Fig. 5) the upper surface of the third substrate (415) is electrically connected to the lower surface of the third substrate using at least one through-hole (See para [0055]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified embodiment of (Fig. 6) to incorporate the teachings of embodiment of (Fig. 5) and provide the upper surface of the third substrate (415) is electrically connected to the lower surface of the third substrate using at least one through-hole to provide vertical interconnect with the substrate (See para [0055]). Regarding claim 4, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 3, wherein Kim further discloses the upper surface of the third substrate is soldered to the second end of the FPC (See para [0063]). Regarding claim 5, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 3, wherein Kim further discloses the lower surface of the third substrate and the upper surface of the second substrate are soldered using a first ball grid array (BGA) (See Fig. 6). . Regarding claim 10, Kim discloses (Figs. 3, 6, 9) an optoelectronic apparatus, comprising: a printed circuit board (PCB) (455), a first substrate (445) and a second substrate (645) separately disposed on the PCB; an application specific integrated circuit (ASIC) (405, 410) disposed on the first substrate (445); an optoelectronic component (605) disposed on the second substrate (645); a flexible printed circuit (FPC) (140), and a third substrate (615) disposed on an upper surface of the second substrate (645), wherein a first end of the FPC is disposed on an upper surface of the PCB and is electrically connected to the ASIC disposed on the first substrate (para [0059]), a second end of the FPC is disposed on an upper surface of the third substrate, and the third substrate is configured to electrically connect the FPC to the optoelectronic component (See Fig. 6, para [0073]), and a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold. Kim is silent on an optoelectronic apparatus and an optoelectronic component. However, CHANG discloses (Fig. 8) an optoelectronic apparatus (10) and an optoelectronic component (106) Kim and CHANG are both considered to be analogous to the claimed invention because they are in the same field of PCN. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teachings of CHANG and provide an optoelectronic apparatus (10) and an optoelectronic component (106). Doing so would provide high energy efficiency, design flexibility and low operating costs and long lifespan. Kim in view of CHANG is silent a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold. However, HUANG discloses a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold (para [0039], [0051], [0063] and [0077]). Kim in view of CHANG and HUANG are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG to incorporate the teachings of HUANG and provide a difference between a dielectric constant of a material of the third substrate and a dielectric constant of a material of the FPC is less than a preset dielectric constant threshold (para [0039], [0051], [0063] and [0077]).Doing so would provide impedance matching, structural flexibility and integration (para [0040] – [0043]). Regarding claim 11, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 10, wherein Kim further discloses the upper surface of the third substrate is electrically connected to the second end of the FPC, a lower surface of the third substrate is electrically connected to the upper surface of the second substrate (See para [0063]), and Kim in the embodiment of (Fig. 6) is silent on the upper surface of the third substrate is electrically connected to the lower surface of the third substrate using at least one through-hole. However Kim discloses in the embodiment of (Fig. 5) the upper surface of the third substrate (415) is electrically connected to the lower surface of the third substrate using at least one through-hole (See para [0055]). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified embodiment of (Fig. 6) to incorporate the teachings of embodiment of (Fig. 5) and provide the upper surface of the third substrate (415) is electrically connected to the lower surface of the third substrate using at least one through-hole to provide vertical interconnect with the substrate (See para [0055]). Regarding claim 12, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 11, wherein Kim further discloses the upper surface of the third substrate is soldered to the second end of the FPC (See para [0063]). Regarding claim 13, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 11, wherein Kim further discloses the lower surface of the third substrate and the upper surface of the second substrate are soldered using a first ball grid array (BGA) (See Fig. 6). Claim(s) 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130181360 A1, “Kim”) in view of CHANG et al. (US 20120241795 A1, “CHANG”) as applied to claim 1 above, and further in view of SHIRAO et al. (US 20220057256 A1, “SHIRAO”). Regarding claim 9, Kim in view of CHANG discloses the optoelectronic apparatus according to claim 1, Kim in view of CHANG is silent on wherein a material of the FPC is an organic material, and a material of the second substrate is ceramic. However, SHIRAO discloses (Fig. 7) wherein a material of the FPC is an organic material (See para [0057]), and a material of the second substrate is ceramic (See para [0039]). Kim in view of CHANG and SHIRAO are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG to incorporate the teachings of SHIRAO and provide wherein a material of the FPC is an organic material (See para [0057]), and a material of the second substrate is ceramic (See para [0039]). Doing so would enable efficient heat dissipation and provide a material having a small loss of a high frequency signal (para [0039] and [0057]) Regarding claim 15, Kim discloses (Figs. 3, 6, 9) an optoelectronic apparatus, comprising: a printed circuit board (PCB) (120); a first substrate (110) and a second substrate (310) separately disposed on the PCB; an application specific integrated circuit (ASIC) (105) disposed on the first substrate; an optoelectronic component (305) disposed on the second substrate; and a flexible printed circuit (FPC) (140) and a conducting wire, wherein a first end of the FPC is disposed on an upper surface of the PCB and is electrically connected to the ASIC disposed on the first substrate (para [0059]), a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate, and Kim further discloses the conducting wire is configured to electrically connect the FPC to the optoelectronic component (See Fig. 6). Kim is silent on an optoelectronic apparatus and an optoelectronic component. However, CHANG discloses (Fig. 8) an optoelectronic apparatus (10) and an optoelectronic component (106) Kim and CHANG are both considered to be analogous to the claimed invention because they are in the same field of PCN. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim to incorporate the teachings of CHANG and provide an optoelectronic apparatus (10) and an optoelectronic component (106). Doing so would provide high energy efficiency, design flexibility and low operating costs and long lifespan. Kim in view of CHANG is silent a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate. However, SHIRAO discloses (Fig. 1) a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate (See annotated figure below). PNG media_image2.png 602 1202 media_image2.png Greyscale Kim in view of CHANG and SHIRAO are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG to incorporate the teachings of SHIRAO and provide a first end of the conducting wire is disposed on a second end of the FPC, a second end of the conducting wire is disposed on an upper surface of the second substrate (See annotated figure above). Doing so can prevent deterioration of high frequency characteristics (para [0112]). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130181360 A1, “Kim”) in view of CHANG et al. (US 20120241795 A1, “CHANG”) and HUANG (US 20170141469 A1, “HUANG”) as applied to claim 11 above, and further in view of SHIRAO et al. (US 20220057256 A1, “SHIRAO”). Regarding claim 14, Kim in view of CHANG and HUANG discloses the optoelectronic apparatus according to claim 11, Kim in view of CHANG and HUANG is silent on wherein a material of the FPC is an organic material, and a material of the second substrate is ceramic. However, SHIRAO discloses (Fig. 7) wherein a material of the FPC is an organic material (See para [0057]), and a material of the second substrate is ceramic (See para [0039]). Kim in view of CHANG and HUANG and SHIRAO are both considered to be analogous to the claimed invention because they are in the same field of PCB. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim in view of CHANG and HUANG to incorporate the teachings of SHIRAO and provide wherein a material of the FPC is an organic material (See para [0057]), and a material of the second substrate is ceramic (See para [0039]). Doing so would enable efficient heat dissipation and provide a material having a small loss of a high frequency signal (para [0039] and [0057]) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIDI M MAIGA/Examiner, Art Unit 2847 /STANLEY TSO/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Feb 27, 2023
Application Filed
Feb 06, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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ELECTRICAL APPARATUS AND PLUG
2y 5m to grant Granted Mar 24, 2026
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HIGH-FREQUENCY ELECTRONIC COMPONENT
2y 5m to grant Granted Mar 24, 2026
Patent 12568584
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2y 5m to grant Granted Mar 03, 2026
Patent 12563665
INSULATING CIRCUIT BOARD AND SEMICONDUCTOR DEVICE IN WHICH SAME IS USED
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WIRING SUBSTRATE
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
85%
With Interview (+9.4%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 29 resolved cases by this examiner. Grant probability derived from career allow rate.

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