DETAILED ACTION
1. This action is in response to the RCE filed on 1/23/26.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/23/26 has been entered.
Claim Rejections - 35 USC § 102
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-2, 4-7, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Price et al. (US 20160308355).
Regarding claim 1: Price et al. discloses a device (i.e. figures 1-4), comprising:
a switch circuit (i.e. circuit of figure 4) comprising one or more transistors (i.e. 126, 124) and configured to:
bias bulk terminals (i.e. bulk terminal BG of 126, 124) of the one or more transistors with (i.e. bulk terminal of 126, 124) a bulk voltage (i.e. voltage to the bulk terminal BG of 126, 124); and
output either a first power supply voltage (i.e. from 104) or a second power supply voltage (i.e. from 106) as a voltage output signal (i.e. output signal at 102) based on either a first selection signal (i.e. 122(1)) or a second selection signal (i.e. 122(2)) respectively,
wherein the second power supply voltage (i.e. from 106) is at a first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104) lower than that of the first power supply voltage (i.e. from 104) during a first mode of operation (i.e. first mode by provides first selection signal 122(1)) and at a second voltage level higher (i.e. second voltage level, when the voltage of 106 > the voltage of 104) than that of the second power supply voltage (i.e. the voltage of the power supply 110 is fluctuation over time. Therefore, when the voltage level of 106 is > the voltage of 104. This means, the second voltage level of 106 is higher than that of the second power supply voltage of the first voltage level) during a second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25); and
a confirmation circuit (i.e. 112) configured to provide a confirmation signal (i.e. 116) to a controller (i.e. 118) device to indicate (i.e. by circuit 112, see ¶ 21 and 24-25) whether the voltage output signal (i.e. output signal at 102) transitioned from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106, 106) (i.e. ¶ 21-32), in response to the second power supply voltage (i.e. from 106) transitioning from the first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104) in the first mode of operation (i.e. first mode by provides first selection signal 122(1)) to the second voltage level (i.e. second voltage level, when the voltage of 106 > the voltage of 104) in the second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25).
Regarding claim 2: further comprising: a voltage generator (i.e. generator includes circuit of 402, 112, 118) configured to output the bulk voltage (i.e. voltage to the bulk terminal BG of 126, 124) based on a comparison between the first power supply voltage (i.e. from 104) and the second power supply voltage (i.e. from 106) (i.e. ¶ 21-32).
Regarding claim 4: (i.e. figures 1-4) wherein the voltage generator (i.e. generator includes circuit of 402, 112, 118) further comprises an initialization circuit (i.e. 402, 406) configured to provide a pre-bulk voltage (i.e. voltage form 402) to the voltage generator (i.e. generator includes circuit of 402, 112, 118) and to transition the pre-bulk voltage (i.e. voltage from 402) from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106) in response to the transition from the first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104)in the first mode of operation (i.e. first mode by provides first selection signal 122(1)) to the second voltage level (i.e. second voltage level, when the voltage of 106 > the voltage of 104) in the second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25).
Regarding claim 5: (i.e. figures 1-4) wherein the voltage generator further comprises a bulk terminal switch (i.e. 406) configured to transition the bulk voltage (i.e. voltage to the bulk terminal of 126, 124) from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106) in response to the transition from the first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104)in the first mode of operation (i.e. first mode by provides first selection signal 122(1)) to the second voltage level (i.e. second voltage level, when the voltage of 106 > the voltage of 104) in the second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25).
Regarding claim 6: (i.e. figures 1-4) wherein the switch circuit is further configured to output either the first power supply voltage (i.e. from 104) or the second power supply voltage (i.e. from 106) based on a control signal (i.e. signal of 112, 118) received from the controller device (i.e. control device of figure 4) (i.e. ¶ 21-32).
Regarding claim 7: (i.e. figures 1-4) wherein the switch circuit further comprises a cross-coupled arrangement of logic devices (i.e. 320, 314, 412) configured to control a first transistor device (i.e. 126) and a second transistor device (i.e. 124) to pass the first power supply voltage (i.e. from 104) and the second power supply voltage (i.e. from 106), respectively (i.e. ¶ 21-32).
Regarding claims 16-20: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Price et al. (US 20160308355) in view of Rao et al. (US 20130321026).
Regarding claim 8: Price et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the cross-coupled arrangement of logic devices comprises a cross-coupled arrangement of NOR logic devices.
Rao et al. disclose a voltage compensated level shifter circuit (i.e. figure 3) comprising the cross-coupled arrangement of logic devices comprises a cross-coupled arrangement of NOR logic devices (i.e. (i.e. ¶ 40, 42, 47)).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Price et al.’s invention with the circuit as disclose by Rao et al. to provide early constant duty cycle and matching rise and fall slopes of the output of the level-shifter, no meta-stability, and nearly constant propagation delay across power supply levels.
8. Claim 9-15 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Price et al. (US 20160308355) in view of Soundararajan (US 20180069566).
Regarding claims 9 and 21: Price et al. disclose a system (i.e. figures 1-4 and 7), comprising:
a memory device (i.e. memory of 710, 702) (i.e. ¶ 40-42);
a controller device (i.e. control device of figure 7 or (i.e. control device of figure 4) (i.e. ¶ 21-32)); and
a power supply interface (i.e. power supply interface of figures 1-4) coupled (i.e. electrically coupled) to the memory device (i.e. memory of 710, 702) and the controller device (i.e. control device of figure 7), wherein the power supply interface (i.e. power supply interface of figures 1-4) comprises:
a switch circuit (i.e. circuit of figure 4) comprising one or more transistors (i.e. 126, 124) and configured to:
bias bulk terminals (i.e. bulk terminal BG of 126, 124) of the one or more transistors with (i.e. bulk terminal of 126, 124) a bulk voltage (i.e. voltage to the bulk terminal BG of 126, 124); and
output either a first power supply voltage (i.e. from 104) or a second power supply voltage (i.e. from 106) as a voltage output signal (i.e. output signal at 102) to the memory device (i.e. memory of 710, 702) based on either a first selection signal (i.e. 122(1)) or a second selection signal (i.e. 122(2) (i.e. ¶ 40-42); and
a comparator circuit (i.e. circuit of 112) configured to compare the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106),
a confirmation circuit (i.e. 112) configured to provide a confirmation signal (i.e. 116) to a controller (i.e. 118) device to indicate (i.e. by circuit 112, see ¶ 21 and 24-25) whether the voltage output signal (i.e. output signal at 102) transitioned from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106) (i.e. ¶ 21-32),
but does not specifically disclose wherein the comparator circuit comprises at least a first stage having a plurality of comparators and a second stage having at least one comparator, and wherein comparator outputs from the plurality of comparators in the first stage are received by the at least one comparator in the second stage
Soundararajan discloses the comparator circuit (i.e. figure 3) comprises at least a first stage (i.e. 310) having a plurality of comparators and a second stage (i.e. 312) having at least one comparator, and wherein comparator outputs from the plurality of comparators in the first stage (i.e. output of 310) are received by the at least one comparator in the second stage (i.e. input of 312).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Price et al.’s invention with *** as disclose by Soundararajan to improve performance.
Regarding claim 10: further comprising: a voltage generator (i.e. generator includes circuit of 402, 112, 118) configured to output the bulk voltage (i.e. voltage to the bulk terminal BG of 126, 124) based on a comparison between the first power supply voltage (i.e. from 104) and the second power supply voltage (i.e. from 106) (i.e. ¶ 21-32).
Regarding claims 11: (i.e. figures 1-4) wherein the comparator circuit (i.e. circuit of 112) comprises a comparator output configured to transistor form a first value to a second value (i.e. value output of 112) in response to the second power supply voltage (i.e. from 104) being higher than the first power supply voltage (i.e. from 106) (i.e. ¶ 21-32).
Regarding claim 12: (i.e. figures 1-4) wherein the voltage generator further comprises an initialization circuit (i.e. 402, 406) configured to provide a pre-bulk voltage (i.e. voltage from 402) to the voltage generator (i.e. generator includes circuit of 402, 112, 118) and to transition the pre-bulk voltage from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. circuit of 118) in response to the second power supply voltage being higher than the first power supply voltage (i.e. ¶ 21-32).
Regarding claim 13: (i.e. figures 1-4) wherein the voltage generator further comprises a bulk terminal switch (i.e. 406) configured to transition the bulk voltage from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106) in response to the second power supply voltage being higher than the first power supply voltage (i.e. ¶ 32-33).
Regarding claim 14: (i.e. figures 1-4) wherein the switch circuit is further configured to output either the first power supply voltage (i.e. from 104) or the second power supply voltage (i.e. from 106) based on a control signal (i.e. signal of 112, 118) received from the controller device (i.e. control device of figure 4) (i.e. ¶ 21-32).
Regarding claim 15: (i.e. figures 1-4) wherein the switch circuit further comprises a cross-coupled arrangement of logic devices (i.e. 320, 314, 412) configured to control a first transistor device (i.e. 126) and a second transistor device (i.e. 124) to pass the first power supply voltage (i.e. from 104) and the second power supply voltage (i.e. from 106), respectively (i.e. ¶ 21-32).
Response to Arguments
9. Applicant's arguments filed 1/23/26 have been fully considered but they are not persuasive.
Applicant argues that “Price does not teach or suggest that either first supply voltage 104 or second supply voltage 106 is at a first voltage level during a first mode of operation and at a second voltage level during a second mode of operation, where automatic voltage switching circuit 100 transitions from first supply voltage 104 to second supply voltage 106-or vice versa-in response to one of supply voltages 104/106 transitioning from the first voltage level in the first mode of operation to the second voltage level in the second mode of operation. Indeed, Price does not disclose transitioning its supply voltages based on a change in mode of operation. For at least these reasons, the above-noted distinguishing features of claims 1 and 16 are distinguishable over Price.”
The Examiner disagrees, because Price discloses (i.e. figures 1-4) (i.e. equivalent shows in parentheses) wherein the second power supply voltage (i.e. from 106) is at a first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104) lower than that of the first power supply voltage (i.e. from 104) during a first mode of operation (i.e. first mode by provides first selection signal 122(1)) and at a second voltage level higher (i.e. second voltage level, when the voltage of 106 > the voltage of 104) than that of the second power supply voltage (i.e. the voltage of the power supply 110 is fluctuation over time. Therefore, when the voltage level of 106 is > the voltage of 104. This means, the second voltage level of 106 is higher than that of the second power supply voltage of the first voltage level) during a second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25); and a confirmation circuit (i.e. 112) configured to provide a confirmation signal (i.e. 116) to a controller (i.e. 118) device to indicate (i.e. by circuit 112, see ¶ 21 and 24-25) whether the voltage output signal (i.e. output signal at 102) transitioned from the first power supply voltage (i.e. from 104) to the second power supply voltage (i.e. from 106, 106) (i.e. ¶ 21-32), in response to the second power supply voltage (i.e. from 106) transitioning from the first voltage level (i.e. first voltage level, when the voltage of 106 < the voltage of 104) in the first mode of operation (i.e. first mode by provides first selection signal 122(1)) to the second voltage level (i.e. second voltage level, when the voltage of 106 > the voltage of 104) in the second mode of operation (i.e. second mode by provides second selection signal 11(2)) (i.e. ¶ 22-25).
Applicant’s arguments with respect to claim(s) 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/ Primary Examiner, Art Unit 2838