DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
Claim Objections
Claim 1 is objected to because of the following informalities: the preamble of the claim is suggested to be changed to “A shield structure for a semiconductor chip, the shield structure comprising:” for clarity. Appropriate correction is required.
Claim 17 is objected to because of the following informalities: the preamble of the claim is suggested to be changed to “A magnetic shield structure for a semiconductor chip, the magnetic shield structure comprising” for clarity. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (WO 2011/046091; see copy with English translation).
Regarding claim 1, Watanabe discloses, in FIGS. 2-3 and in related text, a shield structure for a semiconductor chip comprising:
a chip mounting region (around chip 20) on a base plate (10); and
a shell (30) arranged over the base plate to provide a chamber (MC) having a volume within which the chip mounting region is arranged, wherein the shell is connected to the base plate (see Watanabe, [0015]-[0021]).
Regarding claim 2, Watanabe discloses the structure of claim 1.
Watanabe discloses wherein the shell (30) comprises a surface having a curved profile (see Watanabe, FIG. 2)
Regarding claim 3, Watanabe discloses the structure of claim 2.
Watanabe discloses wherein the shell (30) comprises a domed portion (see Watanabe, FIGS. 2-3, [0020]).
Regarding claim 4, Watanabe discloses the structure of claim 2.
Watanabe discloses wherein the surface having a curved profile is an outer surface of the shell (30) (see Watanabe, FIG. 2).
Regarding claim 5, Watanabe discloses the structure of claim 4.
Watanabe discloses wherein the shell (30) further comprises an inner surface having a curved profile (see Watanabe, FIG. 2).
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watanabe (WO 2011/046091; see copy with English translation).
Regarding claim 17, Watanabe discloses, in FIGS. 2-3 and in related text, a magnetic shield structure for a semiconductor chip comprising:
a chip mounting region (around chip 20) on a base plate (10); and
a shell (30) arranged over the base plate to provide a chamber (MC) having a volume within which the chip mounting region is arranged, wherein the shell comprises a magnetic material (see Watanabe, [0015]-[0021]).
Claims 1 and 6-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otsuka (US 2016/0293833).
Regarding claim 1, Otsuka discloses, in FIG. 6 and in related text, a shield structure for a semiconductor chip comprising:
a chip mounting region (around chip 102) on a base plate (101a, 103, 101b); and
a shell (104, 105) arranged over the base plate to provide a chamber having a volume within which the chip mounting region is arranged, wherein the shell is connected to the base plate (see Otsuka, [0025]-[0027])
Regarding claim 6, Otsuka discloses the structure of claim 1.
Otsuka discloses wherein the shell (104, 105) and the base plate (103) are magnetically coupled (see Otsuka, FIG. 6, [0041]-[0043]).
Regarding claim 7, Otsuka discloses the structure of claim 1.
Otsuka discloses wherein the shell (104, 105) comprises a bottom shell surface adjoining an outer shell surface and an inner shell surface, and the bottom shell surface contacts the base plate (101a, 103, 101b) (see Otsuka, FIG. 6).
Regarding claim 8, Otsuka discloses the structure of claim 1.
Otsuka discloses a first via (114) in the base plate (101a) and arranged at least partially below the shell (105) (see Otsuka, FIG. 6, [0043]).
Regarding claim 9, Otsuka discloses the structure of claim 8.
Otsuka discloses wherein the first via (144) has a portion that directly contacts the shell (104, 105) (see Otsuka, FIG. 6).
Regarding claim 10, Otsuka discloses the structure of claim 8.
Otsuka discloses a second via (114) in the base plate (101a, 103, 101b) and arranged at least partially below the shell (see Otsuka, FIG. 6, [0043]).
Regarding claim 11, Otsuka discloses the structure of claim 8.
Otsuka discloses wherein the first via (114) comprises a via plug (105a) (see Otsuka, FIGS. 6-7, [0067]).
Regarding claim 12, Otsuka discloses the structure of claim 11.
Otsuka discloses wherein the via plug (105a) comprises a magnetic material (see Otsuka, [0046], [0067]).
Regarding claim 13, Otsuka discloses the structure of claim 1.
Otsuka discloses wherein the chip mounting region (around chip 102) is arranged within a central region of the base plate (101a, 103, 101b) under the shell (104, 105) (see Otsuka, FIG. 6).
Regarding claim 14, Otsuka discloses the structure of claim 1.
Otsuka discloses wherein the base plate (101a, 103, 101b) comprises a multi-layer plate (see Otsuka, FIG. 6, and discussion on claim 1 above).
Regarding claim 15, Otsuka discloses the structure of claim 14.
Otsuka discloses wherein the multi-layer plate (101a, 103, 101b) includes a top layer (101a) over a bottom layer (103), wherein the top layer comprises a non-magnetic material (glass epoxy resin) (see Otsuka, [0027]).
Regarding claim 16, Otsuka discloses the structure of claim 15.
Otsuka discloses wherein the multi-layer plate comprises a via (114) in the top layer (101a) (see Otsuka, FIG. 6, [0043]).
Claims 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Otsuka (US 2016/0293833).
Regarding claim 17, Otsuka discloses, in FIG. 6 and in related text, a magnetic shield structure for a semiconductor chip comprising:
a chip mounting region (around chip 102) on a base plate (101a, 103, 101b); and
a shell (104, 105) arranged over the base plate to provide a chamber having a volume within which the chip mounting region is arranged, wherein the shell comprises a magnetic material (see Otsuka, [0025]-[0027], [0046]).
Regarding claim 18, Otsuka discloses the structure of claim 17.
Otsuka discloses wherein the base plate (103) comprises a magnetic material (see Otsuka, [0046]).
Regarding claim 19, Otsuka discloses the structure of claim 17.
Otsuka discloses wherein the base plate (101a) comprises a first via (114) directly contacting a bottom surface of the shell (105) (see Otsuka, FIG. 6, [0043]).
Regarding claim 20, Otsuka discloses the structure of claim 19.
Otsuka discloses wherein the base plate (101a) comprises a second via (114) directly contacting a bottom surface of the shell (105), the second via being spaced from the first via (114) (see Otsuka, FIG. 6, [0043]).
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kikitsu (US 2018/0337139).
Regarding claim 1, Kikitsu discloses, in FIGS. 1A-1D and in related text, a shield structure for a semiconductor chip comprising:
a chip mounting region (around chip 53) on a base plate (60); and
a shell (10) arranged over the base plate to provide a chamber having a volume within which the chip mounting region is arranged, wherein the shell is connected to the base plate (see Kikitsu, [0019]-[0020]).
Regarding claim 2, Kikitsu discloses the structure of claim 1.
Kikitsu discloses wherein the shell (10) comprises a surface having a curved profile (see Kikitsu, FIGS. 1B-1C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kikitsu.
Regarding claim 3, Kikitsu discloses the structure of claim 2.
Kikitsu discloses the shell (10) having a cup shape (see Kikitsu, FIGS. 1B-1C). Kikitsu does not explicitly discloses the shell having a hemispherical or domed shape. Kikitsu does not explicitly disclose the limitation “wherein the shell comprises a domed portion”.
However, the limitation is mere changes in shape, and would be considered as a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed was significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also, MPEP § 2144.04.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811