DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is in reply to the application filed on 02/27/2023. Claims 1-20 are currently pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al (Japanese Patent Publication No. JP2013021017) as evidenced by the machine translation of Kawase, in view of Kajiyama et al (US PGPUB No. 2009/001623), hereinafter referred to as Kawase and Kajiyama, respectively.
Regarding claim 1, Kawase discloses a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising:
sticking a protection tape on a first surface of the semiconductor substrate [Kawase, fig 2, 23 is attached to 11 on a first surface];
cutting the protection tape by supporting the second surface of the semiconductor substrate and flattening the protection tape [Kawase, fig 5, 28 flattens 23 and page 18, pp’s 0026-0027 and page 19, pp 0028-0029]; and
second grinding by supporting the protection tape and grinding the second surface of the semiconductor substrate [Kawase, figs 7-8, surface 11b is ground by 52 and page 25, pp 0040].
Kawase does not explicitly disclose first grinding by supporting the protection tape and grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface.
Kajiyama teaches a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising:
sticking a protection tape on a first surface of the semiconductor substrate [Kajiyama, fig 3A, 10 is adhered to a first surface of 1 and page 2, pp 0030];
first grinding by supporting the protection tape and grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface [Kajiyama, page 3, pp 0031, and page 4, pp 0048-0049 rough grinding step]; and
second grinding by supporting the protection tape and grinding the second surface of the semiconductor substrate [Kajiyama, page 3, pp 0031, and page 4, pp 0049, finish grinding step].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the rough and finish grinding steps as taught by Kajiyama within the method of Kawase because having the finishing step allows for the ability to have greater control over the thickness of the wafer [Kajiyama, page 4, pp 0049 – page 5, pp 0051, summarized].
Regarding claim 3, Kawase as modified further discloses the manufacturing method of the semiconductor device according to claim 1, further comprising processing, based on an expected shape of the second surface of the semiconductor substrate after the first grinding, a table for supporting the first surface of the semiconductor substrate in the second grinding [Kajiyama, fig 4, a table 70 is provided for the rough and finish grinding apparatus’ 80a and 80b].
Regarding claim 10, Kawase as modified further discloses the manufacturing method of the semiconductor device according to claim 1, but does not explicitly disclose wherein a grinding depth in the first grinding is smaller than a grinding depth in the second grinding.
Kajiyama further teaches the finishing grinding and rough grinding apparatuses are the same expect the grindstones are different [Kajiyama, page 4, pp 0043], where the type of grindstones affects the amount removed and rate of removal based upon user inputs such as grinding time being the difference in grinding depth.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the use of the device of Kawase to change the order of the finishing grinding and rough grinding times such that the first grinding is smaller than a grinding depth in the second grinding since it has been held that “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results” [MPEP 2144.04(IV)(C)]. In the instant case, the device of Kawase as modified would not operate differently with the claimed grinding depths/grinding times since the grinding times can be adjusted and reversed, the device would function appropriately having the claimed order.
Claims 2, 7-9, 14, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kawase et al (Japanese Patent Publication No. JP2013021017), as evidenced by the machine translation of Kawase, in view of Kajiyama et al (US PGPUB No. 2009/001623) as applied to claim 1 above, and in further view of Sugiya et al (US PGPUB No. 2014/0183163), hereinafter referred to as Kawase, Kajiyama, and Sugiya, respectively.
Regarding claim 2, Kawase as modified discloses the manufacturing method of the semiconductor device according to claim 1, but does not explicitly disclose wherein in the second grinding, in order to leave a convex part in an outer circumference of the semiconductor substrate, an inside of the convex part is ground.
Sugiya teaches a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising: grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface [Sugiya, fig 1, 10 grinds 1 which is opposite the surface being held by 20]; wherein in the grinding, in order to leave a convex part in an outer circumference of the semiconductor substrate, an inside of the convex part is ground [Sugiya, fig 5, shape b, and fig 6b, surface 1c is ground].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the shape of the table surface as taught by Sugiya so that the surface of the wafer is ground as shown in Sugiya on the table surface and shape of the wafer of Kawase as modified because this allows for the grinding to compensate for errors in the etching rate which is harder to control flatness during the etching [Sugiya, page 1, pp’s 0005-0006, summarized].
Regarding claims 7, 18, and 19, Kawase as modified discloses the manufacturing method of the semiconductor device according to claims 1, 2, and 3, respectively, but does not explicitly disclose wherein in the second grinding, regarding a table for supporting the first surface of the semiconductor substrate, in a portion overlapping with the first surface of the semiconductor substrate, a height of an upper surface monotonously decreases from a center part of the portion to an end part of the portion.
Sugiya teaches a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising: grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface [Sugiya, fig 1, 10 grinds 1 which is opposite the surface being held by 20]; wherein in the grinding, regarding a table for supporting the first surface of the semiconductor substrate, in a portion overlapping with the first surface of the semiconductor substrate, a height of an upper surface monotonously decreases from a center part of the portion to an end part of the portion [Sugiya, fig 2, surface 22a is a straight slope from the center 20a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the shape of the table surface as taught by Sugiya so that the surface of the wafer is ground as shown in Sugiya on the table surface and shape of the wafer of Kawase as modified in the second grinding because this allows for the grinding to compensate for errors in the etching rate which is harder to control flatness during the etching [Sugiya, page 1, pp’s 0005-0006, summarized].
Regarding claim 8, Kawase as modified discloses the manufacturing method of the semiconductor device according to claim 3, but does not explicitly disclose wherein a maximum value of a difference in heights of the table is 0.004% or less of a diameter of the semiconductor substrate.
Sugiya teaches a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising: grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface [Sugiya, fig 1, 10 grinds 1 which is opposite the surface being held by 20]; wherein a maximum value of a difference in heights of the table is 0.004% or less of a diameter of the semiconductor substrate [Sugiya, page 2, pp 0026, 0.0001 to 0.001 degree difference in height, where the table is substantially similar to the size of the wafer, such that the height of the wafer is thus 0.0001 to 0.001 percent of the height of the wafer, which makes this range overlap and per MPEP 2144.05(I) when the range overlaps a prima facie case of obviousness exists].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the shape of the table surface as taught by Sugiya so that the surface of the wafer is ground as shown in Sugiya on the table surface and shape of the wafer of Kawase as modified having maximum value of heights between the diameter of the substrate because this allows for the grinding to compensate for errors in the etching rate which is harder to control flatness during the etching [Sugiya, page 1, pp’s 0005-0006, summarized].
Regarding claim 9, Kawase as modified discloses the manufacturing method of the semiconductor device according to claim 1, but does not explicitly disclose wherein in the first grinding, regarding a table for supporting the first surface of the semiconductor substrate, in a portion overlapping with the first surface of the semiconductor substrate, a height of an upper surface monotonously decreases from a center part of the portion to an end part of the portion.
Sugiya teaches a manufacturing method of a semiconductor device comprising a semiconductor substrate, the manufacturing method of the semiconductor device comprising: grinding a second surface of the semiconductor substrate that is a surface on an opposite side of the first surface [Sugiya, fig 1, 10 grinds 1 which is opposite the surface being held by 20]; wherein in the grinding, regarding a table for supporting the first surface of the semiconductor substrate, in a portion overlapping with the first surface of the semiconductor substrate, a height of an upper surface monotonously decreases from a center part of the portion to an end part of the portion [Sugiya, fig 2, surface 22a is a straight slope from the center 20a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used the shape of the table surface as taught by Sugiya so that the surface of the wafer is ground as shown in Sugiya on the table surface and shape of the wafer of Kawase as modified in the first grinding because this allows for the grinding to compensate for errors in the etching rate which is harder to control flatness during the etching [Sugiya, page 1, pp’s 0005-0006, summarized].
Regarding claim 14, Kawase as modified further discloses the manufacturing method of the semiconductor device according to claim 2, further comprising processing, based on an expected shape of the second surface of the semiconductor substrate after the first grinding, a table for supporting the first surface of the semiconductor substrate in the second grinding [Kajiyama, fig 4, a table 70 is provided for the rough and finish grinding apparatus’ 80a and 80b].
Allowable Subject Matter
Claims 4-6, 11-13, 15-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4, 15, 16, Sugiya et al (US PGPUB No. 2014/0183163) teaches a table to hold a substrate during grinding [Sugiya, fig 2, 20] comprising a shape having a peak in the middle and a sloped surface [Sugiya, fig 2, 22 has sloped surface 22a to the middle 20a]. However, Sugiya does not teach different shapes of the table for the different grinding shapes, but rather uses the same table in various orientations with respect to the grinder to achieve the shape of the wafer.
The prior art considered as a whole, alone or in combination, neither anticipates nor renders obvious “a table for supporting the first surface of the semiconductor substrate has, in a portion overlapping with the first surface of the semiconductor substrate, a valley part between a center part of the portion and an end part of the portion” together in combination with the rest of the limitations of the claim and in the independent claim.
Claim(s) 5-6, 17 and 20 would be allowed as being dependent on claim 4.
Regarding claim 11, Kawase et al (Japanese Patent Publication No. JP2013021017) teaches the flattening of the tape [Kawase, claim 1]. However, Kawase is silent regarding the deterioration of the flattener based upon condition of the surface.
Sugiya (Chinese Patent Publication No. CN102848305) as evidenced by the machine translation of Sugiya, teaches a flattener to flatten tape on a substrate surface [Sugiya, fig 8, 58b flattens 40 to surface 40b]. However, Sugiya is silent regarding the deterioration of the flattener based upon condition of the surface.
The prior art considered as a whole, alone or in combination, neither anticipates nor renders obvious “estimating, by acquiring appearance information on a front surface of the protection tape after the cutting of the protection tape, deterioration of a flattening tool in the cutting the protection tape from the appearance information” together in combination with the rest of the limitations of the claim and in the independent claim. The Office notes that the term “estimating” is interpreted to be a definite term since the estimating is based upon set conditions that one of ordinary skill in the art would be able to recognize deteriorate the cutting performance of the tape, and in light of the disclosure, is done using equipment.
Claim(s) 12-13 would be allowed as being dependent on claim 11.
Conclusion
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/ROBERT F NEIBAUR/Primary Examiner, Art Unit 3723